USRE40113E1 - Method for fabricating gate oxide - Google Patents

Method for fabricating gate oxide Download PDF

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USRE40113E1
USRE40113E1 US10/246,826 US24682602A USRE40113E US RE40113 E1 USRE40113 E1 US RE40113E1 US 24682602 A US24682602 A US 24682602A US RE40113 E USRE40113 E US RE40113E
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gate oxide
nitrogen
fabricating
moisture
volume
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US10/246,826
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Yu-Shan Tai
H. T. Yang
Hsueh-Hao Shih
Kuen-Chu Chen
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United Microelectronics Corp
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United Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/3167—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself of anodic oxidation
    • H01L21/31675—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself of anodic oxidation of silicon

Definitions

  • This invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating gate oxide, which improves the electrical quality of a gate oxide layer.
  • gate oxide is one of the important components in a metal-oxide-semiconductor (MOS) device
  • MOS metal-oxide-semiconductor
  • the electrical quality of the gate oxide directly affects the quality of a MOS device.
  • a wet oxidation process is usually performed on a gate oxide layer that exceeds 200 ⁇ in thickness.
  • VLSI very-large-semiconductor-integration
  • the gate oxide layer used in a MOS device which has a thickness of about 100-200 ⁇ , is normally formed by a dry oxidation process in the presence of C 2 H 2 Cl 2 vapor.
  • gate oxide is thinner than 100 ⁇ , perhaps even as thin as about 50 ⁇ , such as the tunneling oxide within a flash memory, the method for fabricating gate oxide is normally a dry oxidation. However, if the required thickness of the gate oxide is thinner than 50 ⁇ , it is very difficult to obtain a high-quality gate oxide layer through a conventional oxidation process.
  • an oxidation process is performed on a provided silicon substrate in step 10 .
  • a gate oxide layer is formed on the silicon substrate by performing a thermal oxidation in an environment filled with oxygen at a temperature of about 900°-100° C.
  • an annealing process is performed in an environment filled with gas, such as nitrogen or inert gases, at a temperature of about 900°-1100° C. This eliminates the stress within the gate oxide layer caused by defects.
  • a gate oxide layer with a thickness of about 40 ⁇ formed by the foregoing method has a measured breakdown charge (Q bd ) equal to or less than 5 coulombs per square centimeter.
  • Q bd measured breakdown charge
  • a measured leakage current through the gate oxide layer is about 34.6 ⁇ 10 ⁇ 8 amperes under a 3.2-volt gate voltage. This shows that the electrical quality of the thin gate oxide is not acceptable
  • the invention provides a method for fabricating gate oxide that includes providing a silicon substrate, performing an oxidation process, and performing an annealing process.
  • the oxidation process includes a dilute wet oxidation in an environment filled with oxygen, moisture, and nitrogen at a temperature of about 750°-900° C. to form a gate oxide layer over the substrate, wherein the volume of filled nitrogen is about 6 to 12 20 times of the volume of filled moisture.
  • the gas used in the annealing process includes nitrogen at a temperature of about 800°-1200° C.
  • FIG 1 is a flowchart showing a conventional method for fabricating gate oxide
  • FIG 2 is a flowchart showing the method for fabricating gate oxide of a preferred embodiment according to the invention.
  • FIG 2 is a flowchart showing the method for fabricating gate oxide according to the invention.
  • FIG. 2 shows step 110 , in which a dilute wet oxidation process is performed in a environment filled with oxygen, moisture, and dilute gas at a temperature of about 750°-900° C. to form a gate oxide layer.
  • the dilute gas includes inert gas such as nitrogen.
  • the volume of the dilute gas is about 6-126-20 times of the volume of the moisture.
  • an annealing process is performed on the gate oxide layer to eliminate the stress within the gate oxide layer caused by defects within the gate oxide.
  • the annealing process is performed in the presence of a gas, such as N 2 O, NO, or other nitrogen base gases, at a temperature of about 800°-1200° C.
  • the gate oxide with a thickness of about 40 ⁇ formed by the method of the foregoing preferred embodiment according to the invention has a measured Q bd equal to or less than 15 Coulombs per square centimeter. This is about three times that of a conventional gate oxide.
  • Such a gate oxide also has a leakage current of about 16 ⁇ 10 ⁇ 8 amperes under a gate voltage of 3 2 volts, which is about half the leakage current of a conventional gate oxide.
  • the method for fabricating gate oxide according to the invention improves the electrical quality of gate oxide by raising the Q bd and reducing the leakage current.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A method for fabricating gate oxide includes a dilute wet oxidation process with additional nitrogen and moisture and an annealing process with a nitrogen base gas, wherein the volume of additional nitrogen is about 6-12 6-20 times of the volume of the additional moisture. The method according to the invention improves the electrical quality of the gate oxide by raising the Qbd and by reducing the leakage current of the gate oxide.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 87112101, filed Jul. 24, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND Of THE INVENTION
1. Field of the Invention:
This invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating gate oxide, which improves the electrical quality of a gate oxide layer.
2. Description of Related Art:
Since gate oxide is one of the important components in a metal-oxide-semiconductor (MOS) device, the electrical quality of the gate oxide directly affects the quality of a MOS device. Conventionally, a wet oxidation process is usually performed on a gate oxide layer that exceeds 200 Å in thickness. In a current very-large-semiconductor-integration (VLSI) process, the gate oxide layer used in a MOS device, which has a thickness of about 100-200 Å, is normally formed by a dry oxidation process in the presence of C2H2Cl2 vapor.
If the required thickness of gate oxide is thinner than 100 Å, perhaps even as thin as about 50 Å, such as the tunneling oxide within a flash memory, the method for fabricating gate oxide is normally a dry oxidation. However, if the required thickness of the gate oxide is thinner than 50 Å, it is very difficult to obtain a high-quality gate oxide layer through a conventional oxidation process.
As shown in FIG. 1, which is a flowchart represents a conventional method for fabricating gate oxide, an oxidation process is performed on a provided silicon substrate in step 10. A gate oxide layer is formed on the silicon substrate by performing a thermal oxidation in an environment filled with oxygen at a temperature of about 900°-100° C. Then, in step 20, an annealing process is performed in an environment filled with gas, such as nitrogen or inert gases, at a temperature of about 900°-1100° C. This eliminates the stress within the gate oxide layer caused by defects.
A gate oxide layer with a thickness of about 40 Å formed by the foregoing method has a measured breakdown charge (Qbd) equal to or less than 5 coulombs per square centimeter. A measured leakage current through the gate oxide layer is about 34.6×10−8 amperes under a 3.2-volt gate voltage. This shows that the electrical quality of the thin gate oxide is not acceptable
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for fabricating gate oxide that improves the electrical quality of a gate oxide by raising the Qbd and reducing the leakage current of the gate oxide layer.
In accordance with the foregoing objective of the present invention, the invention provides a method for fabricating gate oxide that includes providing a silicon substrate, performing an oxidation process, and performing an annealing process. The oxidation process includes a dilute wet oxidation in an environment filled with oxygen, moisture, and nitrogen at a temperature of about 750°-900° C. to form a gate oxide layer over the substrate, wherein the volume of filled nitrogen is about 6 to 12 20 times of the volume of filled moisture. The gas used in the annealing process includes nitrogen at a temperature of about 800°-1200° C.
BRIEF DESCRIPTION OF DRAWINGS
The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
FIG 1 is a flowchart showing a conventional method for fabricating gate oxide; and
FIG 2 is a flowchart showing the method for fabricating gate oxide of a preferred embodiment according to the invention.
 DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The invention provides a new method for fabricating gate oxide. FIG 2 is a flowchart showing the method for fabricating gate oxide according to the invention.
FIG. 2 shows step 110, in which a dilute wet oxidation process is performed in a environment filled with oxygen, moisture, and dilute gas at a temperature of about 750°-900° C. to form a gate oxide layer. The dilute gas includes inert gas such as nitrogen. The volume of the dilute gas is about 6-126-20 times of the volume of the moisture. Then, an annealing process is performed on the gate oxide layer to eliminate the stress within the gate oxide layer caused by defects within the gate oxide. The annealing process is performed in the presence of a gas, such as N2O, NO, or other nitrogen base gases, at a temperature of about 800°-1200° C.
The gate oxide with a thickness of about 40 Å formed by the method of the foregoing preferred embodiment according to the invention has a measured Qbd equal to or less than 15 Coulombs per square centimeter. This is about three times that of a conventional gate oxide. Such a gate oxide also has a leakage current of about 16×10−8 amperes under a gate voltage of 3 2 volts, which is about half the leakage current of a conventional gate oxide.
It is obvious that the method for fabricating gate oxide according to the invention improves the electrical quality of gate oxide by raising the Qbd and reducing the leakage current.
The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements

Claims (5)

1. A method for fabricating gate oxide, the method comprising:
providing a silicon substrate;
forming the gate oxide by performing a dilute wet oxidation process with additional nitrogen and moisture, wherein the nitrogen has a volume of about 6 to 12 20 times the moisture's volume; and
performing an annealing process with a nitrogen base gas on the gate oxide.
2. The method of claim 1, wherein the dilute wet oxidation is performed at a first temperature of about 750°-900° C.
3. The method of claim 1, wherein the annealing process is performed at a second temperature of about 800°-1200° C.
4. The method of claim 1, wherein the nitrogen base gas includes N2O.
5. The method of claim 1, wherein the nitrogen base gas includes NO.
US10/246,826 1998-07-24 2002-09-17 Method for fabricating gate oxide Expired - Lifetime USRE40113E1 (en)

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TW87112101 1998-07-24
US09/191,913 US6121095A (en) 1998-07-24 1998-11-13 Method for fabricating gate oxide
US10/246,826 USRE40113E1 (en) 1998-07-24 2002-09-17 Method for fabricating gate oxide

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US6223165B1 (en) * 1999-03-22 2001-04-24 Keen.Com, Incorporated Method and apparatus to connect consumer to expert
US6784053B2 (en) * 2001-07-16 2004-08-31 Macronix International Co., Ltd. Method for preventing bit line to bit line leakage in memory cell
KR100426484B1 (en) * 2001-12-22 2004-04-14 주식회사 하이닉스반도체 Flash memory cell and method of manufacturing the same
US7709403B2 (en) * 2003-10-09 2010-05-04 Panasonic Corporation Silicon carbide-oxide layered structure, production method thereof, and semiconductor device
CN103681456A (en) * 2013-10-23 2014-03-26 上海华力微电子有限公司 Method for reducing critical dimension loss in HARP (High Aspect Ratio Process) film annealing

Citations (7)

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US4975387A (en) * 1989-12-15 1990-12-04 The United States Of America As Represented By The Secretary Of The Navy Formation of epitaxial si-ge heterostructures by solid phase epitaxy
US5096842A (en) * 1988-05-16 1992-03-17 Kabushiki Kaisha Toshiba Method of fabricating bipolar transistor using self-aligned polysilicon technology
US5656516A (en) * 1994-06-03 1997-08-12 Sony Corporation Method for forming silicon oxide layer
US5854505A (en) * 1992-12-25 1998-12-29 Sony Corporation Process for forming silicon oxide film and gate oxide film for MOS transistors
JPH11116903A (en) * 1997-10-20 1999-04-27 Sekisui Chem Co Ltd Photocurable adhesive sheet
US5902452A (en) * 1997-03-13 1999-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method for etching silicon surface
JPH11212821A (en) * 1998-01-22 1999-08-06 Nec Corp Trace data gathering system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5096842A (en) * 1988-05-16 1992-03-17 Kabushiki Kaisha Toshiba Method of fabricating bipolar transistor using self-aligned polysilicon technology
US4975387A (en) * 1989-12-15 1990-12-04 The United States Of America As Represented By The Secretary Of The Navy Formation of epitaxial si-ge heterostructures by solid phase epitaxy
US5854505A (en) * 1992-12-25 1998-12-29 Sony Corporation Process for forming silicon oxide film and gate oxide film for MOS transistors
US5656516A (en) * 1994-06-03 1997-08-12 Sony Corporation Method for forming silicon oxide layer
US5902452A (en) * 1997-03-13 1999-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method for etching silicon surface
JPH11116903A (en) * 1997-10-20 1999-04-27 Sekisui Chem Co Ltd Photocurable adhesive sheet
JPH11212821A (en) * 1998-01-22 1999-08-06 Nec Corp Trace data gathering system

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