CN103681456A - Method for reducing critical dimension loss in HARP (High Aspect Ratio Process) film annealing - Google Patents
Method for reducing critical dimension loss in HARP (High Aspect Ratio Process) film annealing Download PDFInfo
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- CN103681456A CN103681456A CN201310505326.5A CN201310505326A CN103681456A CN 103681456 A CN103681456 A CN 103681456A CN 201310505326 A CN201310505326 A CN 201310505326A CN 103681456 A CN103681456 A CN 103681456A
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- Prior art keywords
- critical size
- loss
- thin
- wet oxidation
- oxidation process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention belongs to the technical field of semiconductor device manufacture, and relates to a method for film annealing, especially to a method for reducing the critical dimension loss in HARP film annealing. N2 or inert gas is introduced in the wet oxidation process. The method of the invention has the advantages that gaps in HARP films can be eliminated, the oxidation speed in the wet oxidation process is reduced, and silicon consumption of the active area in the wet oxidation process is decreased; and thus, the critical dimension loss of the active area is decreased, and the yield rate of semiconductor devices is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to the method for Thin-film anneal, specifically a kind of method that reduces critical size loss in high depth trench fill Thin-film anneal.
Background technology
Development along with semiconductor technology, for higher capacity and the performance that improves better device, STI(Shallow Trench Isolation, shallow trench isolation from) depth-to-width ratio of the groove of technique is more and more large, processing procedure below 65nm, groove adopts the high depth trench fill of HARP(mostly) process deposits film, but after thin film deposition completes, need Anneal(annealing) eliminate issuable thin film void in deposition process, but in annealing process, can cause AA district (ActiveArea, active area) loss CD(Critical Dimension, critical size).
And in existing annealing process, cause two parts that have of AA district CD loss, Wet Oxide(wet oxidation) oxidation and the N of process
2the oxidation of the OH key that film in annealing process is residual, wherein part is above occupied an leading position.Silicon in wet oxidation process ZhongAA district is consumed in a large number, causes the severe attrition of LiaoAA district CD, and the CD in ErAA district is very crucial in semiconductor device, has even had influence on the yield of product.
Chinese patent (publication number: the preparation method who CN102420141A) discloses a kind of fleet plough groove isolation structure with polycrystalline sacrificial liner layer, wherein, comprise the steps: step a, form an initial composite structure, described initial composite structure comprises Semiconductor substrate, be covered in the oxide-film in described Semiconductor substrate, the patterning groove that is covered in one deck silicon nitride liner on described oxide-film and forms on said structure; Step b, cover layer of oxide layer with described trench wall and bottom, described oxide layer and described initial composite structure form the first composite construction.This beneficial effect of the invention is, the silicon that has reduced active area by introducing poly semiconductor sacrificial liner layer consumes, make in successive process critical size in controllable state, by dry method, anneal and make high-aspect-ratio process filling film shrink the elongation strain of generation silicon to strengthen the mobility of charge carrier simultaneously, improve the performance of device.
Chinese patent (publication number: CN102437083A) disclose a kind of method that reduces critical dimension loss of high aspect ratio process filling shallow isolation trench, by adopting nitric oxide to the nitrogen treatment of the silicon oxide liner bed course of initial growth or using the mixed oxidization of nitric oxide/oxygen to silicon face, in silicon oxide liner bed course, form the silicon oxynitride film of one deck densification, thereby strengthened the blocking capability of silicon oxide liner bed course for steam, with reduce high-aspect-ratio technique the loss that must densification process active area live width be caused, and can reasonably control cost, increased accordingly process window.
Although above-mentioned two patents all disclose the method that reduces active area critical size loss, do not relate in annealing process, therefore, the technical scheme of employing is also completely different with the present invention.
Summary of the invention
Problem for above-mentioned existence, the present invention discloses a kind of method that reduces critical size loss in high depth trench fill Thin-film anneal, to overcome the silicon in the wet oxidation process ZhongAA district of high depth trench fill Thin-film anneal technique in prior art, consumed in a large number, caused the severe attrition problem of AA district CD.
To achieve these goals, the present invention adopts following technical scheme:
A method that reduces critical size loss in high depth trench fill Thin-film anneal wherein, passes into N in wet oxidation process
2or inert gas.
The method of critical size loss in the high depth trench fill of above-mentioned minimizing Thin-film anneal, wherein, also passes into H in described wet oxidation process
2/ O
2gas.
The method of critical size loss in the high depth trench fill of above-mentioned minimizing Thin-film anneal, wherein, described wet oxidation process is carried out in boiler tube, described N2 or inert gas and described H
2/ O
2gas passes into described boiler tube simultaneously.
The method of critical size loss in the high depth trench fill of above-mentioned minimizing Thin-film anneal, wherein, H described in described N2 or inert gas dilution
2/ O
2gas, to reduce the oxidation rate in described wet oxidation process, reduces the silicon consumption of active area in described wet oxidation process, thereby reduces the loss of active area critical size.
The method of critical size loss in the high depth trench fill of above-mentioned minimizing Thin-film anneal, wherein, when technology node is 65/55nm, described N
2or the flow of inert gas is greater than 0slm, and be less than or equal to 20slm.
The method of critical size loss in the high depth trench fill of above-mentioned minimizing Thin-film anneal, wherein, when technology node is 45/40nm, described N
2or the flow of inert gas is greater than 0slm, and be less than or equal to 15slm.
The method of critical size loss in the high depth trench fill of above-mentioned minimizing Thin-film anneal, wherein, described H
2/ O
2h in gas
2and O
2flow-rate ratio be 7:5.
The method of critical size loss in the high depth trench fill of above-mentioned minimizing Thin-film anneal, wherein, described inert gas adopts He or Ar.
Tool of the present invention has the following advantages or beneficial effect:
Adopt method of the present invention, both can meet the space of eliminating in high depth trench fill film, also can reduce the oxidation rate in wet oxidation process simultaneously, the silicon consumption of active area in wet oxidation process is reduced, thereby reduce the loss of active area critical size, promote the yield of semiconductor device.
Embodiment
Below in conjunction with specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
The first embodiment of the present invention relates to a kind of method that reduces critical size loss in high depth trench fill Thin-film anneal, wherein, passes into N in wet oxidation process
2, also pass into H simultaneously
2/ O
2gas.Wet oxidation process is carried out in boiler tube, N
2and H
2/ O
2gas passes into boiler tube simultaneously (only has H in prior art
2/ O
2gas passes into boiler tube).Due to N
2dilution H
2/ O
2gas, reduces the oxidation rate in wet oxidation process, and the silicon consumption of active area in wet oxidation process is reduced, thereby reduces the loss of active area critical size.
But on the other hand, owing to only passing into H in the wet oxidation process of prior art Central Plains
2/ O
2gas, in the present embodiment owing to having increased N
2, the overall gas flow in boiler tube is increased, so, will accelerate the accessory substance H of OH key oxidation in high depth trench fill film
2taking out of O(4OH+SI->SiO2+2H2O), has promoted oxidation to carry out indirectly, thereby accelerates the silicon consumption in AA region.
Therefore, must guarantee that the oxidation rate reducing in wet oxidation process is more than the OH key oxidation rate of accelerating in high depth trench fill film.This just must control N
2flow, for the product of any structure, have a N
2range of flow.When technology node is 65/55nm, N
2flow be greater than 0slm, and be less than or equal to 20slm.When technology node is 45/40nm, N
2flow be greater than 0slm, and be less than or equal to 15slm.N
2flow only in above-mentioned scope, guarantee reduces the loss of active area critical size.
The semiconductor device of 55nm of take is example, H in boiler tube
2/ O
2flow in gas is H
2: O
2=7slm:5slm, the time of wet oxidation process is 63min, gets respectively and does not pass into N
2(being 0slm) and pass into N
2flow is 7.5slm, 10slm, 12.5slm, five flow values of 20slm, measures active area critical size, sees table 1:
Table 1
As can be seen from Table 1, do not passing into N
2time, the loss of active area critical size is serious, and passes into N
2after can reduce the loss of active area critical size.Best, at N
2when flow is 7.5slm, can reduce to greatest extent the loss of active area critical size, promote the yield of semiconductor device.
The second embodiment of the present invention relates to a kind of method that reduces critical size loss in high depth trench fill Thin-film anneal.The second embodiment and the first embodiment are roughly the same, and main distinction part is: in the first embodiment, pass into N in wet oxidation process
2.And in second embodiment of the invention, in wet oxidation process, pass into inert gas, preferably, inert gas adopts He or Ar.In addition, the correlation technique details of mentioning in the first execution mode is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first execution mode.
In addition it will be understood by those skilled in the art that no matter be N,
2or inert gas, in boiler tube, carry out in wet oxidation process, not can with H
2/ O
2gas generation chemical reaction, therefore for dilution H
2/ O
2gas can play good effect, effectively reduces the oxidation rate in wet oxidation process, and the silicon consumption of active area in wet oxidation process is reduced, thereby reduces the loss of active area critical size.
The technology node of the present invention's application is 65/55nm or 45/40nm, and the technology platform of application is Logic, Memory, RF, HV, Analog/Power, MEMS, CIS, Flash or eFlash.
It should be appreciated by those skilled in the art that those skilled in the art can realize described variation example in conjunction with prior art and above-described embodiment, such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (8)
1. reduce a method for critical size loss in high depth trench fill Thin-film anneal, it is characterized in that, in wet oxidation process, pass into N
2or inert gas.
2. the method for critical size loss in the high depth trench fill of minimizing according to claim 1 Thin-film anneal, is characterized in that, also passes into H in described wet oxidation process
2/ O
2gas.
3. the method for critical size loss in the high depth trench fill of minimizing according to claim 2 Thin-film anneal, is characterized in that, described wet oxidation process is carried out in boiler tube, described N
2or inert gas and described H
2/ O
2gas passes into described boiler tube simultaneously.
4. the method for critical size loss in the high depth trench fill of minimizing according to claim 3 Thin-film anneal, is characterized in that described N
2or H described in inert gas dilution
2/ O
2gas, to reduce the oxidation rate in described wet oxidation process, reduces the silicon consumption of active area in described wet oxidation process, thereby reduces the loss of active area critical size.
5. according to the method for critical size loss in the high depth trench fill of the minimizing Thin-film anneal described in claim 1-4 any one, it is characterized in that, when technology node is 65/55nm, described N
2or the flow of inert gas is greater than 0slm, and be less than or equal to 20slm.
6. according to the method for critical size loss in the high depth trench fill of the minimizing Thin-film anneal described in claim 1-4 any one, it is characterized in that, when technology node is 45/40nm, described N
2or the flow of inert gas is greater than 0slm, and be less than or equal to 15slm.
7. according to the method for critical size loss in the high depth trench fill of the minimizing Thin-film anneal described in claim 2-4 any one, it is characterized in that described H
2/ O
2h in gas
2and O
2flow-rate ratio be 7:5.
8. according to the method for critical size loss in the high depth trench fill of the minimizing Thin-film anneal described in claim 1-4 any one, it is characterized in that, described inert gas adopts He or Ar.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310505326.5A CN103681456A (en) | 2013-10-23 | 2013-10-23 | Method for reducing critical dimension loss in HARP (High Aspect Ratio Process) film annealing |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310505326.5A CN103681456A (en) | 2013-10-23 | 2013-10-23 | Method for reducing critical dimension loss in HARP (High Aspect Ratio Process) film annealing |
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| CN103681456A true CN103681456A (en) | 2014-03-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108447770A (en) * | 2018-03-08 | 2018-08-24 | 清华大学 | The preparation method of silica membrane |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121095A (en) * | 1998-07-24 | 2000-09-19 | United Integrated Circuits Corp. | Method for fabricating gate oxide |
| CN101416296A (en) * | 2006-04-07 | 2009-04-22 | 应用材料股份有限公司 | Multi-step anneal of thin films for film densification and improved gap-fill |
| CN101635270A (en) * | 2008-07-25 | 2010-01-27 | 台湾积体电路制造股份有限公司 | Sti film property using sod post-treatment |
-
2013
- 2013-10-23 CN CN201310505326.5A patent/CN103681456A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121095A (en) * | 1998-07-24 | 2000-09-19 | United Integrated Circuits Corp. | Method for fabricating gate oxide |
| CN101416296A (en) * | 2006-04-07 | 2009-04-22 | 应用材料股份有限公司 | Multi-step anneal of thin films for film densification and improved gap-fill |
| CN101635270A (en) * | 2008-07-25 | 2010-01-27 | 台湾积体电路制造股份有限公司 | Sti film property using sod post-treatment |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108447770A (en) * | 2018-03-08 | 2018-08-24 | 清华大学 | The preparation method of silica membrane |
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Application publication date: 20140326 |