JP5720244B2 - Semiconductor substrate manufacturing method and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor substrate manufacturing method and a semiconductor device manufacturing method.

  In a MOS (Metal Oxide Semiconductor) transistor formed on a silicon substrate, an SOI (Silicon On Insulator) substrate is used in order to reduce junction capacitance and reduce leakage current. In the SOI substrate, an insulating layer made of silicon oxide or the like is formed on a silicon substrate, and a silicon layer is further formed on the insulating layer. Since a MOS transistor is formed on a silicon layer formed on an insulating layer, the silicon layer is required to be a single crystal, but it is extremely difficult to form a single crystal silicon film on the insulating layer. Have difficulty. Therefore, a local SOI structure in which an insulating film is formed in part of the source and drain regions and the like has been developed, and a technique related to a semiconductor device such as a MOS transistor having such a local SOI structure is disclosed (for example, Patent Documents 1 and 2, Non-Patent Documents 1 and 2).

JP 2005-183987 A JP 2008-112900 A

Kyoung H. Y., et al. IEEE Electron Device Letters. Vol. 25, No. 6, June 2004 T. Yamazaki, et al. Materials Science in Semiconductor Processing 8 2005 59-63

  A semiconductor device having such a local SOI structure is manufactured by the following manufacturing method. First, as shown in FIG. 1A, in a silicon (Si) substrate 410 in a region where an STI (Shallow Trench Isolation) 411 formed of silicon oxide, a gate electrode 412, and a sidewall 413 are not formed. Remove the silicon. Specifically, in the silicon substrate 410, silicon in a region other than the region where the STI 411, the gate electrode 412 and the sidewall 413 are formed is removed by etching to a depth where an insulating film for forming the Local SOI structure is formed. To do. Note that a gate insulating film 419 is formed immediately below the gate electrode 412.

  Next, as shown in FIG. 1B, a SiGe layer 414 and a silicon (Si) layer 415 are sequentially formed by epitaxial growth in the region where the silicon is removed. In this manner, a single crystal silicon film can be formed by forming the silicon layer 415 by epitaxial growth. In the specification of the present application, SiGe means Si including Ge, and includes Si and Ge whose composition ratio is not 1: 1. Moreover, what has another component other than Si and Ge, and the thing containing the dopant which provides electroconductivity are included.

  Next, as shown in FIG. 1C, the silicon oxide forming the STI 411 is removed to a depth where the SiGe layer 414 is formed. That is, the silicon oxide forming the STI 411 is removed until the side surface of the SiGe layer 414 is exposed.

  Next, as shown in FIG. 2A, only the SiGe layer 411 is selectively removed by wet etching or the like to form an opening region 416 that is substantially parallel to the substrate surface of the silicon substrate 410.

  Next, as shown in FIG. 2B, an insulating film 417 is formed in the opening region 416, and further, an STI insulating film 418 made of silicon oxide is formed on the STI 411 from which the silicon oxide has been removed. The STI 411 is formed of silicon oxide including the STI insulating film 418 formed as described above.

  Thereafter, an impurity diffusion region is formed by ion implantation into the silicon layer 415, and a drain electrode and a source electrode (not shown) are formed on the silicon layer 415, thereby manufacturing a semiconductor device having a Local SOI structure. Can do.

  As described above, the insulating film for forming the Local SOI structure is formed by forming the insulating film 417 in the opening region 416. The opening region 416 is formed as shown in FIG. The length W in the depth direction is longer than the width H of the inlet. For example, while the width H of the entrance of the opening region 416 is 50 nm, the length W in the depth direction is formed to be 10 μm, and the length ratio W / H in the depth direction to the width of the opening is 200. It becomes. FIG. 3 is a cross-sectional view taken along the alternate long and short dash line 2A-2B in FIG.

  As a method for forming the insulating film 417 in the opening region 416, a CVD (Chemical Vapor Deposition) method can be given. As shown in FIG. 4A, the silicon oxide film 421 to be the insulating film 417 in the opening region 416 is formed by film formation by CVD or the like. However, since the step coverage is not good in the film formation method by CVD or the like, the silicon oxide film 421 is formed relatively thick near the entrance of the opening region 416, but is extremely thin behind the opening region 416. The Therefore, the vicinity of the entrance of the opening region 416 is blocked by the deposited silicon oxide film 421, and particles contributing to the formation of the silicon oxide film 421 can enter the opening region 416. Therefore, the insulating film 417 cannot be formed over the entire opening region 416.

  Further, as shown in FIG. 4B, a method of forming a silicon oxide film 422 by thermal oxidation of silicon is conceivable. Specifically, the silicon substrate 410 and the silicon layer 415 that form the side surfaces of the opening region 416 are thermally oxidized to form a silicon oxide film 422 that becomes the insulating film 417. In this method, since oxygen for thermally oxidizing silicon enters the inside of the opening region 416 from the entrance of the opening region 416, the oxidation starts from the silicon near the entrance of the opening region 416. Therefore, since the volume of silicon expands due to oxidation of silicon to silicon oxide, the silicon in the vicinity of the entrance is oxidized to form silicon oxide, whereby the width of the entrance of the opening region 416 is gradually narrowed. As a result, the entrance of the opening region 416 is blocked. Accordingly, oxygen cannot enter the opening region 416, and the insulating film 417 cannot be formed in the entire opening region 416.

  Therefore, a semiconductor substrate manufacturing method capable of manufacturing a semiconductor substrate having a Local SOI structure in which an opening region is embedded with an insulating film at low cost is desired, and a junction capacitance is low and leakage current is low. A method for manufacturing a semiconductor device that can manufacture a small number of semiconductor devices at low cost is desired.

According to one aspect of the present embodiment, a semiconductor layer forming step of sequentially forming a layer made of the second semiconductor and a layer made of the first semiconductor by crystal growth on the substrate made of the first semiconductor; An opening region forming step of removing the second semiconductor layer from the side surface by etching to form an opening region; and an oxidation delay formed by a material including a nitride film, a carbide film, or an oxide film in the opening region. An oxidation delay film forming step of forming a film so that a film thickness at the entrance of the opening region is a predetermined film thickness; and the first semiconductor substrate and the first semiconductor layer And a thermal oxidation step of thermally oxidizing a part of the semiconductor 1 to form a thermal oxide film in the opening region.

According to another aspect of the present embodiment, a gate electrode forming step of forming a gate electrode on a substrate made of a first semiconductor, and a source and a drain are formed in the substrate made of the first semiconductor. A first semiconductor removing step of removing the first semiconductor in a predetermined depth to a predetermined depth; a layer made of a second semiconductor by crystal growth in the removed region from which the first semiconductor has been removed; and the first semiconductor A semiconductor layer forming step of sequentially forming the semiconductor layer, an opening region forming step of removing the second semiconductor layer by etching to form an opening region, and a nitride film and a carbide film in the opening region. Or an oxidation delay film forming step of forming an oxidation delay film formed of a material including an oxide film so that the film thickness at the entrance of the opening region is a predetermined film thickness, and the first semiconductor. substrate By a portion of said first semiconductor fine the first consisting of a semiconductor layer is thermally oxidized, the thermal oxidation process of forming a thermal oxide film on the opening area, the impurity in the layer consisting of the first semiconductor the diffusion regions are formed, have a, and an electrode forming step of forming a source and a drain in the impurity diffusion region, the substrate made of the first semiconductor, STI region made of an insulator has been formed, The gate electrode is formed in a region excluding the STI region, and the region in which the second semiconductor layer is formed as an insulator in the STI region after the semiconductor layer forming step. And the opening region forming step is performed after the step of removing the insulator in the STI region .
According to another aspect of the present embodiment, a gate electrode forming step of forming a gate electrode on a substrate made of a first semiconductor, and a source and a drain are formed in the substrate made of the first semiconductor. A first semiconductor removing step of removing the first semiconductor in a predetermined depth to a predetermined depth; a layer made of a second semiconductor by crystal growth in the removed region from which the first semiconductor has been removed; and the first semiconductor A semiconductor layer forming step for sequentially forming a layer made of the semiconductor, and an opening region in which the layer made of the second semiconductor is removed from the side surface by etching to form an opening region substantially parallel to the substrate made of the first semiconductor And forming an oxidation delay film formed of a material including a nitride film, a carbide film, or an oxide film in the opening region so that the film thickness at the entrance of the opening region is a predetermined thickness. acid A thermal oxide film is formed in the opening region by thermally oxidizing part of the first semiconductor of the retardation film forming step and the substrate made of the first semiconductor and the layer made of the first semiconductor. A thermal oxidation step; and an electrode formation step of forming an impurity diffusion region in the first semiconductor layer and forming a source and a drain on the impurity diffusion region.

  According to the semiconductor substrate manufacturing method and the semiconductor device manufacturing method disclosed in the present invention, since the formed opening region can be substantially completely filled with the insulating film in the semiconductor substrate having the local SOI structure, the highly reliable local SOI structure. This semiconductor substrate can be provided at low cost. Further, by using the substrate having the Local SOI structure, a semiconductor device with low junction capacitance and low leakage current can be provided at low cost.

Process diagram of manufacturing method of semiconductor device having local SOI structure (1) Process diagram of manufacturing method of semiconductor device having local SOI structure (2) Explanatory drawing of the opening area | region for forming Local SOI structure Explanatory drawing of the oxide film for forming Local SOI structure Process drawing (1) of the manufacturing method of the semiconductor substrate in 1st Embodiment Process drawing (2) of the manufacturing method of the semiconductor substrate in 1st Embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (3) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (4) of the manufacturing method of the semiconductor device in the first embodiment Process drawing of the manufacturing method of the semiconductor device in the first embodiment (5) Process drawing (6) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (7) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (8) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (9) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (3) Process drawing (4) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (5) Process drawing (1) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing of the manufacturing method of the semiconductor device in 3rd Embodiment (3) Process drawing (4) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing (5) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing (6) of the manufacturing method of the semiconductor device in 3rd Embodiment

  Modes for carrying out the invention will be described below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
(Semiconductor substrate manufacturing method)
As a method for manufacturing a semiconductor substrate in the present embodiment, a method for manufacturing a semiconductor substrate having a Local SOI structure will be described with reference to FIGS.

  First, as shown in FIG. 5A, a SiGe layer 11 and a silicon (Si) layer 12 are formed on a silicon substrate 10 by epitaxial growth. The silicon layer 13 formed by such epitaxial growth is a single crystal film. The SiGe layer 11 is formed to a thickness of 50 nm.

  Next, as shown in FIG. 5B, wet etching or the like is performed from the side surface of the SiGe layer 11 to remove the SiGe layer 11 from the side surface, and an opening region 13 having a width A is formed. The opening region 13 formed in this way is formed so as to be substantially parallel to the silicon substrate 10 and the silicon layer 12.

Next, as shown in FIG. 5C, an oxidation delay film 14 made of a silicon nitride film, a silicon carbide film, a silicon oxide film, or the like is formed from the surface of the silicon layer 12 by CVD. In the film formation method by CVD or the like, particles that contribute to film formation wrap around and the film is formed, but since the step coverage is not good, the entrance portion is formed thicker than the inside of the opening region 13. For example, when the oxidation delay film 14 made of silicon nitride is formed on the surface of the silicon layer 12 by CVD so that the film thickness B is about 20 nm, the film thickness C of the oxidation delay film 14 at the entrance of the opening region 13 is about 4 nm. In the opening region 13, the oxidation delay film 14 is formed thinner as it goes in the depth direction. Further, the oxidation delay film 14 is formed so as not to block the entrance of the opening region 13, and is formed near the entrance of the opening region 13 with respect to the width A of the opening region 13. 14 is formed so that the film thickness C is less than A / 2. Examples of the oxidation delay film 14 include a silicon or metal nitride film, a carbonized film, and an oxide film. Specifically, silicon nitride (Si ₃ N ₄ ), silicon carbide (SiC), silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum pentoxide (Ta ₂ O) ₅ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ) and the like. Examples of the method for forming the oxidation delay film 14 include plasma CVD, thermal CVD, sputtering, and vacuum deposition. In addition, before the above-described formation of the antioxidant film, for example, an oxidation process for forming silicon oxide (SiO ₂ ) with a thickness of 3 nm may be performed for the purpose of reducing film formation stress.

  Next, as shown in FIG. 6A, thermal oxidation of silicon is performed. Oxygen gas or the like for thermal oxidation enters the inside of the opening region 13 from the entrance of the opening region 13, but the oxidation delay film 14 is formed thick near the entrance of the opening region 13, so the rate of thermal oxidation is slow. This is because oxygen needs to diffuse through the oxidation retardation film 14 for silicon oxidation, but it takes a long time to diffuse because it is formed thick. On the other hand, since the oxidation delay film 14 is hardly formed or very thin in the depth of the opening region 13, the thermal oxidation rate is high. Therefore, as shown in the drawing, the oxidation of silicon proceeds from the inner part of the opening region 13 toward the inlet. Thereby, the silicon oxide film 15 by thermal oxidation is formed so as to fill the opening region 13 from the back of the opening region 13 toward the entrance.

  Next, as shown in FIG. 6B, by further performing thermal oxidation of silicon, the entire inside of the opening region 13 can be completely filled with the silicon oxide film 15 formed by thermal oxidation. In this manner, a semiconductor substrate having a Local SOI structure using the silicon oxide film 15 as an insulating film can be manufactured. In the semiconductor substrate having the Local SOI structure manufactured as described above, the silicon oxide film 15 which is an insulating film contains the nitrogen component and the like contained in the oxidation delay film 14 inside. Further, in the present embodiment, as shown in FIG. 5B, etching is performed from the side surface of the SiGe layer 11. However, the side surface of the SiGe layer 11 is not formed STI (not shown). Alternatively, the side surface of the SiGe layer 11 may be exposed by removing. Alternatively, a method of exposing the side surface of the SiGe layer 11 by etching in the depth direction of the silicon substrate 10 by RIE (Reactive Ion Etching) or the like may be used.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described.

  First, as shown in FIG. 7A, an STI region 21 made of silicon oxide for element isolation is formed on a silicon substrate 10.

  Next, as shown in FIG. 7B, a SiON film 22 having a thickness of 0.3 to 20 nm is formed on the surface of the silicon substrate 10 in a region where the STI region 21 is not formed. Specifically, the SiON film 22 is formed by performing thermal oxidation and thermal nitridation of silicon using NO gas. As another method for forming the SiON film 22, the SiO film is first formed by thermal CVD, then plasma treatment is performed in an atmosphere containing nitrogen gas, and then annealing is performed at 750 ° C. to 1100 ° C. The method of forming by may be sufficient.

  Next, as shown in FIG. 7C, a silicon film 23 and a silicon nitride film 24 are formed on the SiON film 22. The silicon film 23 is formed by depositing polysilicon or amorphous silicon to a thickness of 10 nm to 200 nm by thermal CVD or the like. The silicon nitride film 24 is formed by depositing silicon nitride in a thickness of 5 to 50 nm by thermal CVD. The silicon nitride film 24 is used as a hard mask in the etching process and may not be formed depending on the process or the like.

  Next, as shown in FIG. 8A, a resist pattern 25 is formed. Specifically, a photoresist pattern is formed on the silicon nitride film 24, and a resist pattern for forming a gate electrode to be described later is formed by performing exposure and development with an exposure apparatus.

Next, as shown in FIG. 8B, the silicon nitride film 24, the silicon film 23, and the SiON film 22 in the region where the resist pattern 25 is not formed are removed. Specifically, CF ₄ , CH ₃ F, Ar and O ₂ are introduced as etching gases and RIE is performed to remove the silicon nitride film 24 in the region where the resist pattern 25 is not formed. Next, using the silicon nitride film 24 in the region where the resist pattern 25 was formed as a mask, CF ₄ , Cl ₂ and N ₂ were introduced as etching gases and RIE was performed to remove the silicon nitride film 24. The silicon film 23 in the region is removed. The silicon film 23 remaining by this etching becomes a gate electrode. Further, using the silicon nitride film 24 in the region where the resist pattern 25 is formed as a mask, the SiON film 22 in the region where the silicon film 23 is removed is removed by RIE. The resist pattern 25 is removed by an organic solvent after the silicon nitride film 24 is etched.

  Next, as shown in FIG. 8C, a silicon nitride film 26 is formed to a thickness of about 20 nm by thermal CVD.

Next, as shown in FIG. 9A, CF ₄ , CH ₃ F, Ar, and O ₂ are introduced as etching gases and RIE is performed to remove the silicon nitride film 26 on the silicon substrate 10. A sidewall 26a made of silicon nitride is formed. Furthermore, by performing RIE by introducing CF ₄ , Cl ₂ and N ₂ as etching gases, the silicon in the silicon substrate 10 where silicon is exposed is selectively selected so that the depth D is about 100 nm. Remove. In this way, the removal region 27 is formed by removing a part of the silicon in the silicon substrate 10.

Next, as shown in FIG. 9B, the SiGe layer 11 and the silicon layer 12 are formed by epitaxial growth in the removal region 27 where the silicon is exposed in the silicon substrate 10. Specifically, SiH ₄ , DCS (Dichlorosilane: SiH ₂ Cl ₂ ), and GeH ₄ are introduced as source gases, the SiGe layer 11 is formed with a thickness of about 27 nm by CVD, and SiH ₄ or DCS is introduced as a source gas. The silicon layer 12 is formed with a thickness of about 60 nm by CVD. Since the silicon film 12 formed in this way is formed by epitaxial growth, it is a single crystal film of silicon.

Next, as shown in FIG. 9C, a part of silicon oxide forming the STI region 21 is selectively removed by performing wet etching using diluted hydrofluoric acid. The removal of the silicon oxide forming the STI region 21 is performed until the side surface of the SiGe layer 11 is exposed. As a method for removing the silicon oxide forming the STI region 21, silicon oxide (SiO ₂ ) is easily sublimated by a chemical reaction using a fluorine-based gas such as NF ₃ gas or NH ₄ F (NH ₄ ). _{After making 2} SiF ₅ , the temperature may be raised to about 200 ° C. to sublimate (NH ₄ ) ₂ SiF ₅ .

Next, as shown in FIG. 10A, the opening region 13 is formed by selectively removing the SiGe layer 11. Specifically, the SiGe layer 11 is etched from the side surface by thermal dry etching by introducing H ₂ and a chlorine-based gas such as HCl or Cl ₂ . This thermal dry etching is performed at a temperature of 700.degree. Moreover, as a method for etching the SiGe layer 11, wet etching may be performed using a mixed solution of acetic acid (CH ₃ COOH) and hydrofluoric acid (HF). Furthermore, CF ₄ gas may be introduced and chemical dry etching (CDE) using CF ₄ radicals may be performed. Thereby, an opening region 13 having a width A is formed. The opening region 13 formed in this way is formed so as to be substantially parallel to the silicon substrate 10 and the silicon layer 12.

Next, as shown in FIG. 10B, a silicon nitride film to be the oxidation delay film 14 is formed. The silicon nitride film to be the oxidation delay film 14 is formed so that the film thickness B on the surface of the silicon layer 12 is 3 to 10 nm. Examples of the oxidation delay film 14 include a silicon or metal nitride film, a carbonized film, and an oxide film. Specifically, silicon nitride (Si ₃ N ₄ ), silicon carbide (SiC), silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum pentoxide (Ta ₂ O) ₅ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ) and the like. Examples of the method for forming the oxidation delay film 14 include plasma CVD, thermal CVD, sputtering, and vacuum deposition. In this embodiment, a silicon nitride film to be the oxidation delay film 14 is formed at a film formation temperature of 600 ° C. by plasma CVD using a mixed gas of Si ₂ H ₆ , N _2, and NH ₃ . The film formation temperature at this time is 600 ° C., and the film formation is performed so that the film thickness B on the surface of the silicon layer 12 is about 10 nm. In a film formation method such as plasma CVD, particles that contribute to film formation are wrapped around, but the step coverage is not good, so that the film thickness B on the surface of the silicon layer 12 is about 10 nm. In this case, the film thickness C in the vicinity of the entrance of the opening region 13 is about 2 nm. In the opening region 13, the oxidation delay film 14 is formed thinner as it goes in the depth direction. This also applies to the film forming methods such as thermal CVD, sputtering, and vacuum deposition described above. Further, the oxidation delay film 14 is formed so as not to block the entrance of the opening region 13, and is formed near the entrance of the opening region 13 with respect to the width A of the opening region 13. 14 is formed so that the film thickness C is less than A / 2. Further, before the above-described formation of the anti-oxidation film, for example, an oxidation treatment of forming 3 nm of silicon oxide (SiO ₂ ) on the surface of the silicon layer 12 may be performed for the purpose of reducing film formation stress.

  Next, as shown in FIG. 10C, a silicon oxide film 15 is formed in the opening region 13 by thermal oxidation of silicon. Since silicon oxidizes and becomes silicon oxide, the volume expands, so that the inside of the opening region 13 can be filled with the silicon oxide film 15. The oxidation delay film 14 is formed thicker in the vicinity of the entrance of the opening region 13 than in the back of the opening region 13, and the rate of thermal oxidation of silicon is higher in the opening region 13 than in the vicinity of the entrance of the opening region 13. The back is faster. Therefore, since the silicon oxide film 15 is oxidized so as to embed the opening region 13 from the back of the opening region 13 toward the entrance, the inside of the opening region 13 can be substantially completely embedded by the silicon oxide film 15. it can. The formed silicon oxide film 15 also contributes to prevention of oxygen diffusion, so that the oxidation does not continue to spread inside the silicon substrate 10. In the present embodiment, the film thickness E of the silicon oxide film 15 becomes 50 nm by thermal oxidation treatment at 950 ° C. in an oxygen atmosphere containing nitrogen. Note that the silicon oxide film 15 partially includes a nitrogen component contained in the silicon nitride film that is the oxidation delay film 14.

Next, as shown in FIG. 11A, the silicon nitride film which is the oxidation delay film 14 is removed. Specifically, the silicon nitride film which is the oxidation delay film 14 is removed by wet etching using a phosphoric acid aqueous solution (H ₃ PO ₄ , 90%).

  Next, as shown in FIG. 11B, the silicon oxide film 31 is formed sufficiently thick. As a result, the silicon oxide film 31 can be embedded in the STI region 21 where the silicon oxide has been removed. The silicon oxide film 31 is formed by HDP (High Density Plasma) -CVD.

  Next, as shown in FIG. 11C, the silicon oxide film 31 is etched back to expose the surface of the silicon film 23 to be the gate electrode and the surface of the silicon layer 12. As a result, the STI region 21 is formed again by silicon oxide including the silicon oxide film 31.

Next, as shown in FIG. 12A, impurity regions 32 are formed by ion implantation of impurity elements into the silicon layer 12. Specifically, when a P-type region is formed as the impurity region 32, B (boron) is ion-implanted. The acceleration energy at the time of ion implantation of B is 0.5 keV or less, and the dose is 1 × 10 ¹⁴ cm ⁻² to 2 × 10 ¹⁵ cm ⁻² . When an N-type region is formed as the impurity region 32, P (phosphorus) is ion-implanted. The acceleration energy at the time of ion implantation of P is 5 keV to 20 keV, and the dose is 2 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² . When an N-type region is formed as the impurity region 32, ion implantation may be performed using As (arsenic) or Sb (antimony) as an impurity element. For example, the acceleration energy at the time of As ion implantation is 1 keV to 5 keV, and the dose is 1 × 10 ¹⁴ cm ⁻² to 2 × 10 ¹⁵ cm ⁻² .

  Next, as shown in FIG. 12B, a silicon nitride film 33 is formed to a thickness of about 20 nm by thermal CVD.

Next, as shown in FIG. 12C, CF ₄ , CH ₃ F, Ar, and O ₂ are introduced as etching gases and RIE or the like is performed to remove the silicon nitride film 33 on the silicon substrate 10. As a result, sidewalls 33a made of silicon nitride are formed again on the side surfaces of the silicon film 23 to be the gate electrode.

Next, as shown in FIG. 13A, an impurity region 34 is formed by ion implantation of an impurity element in a region deeper than the impurity region 32 in the silicon layer 12. Specifically, when a P-type region is formed as the impurity region 34, B is ion-implanted. The acceleration energy at the time of ion implantation of B is 0.5 keV or less, and the dose is 1 × 10 ¹⁴ cm ⁻² to 2 × 10 ¹⁵ cm ⁻² . When an N-type region is formed as the impurity region 34, P is ion-implanted. The acceleration energy at the time of ion implantation of P is 5 keV to 20 keV, and the dose is 2 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² . When an N-type region is formed as the impurity region 34, ion implantation may be performed using As or Sb as an impurity element. For example, the acceleration energy at the time of As ion implantation is 1 keV to 5 keV, and the dose is 1 × 10 ¹⁴ cm ⁻² to 2 × 10 ¹⁵ cm ⁻² .

  Next, as shown in FIG. 13B, activation annealing is performed to activate the impurity element implanted into the impurity regions 32 and 34, thereby forming an impurity diffusion region 35.

  Next, as shown in FIG. 13C, silicide films 36, 37 and 38 are formed. Specifically, after a metal film such as Ni, Co, Ti, or W is formed by sputtering, heat treatment is performed, whereby a silicide film is formed by silicide of metal and silicon contained in the metal film formed on silicon. 36, 37 and 38 are formed. More specifically, silicide layers 36 and 37 are formed by siliciding silicon exposed in the silicon layer 12 and metal in a metal film formed on the silicon layer 12. Further, the silicide layer 38 is formed by siliciding silicon exposed on the upper surface of the silicon film 23 to be the gate electrode and metal in the metal film formed on the silicon film 23 to be the gate electrode. Thereafter, the metal film other than the region where the silicide layers 36, 37 and 38 are formed is removed by wet etching.

  Next, as shown in FIG. 14A, a silicon oxide film 39 is formed on the silicide layers 36, 37 and 38 and the STI region 21. The silicon oxide film 39 is formed with a sufficiently thick film by HDP-CVD.

  Next, as shown in FIG. 14B, a resist pattern 40 is formed on the surface of the silicon oxide film 39. Specifically, a resist pattern 40 is formed by applying a photoresist to the surface of the silicon oxide film 39 and performing exposure and development with an exposure apparatus.

  Next, as shown in FIG. 14C, openings 41, 42, and 43 are formed by removing the silicon oxide film 39 in the region where the resist pattern 40 is not formed by RIE or the like. The openings 41 and 42 are formed by removing the silicon oxide film 39 until the surfaces of the silicide layers 36 and 37 are exposed. The openings 43 are formed by removing the silicon oxide film 39 until the surface of the silicide layer 38 is exposed. To form.

  Next, as shown in FIG. 15, W plugs 44, 45, 46 made of metal are embedded in each of the openings 41, 42, and 43. Specifically, after a Ti film or a TiN film is formed by MOCVD (Metal Organic Chemical Vapor Deposition), tungsten (W) is embedded to fill W openings 44, 42, and 43 in each of the openings 41, 42, and 43. Form. One of the silicide layer 36 and the W plug 44 and the silicide layer 37 and the W plug 45 serves as a drain electrode, and the other serves as a source electrode. The W plug 46 is electrically connected to the silicon film 23 that is a gate electrode.

  As described above, a semiconductor device can be manufactured by the method for manufacturing a semiconductor device in the present embodiment. In this embodiment mode, a semiconductor substrate having a highly reliable Local SOI structure can be formed at low cost. In addition, in the semiconductor device having this Local SOI structure, a semiconductor device with low junction capacitance and low leakage current can be obtained at low cost.

[Second Embodiment]
Next, a second embodiment will be described. The present embodiment is a method for manufacturing a semiconductor device different from the first embodiment. Note that the manufacturing method of the semiconductor device in the present embodiment is the same up to the step shown in FIG. 10A of the manufacturing method of the semiconductor device in the first embodiment, so that FIG. The process after the process shown is demonstrated.

  First, what is shown in FIG. 16A is the same as that shown in FIG. 10A, and an opening region 13 having a width A is formed by selectively removing the SiGe layer 11. It is a thing.

  Next, as shown in FIG. 16B, a silicon nitride film to be the oxidation delay film 14 is formed. The silicon nitride film to be the oxidation delay film 14 is formed so that the film thickness B on the surface of the silicon layer 12 is 3 to 10 nm. In the present embodiment, film formation is performed so that the film thickness B on the surface of the silicon layer 12 is about 10 nm. In a film formation method such as plasma CVD, the step coverage is not good. Therefore, when the film thickness B on the surface of the silicon layer 12 is about 10 nm, the film thickness C near the entrance of the opening region 13 is Further, the depth of the opening region 13 is made thinner.

  Next, as shown in FIG. 16C, a silicon oxide film 15 is formed in the opening region 13 by thermal oxidation of silicon. Since silicon oxidizes and becomes silicon oxide, the volume expands, so that the inside of the opening region 13 can be filled with the silicon oxide film 15. In the present embodiment, the film thickness E of the silicon oxide film 15 becomes 50 nm by thermal oxidation treatment at 950 ° C. in an oxygen atmosphere containing nitrogen. Note that the silicon oxide film 15 partially includes a nitrogen component contained in the silicon nitride film that is the oxidation delay film 14.

Next, as shown in FIG. 17A, the silicon nitride film which is the oxidation delay film 14 is removed. Specifically, the silicon nitride film which is the oxidation delay film 14 is removed by wet etching using a phosphoric acid aqueous solution (H ₃ PO ₄ , 90%).

  Next, as shown in FIG. 17B, impurity regions 32 are formed by ion implantation of impurity elements into the silicon layer 12.

  Next, as shown in FIG. 17C, a silicon nitride film 33 is formed to a thickness of about 20 nm by thermal CVD.

Next, as shown in FIG. 18A, CF ₄ , CH ₃ F, Ar, and O ₂ are introduced as etching gases and RIE or the like is performed to remove the silicon nitride film 33 on the silicon substrate 10. Thereby, the sidewall 33a made of silicon nitride is formed again on the side surface of the silicon film 23 to be the gate electrode. At this time, a silicon nitride layer 33b is formed on the surface of the STI region 21 where the silicon oxide has been removed.

  Next, as shown in FIG. 18B, an impurity region 34 is formed by ion implantation of an impurity element in a region deeper than the impurity region 32 in the silicon layer 12.

  Next, as shown in FIG. 18C, activation annealing is performed to activate the impurity element implanted into the impurity regions 32 and 34, thereby forming an impurity diffusion region 35. Next, as shown in FIG.

  Next, as shown in FIG. 19A, silicide films 36, 37 and 38 are formed. Specifically, after a metal film such as Ni, Co, Ti, or W is formed by sputtering, heat treatment is performed, whereby a silicide film is formed by silicide of metal and silicon contained in the metal film formed on silicon. 36, 37 and 38 are formed. Thereafter, the metal film other than the region where the silicide layers 36, 37 and 38 are formed is removed by wet etching.

  Next, as shown in FIG. 19B, a silicon oxide film 39 is formed on the silicide layers 36, 37 and 38 and the STI region 21. The silicon oxide film 39 is formed with a sufficiently thick film by HDP-CVD.

  Next, as shown in FIG. 19C, a resist pattern 40 is formed on the surface of the silicon oxide film 39. Specifically, a resist pattern 40 is formed by applying a photoresist to the surface of the silicon oxide film 39 and performing exposure and development with an exposure apparatus.

  Next, as shown in FIG. 20A, openings 41, 42, and 43 are formed by removing the silicon oxide film 39 in the region where the resist pattern 40 is not formed by RIE or the like. The openings 41 and 42 are formed by removing the silicon oxide film 39 until the surfaces of the silicide layers 36 and 37 are exposed. The openings 43 are formed by removing the silicon oxide film 39 until the surface of the silicide layer 38 is exposed. To form.

  Next, as shown in FIG. 20B, W plugs 44, 45, and 46 made of metal are embedded in each of the openings 41, 42, and 43. Specifically, after a Ti film or a TiN film is formed by MOCVD, W plugs 44, 45, and 46 are formed in the openings 41, 42, and 43, respectively, by embedding W. One of the silicide layer 36 and the W plug 44 and the silicide layer 37 and the W plug 45 serves as a drain electrode, and the other serves as a source electrode. The W plug 46 is electrically connected to the silicon film 23 that is a gate electrode.

  As described above, a semiconductor device can be manufactured by the method for manufacturing a semiconductor device in the present embodiment. In the present embodiment, the number of manufacturing steps can be reduced, and a semiconductor device can be manufactured at a lower cost. The contents other than the above are the same as in the first embodiment.

[Third Embodiment]
Next, a third embodiment will be described. The present embodiment is a method for manufacturing a semiconductor device different from the first embodiment. Note that the manufacturing method of the semiconductor device in the present embodiment is the same up to the step shown in FIG. 10A of the manufacturing method of the semiconductor device in the first embodiment, so that FIG. The process after the process shown is demonstrated.

  First, what is shown in FIG. 21A is the same as that shown in FIG. 10A, and by selectively removing the SiGe layer 11, an opening region 13 having a width A is formed. It is a thing.

  Next, as shown in FIG. 21B, a silicon nitride film to be the oxidation delay film 14 is formed. The silicon nitride film to be the oxidation delay film 14 is formed so that the film thickness B on the surface of the silicon layer 12 is 3 to 10 nm. In the present embodiment, film formation is performed so that the film thickness B on the surface of the silicon layer 12 is about 10 nm. In a film formation method such as plasma CVD, the step coverage is not good. Therefore, when the film thickness B on the surface of the silicon layer 12 is about 10 nm, the film thickness C near the entrance of the opening region 13 is Further, the depth of the opening region 13 is made thinner.

  Next, as shown in FIG. 21C, a silicon oxide film 15 is formed in the opening region 13 by thermal oxidation of silicon. Since silicon oxidizes and becomes silicon oxide, the volume expands, so that the inside of the opening region 13 can be filled with the silicon oxide film 15. In the present embodiment, the film thickness E of the silicon oxide film 15 becomes 50 nm by thermal oxidation treatment at 950 ° C. in an oxygen atmosphere containing nitrogen. Note that the silicon oxide film 15 partially includes a nitrogen component contained in the silicon nitride film that is the oxidation delay film 14.

  Next, as shown in FIG. 22A, a silicon oxide film 31 is formed to be sufficiently thick. As a result, the silicon oxide film 31 can be embedded in the STI region 21 where the silicon oxide has been removed. The silicon oxide film 31 is formed by HDP-CVD.

  Next, as shown in FIG. 22B, the silicon oxide film 31 is etched back to expose the silicon nitride film that becomes the oxidation delay film 14 formed on the surface of the silicon layer 12. At this time, the silicon oxide film 31 is buried in the region where the silicon oxide in the STI region 21 is removed.

Next, as shown in FIG. 22C, the silicon nitride film which is the oxidation delay film 14 is removed. Specifically, it is formed on the side surfaces of the silicon nitride film which is the oxidation delay film 14 on the surface of the silicon layer 12 and the silicon film 23 which becomes the gate electrode by wet etching using an aqueous phosphoric acid solution (H ₃ PO ₄ , 90%). The side wall 26a made of silicon nitride is removed. Thereby, the STI region 21 is formed of an insulator including the silicon oxide film 31 and silicon nitride.

  Next, as shown in FIG. 23A, impurity regions 32 are formed by performing ion implantation of impurity elements into the silicon layer 12.

  Next, as shown in FIG. 23B, a silicon nitride film 33 is formed to a thickness of about 20 nm by thermal CVD.

Next, as shown in FIG. 23C, CF ₄ , CH ₃ F, Ar, and O ₂ are introduced as etching gases and RIE or the like is performed to remove the silicon nitride film 33 on the silicon substrate 10. Thereby, the sidewall 33a made of silicon nitride is formed again on the side surface of the silicon film 23 to be the gate electrode.

  Next, as shown in FIG. 24A, impurity regions 34 are formed by ion implantation of an impurity element in a region deeper than the impurity region 32 in the silicon layer 12.

  Next, as shown in FIG. 24B, activation annealing is performed to activate the impurity element implanted into the impurity regions 32 and 34, thereby forming an impurity diffusion region 35. Next, as shown in FIG.

  Next, as shown in FIG. 24C, silicide films 36, 37 and 38 are formed. Specifically, after a metal film such as Ni, Co, Ti, or W is formed by sputtering, heat treatment is performed, whereby a silicide film is formed by silicide of metal and silicon contained in the metal film formed on silicon. 36, 37 and 38 are formed. Thereafter, the metal film other than the region where the silicide layers 36, 37 and 38 are formed is removed by wet etching.

  Next, as shown in FIG. 25A, a silicon oxide film 39 is formed on the silicide layers 36, 37 and 38 and the STI region 21. The silicon oxide film 39 is formed with a sufficiently thick film by HDP-CVD.

  Next, as shown in FIG. 25B, a resist pattern 40 is formed on the surface of the silicon oxide film 39. Specifically, a resist pattern 40 is formed by applying a photoresist to the surface of the silicon oxide film 39 and performing exposure and development with an exposure apparatus.

  Next, as shown in FIG. 25C, openings 41, 42, and 43 are formed by removing the silicon oxide film 39 in the region where the resist pattern 40 is not formed by RIE or the like. The openings 41 and 42 are formed by removing the silicon oxide film 39 until the surfaces of the silicide layers 36 and 37 are exposed. The openings 43 are formed by removing the silicon oxide film 39 until the surface of the silicide layer 38 is exposed. To form.

  Next, as shown in FIG. 26, W plugs 44, 45, 46 made of metal are embedded in the openings 41, 42, and 43, respectively. Specifically, after a Ti film or a TiN film is formed by MOCVD, W plugs 44, 45, and 46 are formed in the openings 41, 42, and 43, respectively, by embedding W. One of the silicide layer 36 and the W plug 44 and the silicide layer 37 and the W plug 45 serves as a drain electrode, and the other serves as a source electrode. The W plug 46 is electrically connected to the silicon film 23 that is a gate electrode.

  As described above, a semiconductor device can be manufactured by the method for manufacturing a semiconductor device in the present embodiment.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
A semiconductor layer forming step of sequentially forming a layer made of the second semiconductor and a layer made of the first semiconductor on the substrate made of the first semiconductor by crystal growth;
An opening region forming step of forming an opening region by removing the layer made of the second semiconductor by etching;
In the opening region, an oxidation retardation film is formed by depositing an oxidation delay film formed of a material including a nitride film, a carbide film, or an oxide film so that the film thickness at the entrance of the opening region becomes a predetermined thickness. A membrane process;
A thermal oxidation step of forming a thermal oxide film in the opening region by thermally oxidizing a part of the first semiconductor of the substrate made of the first semiconductor and the layer made of the first semiconductor;
A method for manufacturing a semiconductor substrate, comprising:
(Appendix 2)
The method of manufacturing a semiconductor substrate according to appendix 1, wherein the first semiconductor is Si, and the second semiconductor is SiGe.
(Appendix 3)
The method of manufacturing a semiconductor substrate according to appendix 1 or 2, wherein a film thickness of the oxidation delay film formed at the entrance of the opening region is less than ½ of the opening width of the opening region. .
(Appendix 4)
4. The method of manufacturing a semiconductor substrate according to any one of appendices 1 to 3, wherein the oxidation delay film is formed by any one of plasma CVD, thermal CVD, sputtering, and vacuum deposition.
(Appendix 5)
The oxidation retardation film is formed of one or more materials selected from silicon nitride, silicon carbide, silicon oxide, aluminum oxide, hafnium oxide, tantalum pentoxide, lanthanum oxide, and yttrium oxide. A method for manufacturing a semiconductor substrate according to any one of appendices 1 to 4.
(Appendix 6)
Forming a gate electrode on a substrate made of a first semiconductor; and
A first semiconductor removing step of removing a predetermined depth of the first semiconductor in a region where the source and drain are formed in the first semiconductor substrate;
A semiconductor layer forming step of sequentially forming a layer made of the second semiconductor and a layer made of the first semiconductor by crystal growth in the removed region from which the first semiconductor has been removed;
An opening region forming step of forming an opening region by removing the layer made of the second semiconductor by etching;
In the opening region, an oxidation retardation film is formed by depositing an oxidation delay film formed of a material including a nitride film, a carbide film, or an oxide film so that the film thickness at the entrance of the opening region becomes a predetermined thickness. A membrane process;
A thermal oxidation step of forming a thermal oxide film by thermally oxidizing a part of the first semiconductor of the substrate made of the first semiconductor and the layer made of the first semiconductor;
Forming an impurity diffusion region in the first semiconductor layer, and forming a source and a drain on the impurity diffusion region;
A method for manufacturing a semiconductor device, comprising:
(Appendix 7)
The method of manufacturing a semiconductor device according to appendix 6, wherein the first semiconductor is Si and the second semiconductor is SiGe.
(Appendix 8)
8. The method of manufacturing a semiconductor substrate according to appendix 6 or 7, wherein the film thickness of the oxidation delay film at the entrance of the opening region is less than ½ of the opening width of the opening region.
(Appendix 9)
9. The method of manufacturing a semiconductor substrate according to any one of appendices 6 to 8, wherein the oxidation retardation film is formed by any one of plasma CVD, thermal CVD, sputtering, and vacuum deposition.
(Appendix 10)
The oxidation retardation film is formed of one or more materials selected from silicon nitride, silicon carbide, silicon oxide, aluminum oxide, hafnium oxide, tantalum pentoxide, lanthanum oxide, and yttrium oxide. A method for manufacturing a semiconductor substrate according to any one of appendices 6 to 9.
(Appendix 11)
11. The method of manufacturing a semiconductor device according to appendix 9 or 10, wherein an oxidation treatment is performed on the substrate made of the first semiconductor before the formation of the oxidation delay film.
(Appendix 12)
12. The method of manufacturing a semiconductor substrate according to any one of appendices 6 to 11, wherein the removal region is a region excluding a region where the gate electrode is formed.
(Appendix 13)
13. The semiconductor according to any one of appendices 6 to 12, wherein in the thermal oxidation step, the region where the thermal oxide film of the first semiconductor is formed is a region where the source and the drain are formed. A method for manufacturing a substrate.
(Appendix 14)
An STI region made of an insulator is formed on the substrate made of the first semiconductor, and the gate electrode is formed in a region excluding the STI region,
After the semiconductor layer forming step, the step of removing the insulator in the STI region up to the region where the layer made of the second semiconductor is formed,
14. The method of manufacturing a semiconductor substrate according to any one of appendices 6 to 13, wherein the opening region forming step is performed after the step of removing the insulator in the STI region.
(Appendix 15)
After the thermal oxidation step, removing the oxidation retardation film formed on the surface of the layer made of the first semiconductor,
15. The method of manufacturing a semiconductor substrate according to any one of appendices 6 to 14, wherein the electrode forming step is performed after removing the oxidation retardation film formed on a surface of the layer made of the first semiconductor. .
(Appendix 16)
16. The method of manufacturing a semiconductor substrate according to any one of appendices 6 to 15, further comprising forming a silicide layer connected to the gate electrode and a silicide layer connected to the source and the drain.
(Appendix 17)
After the silicide layer is formed, an insulating film is formed on the silicide layer, an opening region is formed in the insulating film until each silicide layer is exposed, and the opening region is filled with metal. A method for manufacturing a semiconductor substrate according to any one of appendices 6 to 16.

DESCRIPTION OF SYMBOLS 10 Silicon substrate 11 SiGe layer 12 Silicon layer 13 Opening region 14 Oxidation delay film 15 Silicon oxide film 21 STI region 22 SiON film 23 Silicon film 24 Silicon nitride film 25 Resist pattern 26 Silicon nitride film 26a Side wall 27 Removal region 31 Silicon oxide film 32 impurity region 33 silicon nitride film 33a sidewall 34 impurity region 35 impurity diffusion region 36 silicide layer 37 silicide layer 38 silicide layer 39 silicon oxide film 40 resist pattern 41 opening 42 opening 43 opening 44 W plug 45 W plug 46 W plug

Claims (9)

A semiconductor layer forming step of sequentially forming a layer made of the second semiconductor and a layer made of the first semiconductor on the substrate made of the first semiconductor by crystal growth;
An opening region forming step of forming an opening region by removing the layer made of the second semiconductor from the side surface by etching;
In the opening region, an oxidation retardation film is formed by depositing an oxidation delay film formed of a material including a nitride film, a carbide film, or an oxide film so that the film thickness at the entrance of the opening region becomes a predetermined thickness. A membrane process;
A thermal oxidation step of forming a thermal oxide film in the opening region by thermally oxidizing a part of the first semiconductor of the substrate made of the first semiconductor and the layer made of the first semiconductor;
A method for manufacturing a semiconductor substrate, comprising: The method for manufacturing a semiconductor substrate according to claim 1, wherein the opening region is formed to be substantially parallel to the substrate made of the first semiconductor. Wherein the first semiconductor is Si, a method of manufacturing a semiconductor substrate according to claim 1 or 2, wherein the second semiconductor is SiGe. Thickness of the oxide delay film formed to the inlet of the opening region, a semiconductor according to any one of claims 1 to 3, characterized in that said less than half the width of the opening of the opening region A method for manufacturing a substrate. Forming a gate electrode on a substrate made of a first semiconductor; and
A first semiconductor removing step of removing a predetermined depth of the first semiconductor in a region where the source and drain are formed in the first semiconductor substrate;
A semiconductor layer forming step of sequentially forming a layer made of the second semiconductor and a layer made of the first semiconductor by crystal growth in the removed region from which the first semiconductor has been removed;
An opening region forming step of forming an opening region by removing the layer made of the second semiconductor by etching;
In the opening region, an oxidation retardation film is formed by depositing an oxidation delay film formed of a material including a nitride film, a carbide film, or an oxide film so that the film thickness at the entrance of the opening region becomes a predetermined thickness. A membrane process;
A thermal oxidation step of forming a thermal oxide film in the opening region by thermally oxidizing a part of the first semiconductor of the substrate made of the first semiconductor and the layer made of the first semiconductor;
Forming an impurity diffusion region in the first semiconductor layer, and forming a source and a drain on the impurity diffusion region;
I have a,
An STI region made of an insulator is formed on the substrate made of the first semiconductor, and the gate electrode is formed in a region excluding the STI region,
After the semiconductor layer forming step, the step of removing the insulator in the STI region up to the region where the layer made of the second semiconductor is formed,
A method of manufacturing a semiconductor device , wherein the opening region forming step is performed after the step of removing the insulator in the STI region . Forming a gate electrode on a substrate made of a first semiconductor; and
A first semiconductor removing step of removing a predetermined depth of the first semiconductor in a region where the source and drain are formed in the first semiconductor substrate;
A semiconductor layer forming step of sequentially forming a layer made of the second semiconductor and a layer made of the first semiconductor by crystal growth in the removed region from which the first semiconductor has been removed;
An opening region forming step of removing the layer made of the second semiconductor by etching from a side surface to form an opening region substantially parallel to the substrate made of the first semiconductor ;
In the opening region, an oxidation retardation film is formed by depositing an oxidation delay film formed of a material including a nitride film, a carbide film, or an oxide film so that the film thickness at the entrance of the opening region becomes a predetermined thickness. A membrane process;
A thermal oxidation step of forming a thermal oxide film in the opening region by thermally oxidizing a part of the first semiconductor of the substrate made of the first semiconductor and the layer made of the first semiconductor;
Forming an impurity diffusion region in the first semiconductor layer, and forming a source and a drain on the impurity diffusion region;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 5, wherein the first semiconductor is Si, and the second semiconductor is SiGe. 8. The method of manufacturing a semiconductor device according to claim 5 , wherein a film thickness of the oxidation delay film at an entrance of the opening region is less than ½ of an opening width of the opening region. 9. . In the thermal oxidation process, a region where the first semiconductor thermal oxide film is formed, according to claim 5, wherein 8 of said an area where the source and the drain are formed A method for manufacturing a semiconductor device .

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