USRE37158E1 - High performance sub-micron P-channel transistor with germanium implant - Google Patents

High performance sub-micron P-channel transistor with germanium implant Download PDF

Info

Publication number
USRE37158E1
USRE37158E1 US08/568,891 US56889195A USRE37158E US RE37158 E1 USRE37158 E1 US RE37158E1 US 56889195 A US56889195 A US 56889195A US RE37158 E USRE37158 E US RE37158E
Authority
US
United States
Prior art keywords
oxide
method
implanting
forming
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/568,891
Inventor
Roger Ruojia Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Round Rock Research LLC
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US07/566,433 priority Critical patent/US5266510A/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US08/568,891 priority patent/USRE37158E1/en
Application granted granted Critical
Publication of USRE37158E1 publication Critical patent/USRE37158E1/en
Assigned to ROUND ROCK RESEARCH, LLC reassignment ROUND ROCK RESEARCH, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Abstract

Implantation of germanium (45) into a PMOS buried channel to permits the enhancement implant profile (to 45) to be made more shallow. The shallow profile will reduce or eventually solve P-channel buried channel-induced short channel effects and enable further decrease in device length to deep submicron range.
Benefits include better short channel characteristics, i.e., higher punch through voltage BVDSS, less VT sensitivity to the drain voltage (defined as curl) and better subthreshold leakage characteristics.

Description

FIELD OF THE INVENTION

This invention is related to semiconductor devices. Specifically it is related to high-performance sub-micron channel length P-channel MOS (metal-oxide-semiconductor) transistor (PMOS for short) for the Very Large Scale Integrated (VLSI) or the Ultra Large Scale Integrated (ULSI) circuits. It employs the use of Germanium implant into the channel regions of transistors to both pre-amorphize the channel surface to alleviate the channelling of subsequent enhancement implant required by threshold voltage Vt adjustment and to retard the diffusion of the boron dopants (from enhancement implant) in the region to form a very shallow enhancement implant profile.

BACKGROUND OF THE INVENTION

The invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a “semiconductor”. One of the materials used is silicon, which is used as either single crystal silicon or as polycrystalline silicon material, referred to as polysilicon or “poly” in this disclosure.

Shallow channel junction will reduce significantly the undesirable short channel effects of transistors. This is significant in the fabrication of sub-micron P-channel (P-CH) transistors in which n+ doped poly gate is used and buried channel is formed. It is desired to further reduce or even solve P-channel buried channel-induced short channel effects and enable further decrease in device length to the sub-micron range.

The prior art relating to Germanium in VLSI devices has been in the area of (1) field isolation improvement and (2) transistor source/drain regions to achieve shallow source and drain junctions. The former deals with device isolation and an improvement in electrical encroachment; yet it does not improve transistor performance; the later deals with device performance by means of achieving shallower source drain junction depths so that the reduction in charge-sharing effect would improve transistor short channel characteristics. It however does not solve or reduce P-channel transistor short channel effects caused by the very nature of buried channel behaviour.

SUMMARY OF THE INVENTION

The present invention deals directly with PMOS buried channel characteristics by making the buried channel enhancement implant profile more shallow. The shallow implant profile results in the P-CH device will have less or no buried channel characteristics. This avoids undesirable short channel effects, and therefore permits further reduction in the transistor channel length.

The shallow profile causes surface channel characteristics to be dominant. Surface channel devices will have better short channel characteristics, i.e., higher punch through voltage BVDSS, less VT sensitivity to the drain voltage (defined as curl) and better subthreshold leakage characteristics.

Implantation of germanium into the channel to permit the enhancement implant profile to be made shallower will reduce or event solve P-channel buried channel-induced short channel effects and enable further decrease in device length to deep sub-micron range.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawing Figures each show cross-sections of a portion of a semiconductor circuit device which utilizes the present invention.

FIG. 1 shows growth of an initial gate oxide, patterning of active areas and channel stop implant;

FIG. 2 shows a LOCOS step;

FIG. 3 shows nitride strip and initial oxide strip;

FIG. 4 shows growth of sacrificial oxide and germanium implant;

FIG. 5 shows VT enhancement implant and sacrificial oxide strip;

FIG. 6 shows final gate oxide growth, gate polysilicon deposition and phosphorus deposition;

FIG. 7 shows transistor gate definition and lightly doped source/drain BF2 implant;

FIG. 8 shows spacer formation and heavy source/drain BF2 implant; and

FIG. 9 shows source/drain activation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 shows a cross-section of a semiconductor circuit during its fabrication. A silicon wafer 13 is prepared by forming a thin film of oxide 15 and then depositing nitride 17 over the thin oxide 15. The nitride is masked and etched in order to define active area (31, FIG. 3). The unmasked portions of the wafer 13 are then implanted with boron in order to increase parasitic field transistor threshold voltage VTF.

After the field implant, a thick layer of silicon oxide 21 is grown onto the wafer 13 to form field ox, as shown in FIG. 2. The growth of silicon oxide occurs in areas which are not covered by the nitride mask 17, but tends to encroach on the active area, marked AA. The encroachment is present around the edges of the nitride 17, as indicated by dashed lines 23, where the oxide 21 begins to “buck up” or lift the nitride 17.

The nitride 17 is then stripped and the wafer 13 is oxide etched in order to remove a top portion 41 of the field ox 21, as shown in FIG. 3. This reduces the encroachment of the silicon oxide 21 into the active area 31 by reducing the thickness of the field oxide 21 in the regions of encroachment. This stripping of the top layer, referred to as dilute buffered hydrofluoric acid wet oxide etch, is timed to remove a pre-determined fraction of the field oxide.

The reduced thickness of the field oxide 21 adjacent to the active area 31 establishes an active parasitic MOS transistor device in the completed wafer. This parasitic MOS transistor device could result in shunting between adjacent active areas 31.

At this point, a germanium implant is applied to the wafer by ion implantation, as shown in FIG. 4. Any of various sources of germanium may be used, such as GeF4 gas. A preferred method for implanting the germanium is by ion implantation.

The germanium does not pass through the thick fieldox 21, but does penetrate the wafer 13 where the oxide 41 has been stripped (shown in FIG. 3). The germanium is allowed to penetrate to a level indicated by the dashed line by controlling implant energy, as well as other factors including temperature. This forms a germanium layer 45 to the depth of the dashed line.

The germanium layer 45 is used to reduce P-channel transistor buried channel effects by reducing counter-doping junction depth. A reduction in counter doping junction depths will, in turn, reduce short channel effects in the completed transistor. This also pre-amorphizes the channel surface in order to alleviate channeling of subsequent enhancement implant with boron.

FIG. 4 also shows the addition of a sacrificial layer 47 of oxide which is grown on to the wafer 13 after the germanium implant. Subsequent to the growth of the sacrificial layer, a boron implant is applied. The boron is able to penetrate the thin sacrificial layer 47 in order to permit control of VT of the transistors. The boron dopants diffuse into the wafer 13, but this diffusion remains very shallow as a result of the earlier implant of the germanium. This results in the germanium layer 45 being doped with the boron, and the infusion of the boron being largely confined to the germanium layer 45. After the boron implant, the sacrificial oxide 47 is stripped and a final gate oxide 49 is grown to improve gate oxide quality.

BF2 may be used instead of boron in the boron implant steps in order to provide the boron implant.

A layer of polysilicon 55 is applied to the substrate 13 and, as a result of the final gate oxide 53, remains isolated from the boron doped germanium implant layer 45. This layer of polysilicon 55 forms the gates to transistors formed with the boron doped germanium layer 45, so that the boron doped germanium layer 45 forms source and drain regions. At that point, phosphorus deposition is applied to establish the polysilicon layer 55 as N+ type polysilicon.

The wafer is masked in order to define the transistor gate. As shown in FIG. 7, the definition of the transistor gates is accomplished by etching the N+ polysilicon in order to form gate portions 61 of the transistors. After the transistor gate definition, a lightly doped source and drain implant is applied by using BF2 as an implant material. This results in a lightly doped source drain profile 63 as shown in FIG. 8.

Also as shown in FIG. 8, a spacer oxide 65 is grown from the transistor gate 61, followed by a heavy source/drain BF2 implant. The heavy source/drain BF2 implant results in the profile 73 of P+ areas shown in FIG. 9. The germanium implant earlier also reduces the diffusion of both P+ and P− and makes it possible to have shallower P+ and P− junctions.

The basic fabrication process flow of the inventive P-channel MOS transistor is as follows:

(1) grow initial gate oxide

(2) pattern active area, channel stop implant, LOCOS, nitride strip

(3) initial oxide strip

(4) sacrificial oxide grow

(5) germanium implant

(6) VT enhancement implant

(7) sacrificial oxide strip

(8) final gate oxide grow, gate polysilicon deposition and phosphorus deposition

(9) transistor gate definition

(10) lightly doped source/drain BF2 implant

(11) spacer formation and heavy source/drain BF2 implant

(12) source/drain activation

In the preferred embodiment, one would implant N-type bottom plate capacitors at a does sufficient to significantly compensate the threshold voltage implant sufficiently to insure a desired bottom plate junction formation. The capacitor would include a grounded field plate. It is also possible to include a Vcc/2 field plate.

While the invention is described in terms of DRAMs, this is merely the preferred embodiment for which the inventive techniques were developed. Pertinent examples are EPROMs, video random access memories (VRAMs), other multiport RAMs, and other semiconductor devices.

For example, heavy germanium impurity in the N-channel devices can increase impact ionization rate and therefore make it easier to program in EPROMs by avalanching hot electrons.

Clearly, other steps may be taken within the scope of the invention in order to accomplish either same or different circuit results. Accordingly, the invention should be read only as limited by the claims.

Claims (15)

We claim:
1. Method A method of forming semiconductor circuit devices which include, as a part of each device, a plurality of cells, said cells including active circuit elements, including p channel transistors, to control signals, the method comprising:
a) preparing a silicon wafer and establishing the wafer as a substrate, and forming an oxide layer on the substrate;
b) forming a nitride layer on the wafer to define field oxide and active areas;
c) forming a pattern of nitride from said nitride layer over selected portions of the active areas;
d) implanting the oxide layer adjacent the nitride pattern with an implant dopant which functions as a channel stop for isolating parasitic field effect transistors;
e) growing oxide on the substrate around the nitride pattern, using LOCOS techniques;
f) removing the nitride pattern;
g) removing a portion of the oxide such that a fraction of the oxide in active areas formerly under the nitride pattern is removed, said removed portion defining channels for p channel transistors;
h) implanting germanium into said channel areas of the substrate through the active areas from which a fraction of the oxide has been removed;
i) growing further oxide over the germanium-implanted silicon wafer;
j) implanting boron through said further oxide;
k) stripping said further oxide;
l) growing a gate oxide layer over the active areas;
m) depositing a first conductive layer over the gate oxide layer and etching the conductive layer to leave conductive material from the conductive layer in a gate pattern;
n) implanting lightly doped source/drain regions around the gate pattern;
o) forming oxide spacers adjacent to the conductive material in the gate pattern; and
p) implanting source and drain impurities to form P+ source and drain regions adjacent to the gate pattern, separated by P− regions immediately adjacent to the gate pattern.
2. Method A method of forming semiconductor devices as described in claim 1, further characterized by:
prior to said implanting of source and drain impurities to form the P+ source and drain regions,
growing a spacer oxide from the conductive material in the gate pattern.
3. Method A method of forming semiconductor memory devices as described in claim 1, further characterized by:
a) said fraction of oxide removed being greater than 50% of the thickness of the field oxide; and
b) said implanting the silicon wafer with boron at an implantation dose being performed subsequent to formation of the active areas and prior to said depositing of the first conductive layer.
4. Method A method of forming semiconductor memory devices as described in claim 3, further characterized by:
forming each of said semiconductor memory devices with a grounded field plate.
5. Method A method of forming semiconductor circuit memory devices which include, as a part of each device, a plurality of memory cells and active circuit elements to control signals, the cells and active circuit elements forming a repeating pattern on the device, the method comprising:
a) preparing a wafer and establishing the wafer as a substrate;
b) forming oxide on the wafer to define field oxide and active areas, the active areas including active areas of p channel transistors;
c) implanting germanium into transistor channel areas of the active areas of the p channel transistors;
d) implanting the wafer with a P-type impurity which effects a change in a threshold voltage of the p channel transistors;
e) forming gate electrodes; and
f) implanting to form an N-type bottom plate capacitor with a dose sufficient to compensate the threshold voltage implant sufficiently to insure a desired bottom plate junction formation.
6. Method A method of forming semiconductor memory devices as described in claim 5, further characterized by:
implanting source and drain impurities to form P+ source and drain regions adjacent to the gate electrodes, separated by P− regions immediately adjacent to the gate electrodes.
7. Method A method of forming semiconductor devices as described in claim 6, further characterized by:
prior to implanting the source and drain impurities to form the P+ source and drain regions, growing a spacer oxide adjacent to the gate electrodes.
8. Method A method of forming semiconductor devices as described in claim 5, further characterized by:
a) etching said defined regions of field oxide to be reduced in thickness to remove a fraction of field oxide present; and
b) implanting the wafer with boron as the threshold voltage implant wherein the boron is implanted at energy levels which are optimized for penetration through the field oxide remaining after said etching of said defined regions of field oxide to be reduced in thickness.
9. Method A method of forming semiconductor memory devices as described in claim 1 or 4, further characterized by:
isotropically etching the field oxide by application of a wet oxide etch to remove said fraction of the field oxide, by using dilute buffered hydrofluoric acid wet oxide etch as said oxide etch.
10. Method A method of forming semiconductor memory devices as described in claim 1 or 4, further characterized by:
said fraction of oxide removed being greater than 50% of the thickness of the field oxide.
11. Method A method of forming semiconductor memory devices as described in claim 1 or 5, further characterized by:
forming each of said semiconductor memory devices with a grounded field plate.
12. A method of forming semiconductor circuit devices which include a plurality of cells, said cells including active circuit elements including p channel transistors, comprising the steps of:
providing a silicon wafer having channels of said p channel transistors formed thereon;
implanting germanium into said channels of said p channel transistors;
implanting said silicon wafer with a P-type impurity to effect a change in a threshold voltage of said p channel transistors;
forming gate electrodes; and
implanting lightly doped source and drain regions adjacent to the gate electrodes.
13. The method of claim 12, further comprising the step of forming an oxide layer over said germanium-implanted wafer, and implanting boron through said oxide layer.
14. The method of claim 12, wherein said silicon wafer comprises active areas and field areas thereon, and wherein said channel areas are situated between said field areas, and wherein said method further comprises the steps of:
growing an oxide layer over said germanium-implanted wafer;
implanting boron through said oxide layer;
stripping said oxide layer;
growing a gate oxide layer over said wafer; and
depositing a first conductive layer over said gate oxide layer to form a gate.
15. A method of forming semiconductor circuit memory devices which include, as a part of each device, a plurality of memory cells and active circuit elements to control signals, the method comprising:
providing a wafer as a substrate;
forming oxide on the wafer to define field oxide and active areas, the active areas including active areas of p channel transistors;
implanting germanium into transistor channel areas of said active areas of said p channel transistors;
implanting the wafer with a P-type impurity to effect a change in a threshold voltage of said p channel transistors;
forming gates electrodes; and
implanting lightly doped source and drain regions adjacent to the gate electrodes.
US08/568,891 1990-08-09 1995-11-30 High performance sub-micron P-channel transistor with germanium implant Expired - Lifetime USRE37158E1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US07/566,433 US5266510A (en) 1990-08-09 1990-08-09 High performance sub-micron p-channel transistor with germanium implant
US08/568,891 USRE37158E1 (en) 1990-08-09 1995-11-30 High performance sub-micron P-channel transistor with germanium implant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/568,891 USRE37158E1 (en) 1990-08-09 1995-11-30 High performance sub-micron P-channel transistor with germanium implant

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US07/566,433 Reissue US5266510A (en) 1990-08-09 1990-08-09 High performance sub-micron p-channel transistor with germanium implant

Publications (1)

Publication Number Publication Date
USRE37158E1 true USRE37158E1 (en) 2001-05-01

Family

ID=24262873

Family Applications (2)

Application Number Title Priority Date Filing Date
US07/566,433 Expired - Lifetime US5266510A (en) 1990-08-09 1990-08-09 High performance sub-micron p-channel transistor with germanium implant
US08/568,891 Expired - Lifetime USRE37158E1 (en) 1990-08-09 1995-11-30 High performance sub-micron P-channel transistor with germanium implant

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US07/566,433 Expired - Lifetime US5266510A (en) 1990-08-09 1990-08-09 High performance sub-micron p-channel transistor with germanium implant

Country Status (1)

Country Link
US (2) US5266510A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6352912B1 (en) * 2000-03-30 2002-03-05 International Business Machines Corporation Reduction of reverse short channel effects by deep implantation of neutral dopants
US6696341B1 (en) * 1998-01-21 2004-02-24 Renesas Technology Corp. Method of manufacturing a semiconductor device having electrostatic discharge protection element
US20040132241A1 (en) * 2000-08-24 2004-07-08 Hitachi, Ltd. Insulated gate field effect transistor and method of fabricating the same
US6825544B1 (en) * 1998-12-09 2004-11-30 Cypress Semiconductor Corporation Method for shallow trench isolation and shallow trench isolation structure
US20060197121A1 (en) * 2005-03-04 2006-09-07 Bae Systems Information And Electronic Systems Integration Inc. Abrupt channel doping profile for fermi threshold field effect transistors
US7135423B2 (en) 2002-05-09 2006-11-14 Varian Semiconductor Equipment Associates, Inc Methods for forming low resistivity, ultrashallow junctions with low damage
US20070072355A1 (en) * 2005-09-28 2007-03-29 Fujitsu Limited Method of manufacturing semiconductor device
US7981800B1 (en) 2006-08-25 2011-07-19 Cypress Semiconductor Corporation Shallow trench isolation structures and methods for forming the same
US8828816B2 (en) 2011-05-25 2014-09-09 Globalfoundries Inc. PMOS threshold voltage control by germanium implantation

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633177A (en) * 1993-11-08 1997-05-27 Advanced Micro Devices, Inc. Method for producing a semiconductor gate conductor having an impurity migration barrier
TW304301B (en) * 1994-12-01 1997-05-01 At & T Corp
US5650350A (en) * 1995-08-11 1997-07-22 Micron Technology, Inc. Semiconductor processing method of forming a static random access memory cell and static random access memory cell
KR100197648B1 (en) * 1995-08-26 1999-06-15 김영환 Method of forming an element isolation insulating film of semiconductor device
US5585286A (en) * 1995-08-31 1996-12-17 Lsi Logic Corporation Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device
US5821147A (en) * 1995-12-11 1998-10-13 Lucent Technologies, Inc. Integrated circuit fabrication
US7232728B1 (en) * 1996-01-30 2007-06-19 Micron Technology, Inc. High quality oxide on an epitaxial layer
US5874346A (en) * 1996-05-23 1999-02-23 Advanced Micro Devices, Inc. Subtrench conductor formation with large tilt angle implant
US5767000A (en) * 1996-06-05 1998-06-16 Advanced Micro Devices, Inc. Method of manufacturing subfield conductive layer
US5811343A (en) * 1996-07-15 1998-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation method for removing fluorine gas inside polysilicon during semiconductor manufacturing to prevent delamination of subsequent layer induced by fluorine outgassing dielectric
US5837585A (en) * 1996-07-23 1998-11-17 Vanguard International Semiconductor Corporation Method of fabricating flash memory cell
KR100232206B1 (en) * 1996-12-26 1999-12-01 김영환 Method of manufacturing semiconductor device
JPH10261588A (en) * 1997-03-19 1998-09-29 Mitsubishi Electric Corp Semiconductor device
US5976956A (en) * 1997-04-11 1999-11-02 Advanced Micro Devices, Inc. Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device
US6037639A (en) 1997-06-09 2000-03-14 Micron Technology, Inc. Fabrication of integrated devices using nitrogen implantation
US5989963A (en) * 1997-07-21 1999-11-23 Advanced Micro Devices, Inc. Method for obtaining a steep retrograde channel profile
TW388087B (en) * 1997-11-20 2000-04-21 Winbond Electronics Corp Method of forming buried-channel P-type metal oxide semiconductor
EP0926739A1 (en) 1997-12-24 1999-06-30 Texas Instruments Incorporated A structure of and method for forming a mis field effect transistor
JP3054123B2 (en) * 1998-06-08 2000-06-19 アプライド マテリアルズ インコーポレイテッド Ion implantation method
US6373114B1 (en) 1998-10-23 2002-04-16 Micron Technology, Inc. Barrier in gate stack for improved gate dielectric integrity
US5953615A (en) * 1999-01-27 1999-09-14 Advance Micro Devices Pre-amorphization process for source/drain junction
US6245649B1 (en) 1999-02-17 2001-06-12 Advanced Micro Devices, Inc. Method for forming a retrograde impurity profile
US6265297B1 (en) 1999-09-01 2001-07-24 Micron Technology, Inc. Ammonia passivation of metal gate electrodes to inhibit oxidation of metal
US6251757B1 (en) * 2000-02-24 2001-06-26 Advanced Micro Devices, Inc. Formation of highly activated shallow abrupt junction by thermal budget engineering
US6458714B1 (en) 2000-11-22 2002-10-01 Micron Technology, Inc. Method of selective oxidation in semiconductor manufacture
US7301180B2 (en) * 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
WO2003001607A1 (en) * 2001-06-21 2003-01-03 Massachusetts Institute Of Technology Mosfets with strained semiconductor layers
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US6806151B2 (en) * 2001-12-14 2004-10-19 Texas Instruments Incorporated Methods and apparatus for inducing stress in a semiconductor device
WO2003105204A2 (en) 2002-06-07 2003-12-18 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US6638802B1 (en) * 2002-06-20 2003-10-28 Intel Corporation Forming strained source drain junction field effect transistors
CN1286157C (en) * 2002-10-10 2006-11-22 松下电器产业株式会社 Semiconductor device and method for fabricating the same
US20040206951A1 (en) * 2003-04-18 2004-10-21 Mirabedini Mohammad R. Ion implantation in channel region of CMOS device for enhanced carrier mobility
US6982229B2 (en) 2003-04-18 2006-01-03 Lsi Logic Corporation Ion recoil implantation and enhanced carrier mobility in CMOS device
JP4746332B2 (en) * 2005-03-10 2011-08-10 Okiセミコンダクタ宮城株式会社 A method of manufacturing a semiconductor device
JP5114829B2 (en) * 2005-05-13 2013-01-09 ソニー株式会社 Semiconductor device and manufacturing method thereof
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7816738B2 (en) * 2005-11-30 2010-10-19 International Business Machines Corporation Low-cost FEOL for ultra-low power, near sub-vth device structures
KR101889469B1 (en) * 2011-10-31 2018-08-21 에스케이하이닉스 주식회사 Complementary metal oxide semiconductor integrated circuit with metal gate and high―k dielectric
US20150255475A1 (en) * 2014-03-07 2015-09-10 Kabushiki Kaisha Toshiba NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF p-CHANNEL MOS TRANSISTOR

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4137103A (en) * 1976-12-06 1979-01-30 International Business Machines Corporation Silicon integrated circuit region containing implanted arsenic and germanium
US4352236A (en) * 1981-07-24 1982-10-05 Intel Corporation Double field oxidation process
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
US4413401A (en) * 1979-07-23 1983-11-08 National Semiconductor Corporation Method for making a semiconductor capacitor
US4536947A (en) * 1983-07-14 1985-08-27 Intel Corporation CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
US4603471A (en) * 1984-09-06 1986-08-05 Fairchild Semiconductor Corporation Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions
US4617066A (en) * 1984-11-26 1986-10-14 Hughes Aircraft Company Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
US4683645A (en) * 1985-06-28 1987-08-04 Northern Telecom Limited Process of fabricating MOS devices having shallow source and drain junctions
US4703551A (en) * 1986-01-24 1987-11-03 Ncr Corporation Process for forming LDD MOS/CMOS structures
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
US4764477A (en) * 1987-04-06 1988-08-16 Motorola, Inc. CMOS process flow with small gate geometry LDO N-channel transistors
US4791610A (en) * 1985-05-24 1988-12-13 Fujitsu Limited Semiconductor memory device formed of a SOI-type transistor and a capacitor
US4835112A (en) * 1988-03-08 1989-05-30 Motorola, Inc. CMOS salicide process using germanium implantation
US4837173A (en) * 1987-07-13 1989-06-06 Motorola, Inc. N-channel MOS transistors having source/drain regions with germanium
US4845047A (en) * 1987-06-25 1989-07-04 Texas Instruments Incorporated Threshold adjustment method for an IGFET
WO1990005993A1 (en) * 1988-11-21 1990-05-31 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
US5141882A (en) * 1989-04-05 1992-08-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor
US5145794A (en) * 1989-09-08 1992-09-08 Fujitsu Limited Formation of shallow junction by implantation of dopant into partially crystalline disordered region
US5312766A (en) * 1991-03-06 1994-05-17 National Semiconductor Corporation Method of providing lower contact resistance in MOS transistors

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4137103A (en) * 1976-12-06 1979-01-30 International Business Machines Corporation Silicon integrated circuit region containing implanted arsenic and germanium
US4413401A (en) * 1979-07-23 1983-11-08 National Semiconductor Corporation Method for making a semiconductor capacitor
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
US4352236A (en) * 1981-07-24 1982-10-05 Intel Corporation Double field oxidation process
US4536947A (en) * 1983-07-14 1985-08-27 Intel Corporation CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
US4603471A (en) * 1984-09-06 1986-08-05 Fairchild Semiconductor Corporation Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions
US4617066A (en) * 1984-11-26 1986-10-14 Hughes Aircraft Company Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
US4791610A (en) * 1985-05-24 1988-12-13 Fujitsu Limited Semiconductor memory device formed of a SOI-type transistor and a capacitor
US4683645A (en) * 1985-06-28 1987-08-04 Northern Telecom Limited Process of fabricating MOS devices having shallow source and drain junctions
US4703551A (en) * 1986-01-24 1987-11-03 Ncr Corporation Process for forming LDD MOS/CMOS structures
US4764477A (en) * 1987-04-06 1988-08-16 Motorola, Inc. CMOS process flow with small gate geometry LDO N-channel transistors
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
US4845047A (en) * 1987-06-25 1989-07-04 Texas Instruments Incorporated Threshold adjustment method for an IGFET
US4837173A (en) * 1987-07-13 1989-06-06 Motorola, Inc. N-channel MOS transistors having source/drain regions with germanium
US4835112A (en) * 1988-03-08 1989-05-30 Motorola, Inc. CMOS salicide process using germanium implantation
WO1990005993A1 (en) * 1988-11-21 1990-05-31 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
US5141882A (en) * 1989-04-05 1992-08-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor
US5145794A (en) * 1989-09-08 1992-09-08 Fujitsu Limited Formation of shallow junction by implantation of dopant into partially crystalline disordered region
US5312766A (en) * 1991-03-06 1994-05-17 National Semiconductor Corporation Method of providing lower contact resistance in MOS transistors

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
Ng et al., "Suppression of Hot-Carrier Degradation in Si MOSFET's by Germanium Doping", IEEE Publication 0741-3106/90/0100-0045, Jan. 1990. *
Ozturk et al., "Optimization of the Germanium Preamorphization Conditions for Shallow-Junction Formation", IEEE Trans. on Electron Devices, vol. 35, No. 5, May 1988, pp. 659-668.*
Pfiester et al., "Anomalous Co-Diffusion Effects of Germanium on Group III and V Dopants", Appl. Phys. Lett., vol. 52, No. 6, Feb. 8, 1988, pp. 471-473.*
Pfiester et al., "Improved CMOS Field Isolation Using Germanium/Boron Implantation", IEEE Electron Devices, vol. 9, No. 8, Aug. 1988, pp. 391-393.*
Pfiester et al., "Improved MOSFET Short-Channel Device Using Germanium Implantation", IEEE Electron Device Letters, vol. 9, No. 7, Jul. 1988, pp. 343-346.*
Pfiester et al., "Novel Germanium/Boron Channel-Stop Implantation for Submicron CMOS", IEDM 1987, pp. 740-743.*

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6696341B1 (en) * 1998-01-21 2004-02-24 Renesas Technology Corp. Method of manufacturing a semiconductor device having electrostatic discharge protection element
US6825544B1 (en) * 1998-12-09 2004-11-30 Cypress Semiconductor Corporation Method for shallow trench isolation and shallow trench isolation structure
US6352912B1 (en) * 2000-03-30 2002-03-05 International Business Machines Corporation Reduction of reverse short channel effects by deep implantation of neutral dopants
US6486510B2 (en) 2000-03-30 2002-11-26 International Business Machines Corporation Reduction of reverse short channel effects by implantation of neutral dopants
US20040132241A1 (en) * 2000-08-24 2004-07-08 Hitachi, Ltd. Insulated gate field effect transistor and method of fabricating the same
US7135423B2 (en) 2002-05-09 2006-11-14 Varian Semiconductor Equipment Associates, Inc Methods for forming low resistivity, ultrashallow junctions with low damage
US20060197121A1 (en) * 2005-03-04 2006-09-07 Bae Systems Information And Electronic Systems Integration Inc. Abrupt channel doping profile for fermi threshold field effect transistors
US7271457B2 (en) 2005-03-04 2007-09-18 Bae Systems Information And Electronic Systems Integration Inc. Abrupt channel doping profile for fermi threshold field effect transistors
US20070072355A1 (en) * 2005-09-28 2007-03-29 Fujitsu Limited Method of manufacturing semiconductor device
US7598162B2 (en) * 2005-09-28 2009-10-06 Fujitsu Microelectronics Limited Method of manufacturing semiconductor device
US7981800B1 (en) 2006-08-25 2011-07-19 Cypress Semiconductor Corporation Shallow trench isolation structures and methods for forming the same
US8828816B2 (en) 2011-05-25 2014-09-09 Globalfoundries Inc. PMOS threshold voltage control by germanium implantation

Also Published As

Publication number Publication date
US5266510A (en) 1993-11-30

Similar Documents

Publication Publication Date Title
US6087208A (en) Method for increasing gate capacitance by using both high and low dielectric gate material
US6501131B1 (en) Transistors having independently adjustable parameters
US5571738A (en) Method of making poly LDD self-aligned channel transistors
US6030874A (en) Doped polysilicon to retard boron diffusion into and through thin gate dielectrics
US6673663B2 (en) Methods of forming field effect transistors and related field effect transistor constructions
US5171700A (en) Field effect transistor structure and method
US6229188B1 (en) MOS field effect transistor and its manufacturing method
US5831306A (en) Asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region
US6020244A (en) Channel dopant implantation with automatic compensation for variations in critical dimension
US6506653B1 (en) Method using disposable and permanent films for diffusion and implant doping
US5166765A (en) Insulated gate field-effect transistor with pulse-shaped doping
US6147383A (en) LDD buried channel field effect semiconductor device and manufacturing method
US5962892A (en) MISFET and complementary MISFET device having high performance source and drain diffusion layer
US7470593B2 (en) Method for manufacturing a cell transistor of a semiconductor memory device
US6124610A (en) Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant
US7767503B2 (en) Hybrid SOI/bulk semiconductor transistors
US5846857A (en) CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance
US4503601A (en) Oxide trench structure for polysilicon gates and interconnects
US5426062A (en) Method for forming a silicon on insulator device
US5766969A (en) Multiple spacer formation/removal technique for forming a graded junction
US4760033A (en) Method for the manufacture of complementary MOS field effect transistors in VLSI technology
US5082794A (en) Method of fabricating mos transistors using selective polysilicon deposition
US6306712B1 (en) Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing
US5998835A (en) High performance MOSFET device with raised source and drain
US6093594A (en) CMOS optimization method utilizing sacrificial sidewall spacer

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

CC Certificate of correction
AS Assignment

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223