USRE36801E - Time delayed digital video system using concurrent recording and playback - Google Patents
Time delayed digital video system using concurrent recording and playback Download PDFInfo
- Publication number
- USRE36801E USRE36801E US08/634,618 US63461896A USRE36801E US RE36801 E USRE36801 E US RE36801E US 63461896 A US63461896 A US 63461896A US RE36801 E USRE36801 E US RE36801E
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- United States
- Prior art keywords
- memory
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- combination
- sequence
- television
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/4448—Receiver circuitry for the reception of television signals according to analogue transmission standards for frame-grabbing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/414—Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
- H04N21/4147—PVR [Personal Video Recorder]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
Definitions
- This invention relates generally to video and audio broadcast recording and playback systems and more particularly, although in its broader aspects not exclusively, to an arrangement for monitoring programming as it is broadcast and for enabling the listener or viewer to pause, replay and fast-forward the broadcast programming.
- VCR video cassette recorder
- VCR video cassette recorder
- the viewer may pause the playback to answer the phone or to view a scene in "stop-action" mode, advance or rewind the recorded material to start the viewing to replay a scene or skip over annoying advertising.
- Digital recording techniques such as those described in U.S. Pat. No. 4,963,995, may be used to store the recorded programming in a random access memory comprising the combination of a semiconductor RAM buffer and a disk memory, permitting a desired programming segment to be immediately accessed and viewed without the time consuming fast-forward and fast-reverse tape motion required in conventional video cassette recorders.
- one or more incoming audio or video signals are continuously digitized, compressed and stored in a buffer memory whenever the invention is in operation whereby, without attention from the user, the invention maintains a "circular buffer" which stores programming received during a preceding time interval of predetermined duration.
- the invention preferably employs a dual-ported memory system operating under microprocessor control.
- a data compression unit is connected to supply compressed digital signals to the writing port of the memory system, and a separate data decompression unit is connected to receive data from the reading port of the memory system.
- the invention advantageously comprises a microcontroller for selecting the buffer memory location from which the recorded programming is read for playback, the microcontroller being in turn controlled.
- a viewer manipulated remote control unit which permits the user to select the portion of the buffered program to be viewed, or alternatively controlled by commands received from a connected computer with the microcontroller and buffer memory acting as a peripheral device.
- the invention advantageously includes means for displaying, at the viewer's request, a mosaic of reduced-size images representing images stored in the buffer at spaced time intervals, thereby allowing the viewer to readily locate and select a scene of interest to be replayed.
- the memory location from which the images are read is altered to display the selected scene.
- programming being received from one or more sources is simultaneously processed by a group of input signal processors, each of which delivers a compressed digital signal to the writing port of the memory system under microprocessor control.
- the rate of transmission of frames of a video broadcast from the buffer to the video display can be increased or decreased by the user to provide stop action or slow-motion effects.
- the amount of compression applied to the signal being stored can be varied by the user to allow longer programs to be recorded (with reduced quality) within the available memory space.
- the sequence of the frames transmitted from the buffer to the video display can be transmitted in reverse order.
- the viewer may skip unwanted segments of the viewed broadcast by altering the location from which the displayed images are read in order to bypass the display of unwanted material.
- the broadcast buffer memory advantageously takes the form of the combination of a random access memory and a magnetic disk memory, the random access memory providing temporary storage of programming which is in the process of being written to and read from the larger capacity disk memory.
- incoming analog broadcast signals are advantageously digitized and compressed prior to storage in the buffer, then decompressed and converted back into analog form for playback.
- the buffer memory system contemplated by the invention preferably incorporates a programmable clock/calendar device which provides control signals for automatically activating the buffer memory to begin recording at a predetermined time in anticipation of scheduled use.
- the invention is equally useful, and indeed simplified when used with high definition television signals which are already digitized and compressed, since those signals may be recorded and played back from the digital video buffer memory without additional processing.
- FIG. 1 is a signal flow diagram of a video buffer system which embodies the invention.
- FIG. 2 is a more detailed hardware block diagram of the video buffer system embodying the invention.
- FIG. 1 of the drawings shows the principal signal flow paths of a preferred embodiment of the invention.
- video signals are transmitted along the pathways indicated by the solid arrows and control signals are sent over paths indicated by the dotted line arrows.
- one or more incoming video signals are combined at a switching node 3 after being processed by one or more input signal processing units shown generally within the dotted rectangle 12.
- the node 3 applies selected ones of the compressed digital signals from the input unit 5 to the input (writing) port of a dual-port memory subsystem 5 comprising a RAM buffer memory 6 and a hard disk magnetic memory 7.
- the memory subsystem 5 continually stores the incoming data, writing over the oldest data stored on the hard disk 7, so that a fixed duration or "time window" of prior recorded signals are recorded in the memory subsystem 5 at all times.
- the recorded information is also continuously read from the memory subsystem 5 and supplied to via a decompressor 8 to a video display unit 10.
- the memory system 5 operates under the control of a microprocessor controller 11 which also controls the operation of the switching node 3, the input unit 4, and the decompressor 8.
- the microprocessor 11 is programmed to respond to commands received from an infrared remote control unit 13 manipulated by the user, or alternatively from a computer control connection 14 which provides direct link to the serial or parallel port of a connected computer (not shown).
- the invention may be operated under direct control of a host computer.
- the control connection 14 may take the form of a direct connection to the internal bus of connected host, with the microprocessor 11, the input unit 4, the switching node 3, the dual-ported RAM 6, and the decompressor 8 being mounted on an expansion circuit card which plugs directly into and is powered by the internal bus of the computer.
- the hard disk memory 7 may be mounted in one or more of the available expansion bays and connected by disk controller circuitry also mounted on the expansion card.
- the invention also advantageously includes a clock/calendar unit 15 which is connected to the microprocessor 11 to automatically activate the system at scheduled times.
- the system need not be in continuous operation but may instead be activated in advance of scheduled use so that the memory subsystem 5 is fully loaded with prior programming at the time viewing begins.
- the memory subsystem 5 stores one or more previously received signals which are supplied by the input unit 4 and selected at the switching node 3 under the control of microprocessor 11.
- the input unit 4 is composed of a one or more of simultaneously operating input signal processors each of which is connected to a source of programming signals. As seen in FIG. 1, one of more of these pathways may be connected to a source of compressed digital HDTV signals selected by an RF tuner as indicated at 4A.
- the input signal processors seen at 4B and 4C each comprise the cascaded combination of an RF tuner for selecting a desired frequency channel and a compressor for converting the selected signal into compressed digital format.
- the input signal processor seen at 4D receives a video baseband signal which is simply compressed and supplied to the switching node 3.
- the user may select for viewing on the monitor 10 not only a particular incoming program but may select any point in time within the stored time window. Accordingly, in response to user commands, the display unit can provide an instant replay of selected programming, fast forward over undesired segments, pause and restart the programming, or provide fast, slow, or reverse motion displays, all of these functions being provided by altering the memory system address at which the programming to be displayed is read.
- a single input signal processor shown consists of an RF tuner 17 connected to receive broadcast signals from an antenna 18 or a cable TV source 19.
- the analog-to-digital converter 20 converts the signal from analog to digital form and transmits the resulting frames of the video broadcast to a compressor 21.
- the compressor 21 compresses the frames in accordance with a compression ratio selected by the microcontroller 22 and transmits the compressed frames to a memory system indicated at 23 where the frames are stored at an addressable location established by the microcontroller 22.
- the microcontroller 22 also selects a location in the memory system 23 from which programming is to be read, and the retrieved signal is supplied to a decompressor 25 which translates the compressed information back into digitally expressed analog sample amplitude values which are supplied to a digital-to-analog converter 26.
- the converter 26 restores the retrieved video signal to its original analog form as received and the analog video signal is applied to a video display 30.
- the already compressed signals may be supplied to the write input of the memory subsystem 23 by a direct connection as indicated at 32.
- the stored digital compressed signals may passed directly to the HDTV display by a connection 33.
- the direct connections 32 and 33 by-pass the analog-to-digital conversion, compression, decompression and digital-to-analog conversion units since HDTV signals are broadcast in digital compressed form suitable for direct recording in the memory system 23, and are decompressed and converted into analog form for display within the standard HDTV receiving apparatus.
- the arrangement shown in FIG. 2 advantageously uses the same memory system to store either form of transmission.
- the compressor 18 and decompressor 25 are preferably implemented by one of the available video encoder/decoder (codec) chip sets, such as Integrated Technology's (ITI) video processor, which supports both the H.261 video communications standard and multimedia standards MPEG and JPEG.
- codec chip sets include the AT&T three-chip AVP-1000, GEC Plessey Semiconductors' VP2611 and a multi-standard chip set from Intel.
- the memory system 23 is preferably comprised of primary high speed random access semiconductor memory 37 and a slower, secondary memory implemented by a high capacity magnetic disk device 39. Transfers to and from the random access memory are supervised by a direct memory access controller 41 which responds to memory access requests received from the microcontroller 22, the compressor 18, and the disk controller associated with disk memory 39.
- the microcontroller 22 operates under program control to perform commands generated by a remote control 42 or alternatively by a personal computer 49 whose serial port may be connected to the serial port of the microcontroller 22.
- the microcontroller 22 comprises one or more integrated circuits to provide a processor, a read-only memory (ROM) which stores the programs executed by the processor, peripheral data handling circuits, and a random access read/write scratchpad memory for storing dynamically changing data.
- ROM read-only memory
- Such microcontrollers are available from a variety of sources and include the Intel386 family of devices which are described in detail in the Microprocessor and Peripheral Handbook, Volume 1 (1989), published by Intel Corporation, Literature Sales, Santa Clara, Calif.
- the microcontroller 22 maintains a "circular buffer" in the memory system 23 in which the incoming video signal is continuously written to a continuously advancing memory location, writing over the oldest recorded data in the memory system as it advances the writing location.
- the read location is completely under the control of the viewer who sends commands from the remote control unit 42 to the microcontroller 23 to perform the following functions:
- the microcontroller 22 maintains the read point at its current location and repeatedly sends a single frame (video screen) of data to the display for stop-action viewing;
- the microprocessor assembles single frame compressed data from equally spaced addresses in the random access memory 37 to form mosaic display frame, each frame consisting of set of reduced-size images which may be viewed simultaneously to reveal the contents of the buffer memory at spaced intervals.
- This mosaic presentation is periodically refreshed until the user selects a specific read point by number using the remote control 42 or personal computer 49, whereupon the microcontroller 22 sets the readpoint to the appropriate memory location and playback continues from that location. Note that this single control enables the user to not only replay past scenes, but to "fast forward” over unwanted programming (assuming the current read point is delayed from the write point by a duration at least equal to the programming to be bypassed.
- CHANNEL SELECTION The user may select a channel in the usual way (using numerical channel selection buttons), or may select the channel to be viewed (and recorded in the buffer) by commanding the tuner 10 to supply a sequence of frames from the available channel signals which are assembled, in compressed form, in the random access memory 37, from which they may be supplied via the decompressor 25 for display on the display unit 30.
- This picture-in-picture or "PIP" feature commonly available only at added expense on conventional television receivers, is accordingly made available at little additional cost or complexity since the necessary instrumentalities are already available.
- the microcontroller 22 may also vary the compression ratio of the compressor 18 to increase the effective capacity of the buffer memory by reducing the resolution, color quality image size of the stored images, to vary the effective programming buffer capacity.
- the microcontroller 22 may advance the read point at an increased or decreased rate commensurate with playback speed selected by the user.
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US08/634,618 USRE36801E (en) | 1992-10-29 | 1996-04-18 | Time delayed digital video system using concurrent recording and playback |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/968,439 US5371551A (en) | 1992-10-29 | 1992-10-29 | Time delayed digital video system using concurrent recording and playback |
US08/634,618 USRE36801E (en) | 1992-10-29 | 1996-04-18 | Time delayed digital video system using concurrent recording and playback |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US07/968,439 Reissue US5371551A (en) | 1992-10-29 | 1992-10-29 | Time delayed digital video system using concurrent recording and playback |
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USRE36801E true USRE36801E (en) | 2000-08-01 |
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US07/968,439 Ceased US5371551A (en) | 1992-10-29 | 1992-10-29 | Time delayed digital video system using concurrent recording and playback |
US08/634,618 Expired - Lifetime USRE36801E (en) | 1992-10-29 | 1996-04-18 | Time delayed digital video system using concurrent recording and playback |
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US07/968,439 Ceased US5371551A (en) | 1992-10-29 | 1992-10-29 | Time delayed digital video system using concurrent recording and playback |
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Cited By (187)
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