US9865194B2 - Display system and method for driving same between normal mode and panel self-refresh (PSR) mode - Google Patents

Display system and method for driving same between normal mode and panel self-refresh (PSR) mode Download PDF

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Publication number
US9865194B2
US9865194B2 US14/991,474 US201614991474A US9865194B2 US 9865194 B2 US9865194 B2 US 9865194B2 US 201614991474 A US201614991474 A US 201614991474A US 9865194 B2 US9865194 B2 US 9865194B2
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Prior art keywords
mode
synchronization signal
psr
image
frame rate
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US20160372077A1 (en
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Ja-Hun Koo
Jong-Deuk Moon
Kyung-hun Lee
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/10—Special adaptations of display systems for operation with variable images
    • G09G2320/103—Detection of image changes, e.g. determination of an index representative of the image change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Definitions

  • the present inventive concept relates to a display system, and more particularly to, a method of driving the display system including a display apparatus.
  • the display device may receive an image signal from a host through a display drive IC to display a static image.
  • a display drive IC may display a static image.
  • memory access and an interface of the host may consume substantial power.
  • eDP embedded display port
  • the eDP standard is an interface standard corresponding to a display port (DP) interface designed for devices equipped with a display such as a laptop/notebook computer, a tablet PC, a netbook, an all-in-one desktop PC, or the like.
  • eDP v1.3 standard includes a panel self-refresh (PSR) technology for the purpose of saving power in the display device.
  • PSR panel self-refresh
  • a flicker may occur due to a frame rate difference between the two modes.
  • a display system includes a graphic processor and a display apparatus.
  • the graphic processor is configured to supply a first image signal and a first synchronization signal.
  • the display apparatus is configured to be driven in a normal mode in which a first image is displayed, during a first period, based on the first image signal and the first synchronization signal provided from the graphic processor, to be driven in a panel self refresh (PSR) mode in which a second image is displayed based on a second image signal stored in a frame buffer of the display apparatus and a second synchronization signal generated in the display apparatus, and to transmit the second synchronization signal of the PSR mode to the graphic processor when a driving mode of the display apparatus is changed from the PSR mode to the normal mode.
  • the graphic processor is configured to generate the first synchronization signal synchronized with the second synchronization signal.
  • the display apparatus may include a timing controller configured to transmit the second synchronization signal to the graphic processor.
  • the graphic processor may be configured to generate a third synchronization signal during a second period disposed between the PSR mode and the first period of the normal mode.
  • a frame rate of the third synchronization signal may gradually increase from a first frame rate corresponding to the second synchronization signal to a second frame rate corresponding to the first synchronization signal during a second period of the normal mode disposed between the PSR mode and the first period of the normal mode.
  • the first image signal may be transmitted through a main channel, and the first synchronization signal may be transmitted through an auxiliary channel.
  • the second synchronization signal may be transmitted through the main channel or the auxiliary channel.
  • the first image signal and the first synchronization signal may be transmitted through an interface based on a display port (DP) standard.
  • DP display port
  • the first image may include a moving image
  • the second image may include a static image
  • a method of driving a display apparatus includes driving the display apparatus in a first period of a normal mode in which a first image is displayed based on a first image signal and a first synchronization signal provided by a graphic processor, driving the display apparatus in a panel self refresh (PSR) mode in which a second image signal stored in a frame buffer of the display apparatus is displayed based on a second synchronization signal generated in the display apparatus, transmitting the second synchronization signal to the graphic processor when a driving mode of the display apparatus is changed from the PSR mode to the normal mode, and receiving the first synchronization signal synchronized with the second synchronization signal from the graphic processor.
  • PSR panel self refresh
  • the method may further include receiving a third synchronization signal whose frame rate gradually increases from a first frame rate corresponding to the second synchronization signal to a second frame rate corresponding to the first synchronization signal during a second period of the normal mode disposed between the PSR mode and the first period of the normal mod.
  • the first image signal may be transmitted through a main channel, and the first synchronization signal may be transmitted through an auxiliary channel.
  • the second synchronization signal may be transmitted through the main channel or the auxiliary channel.
  • the first image signal and the first synchronization signal may be transmitted through an interface based a display port (DP) standard.
  • DP display port
  • a method of driving a display system including a graphic processor and a display apparatus includes detecting, using the graphic processor, a driving mode of the display apparatus by detecting a predetermined value of a mode register of the display apparatus, receiving an entry command apparatus from the graphic processor using a first receiver of the display, changing the driving mode from a normal mode, in which a first image is displayed, to a panel self refresh (PSR) mode, in which a second image is displayed, in response to the received entry command, storing a second image signal corresponding to the second image to a buffer in response to a PSR packet received from the graphic processor through the first receiver, receiving an off-command from the graphic processor using the display apparatus, turning off the first receiver connected to the graphic processor through a main channel in response to the received off-command, maintaining a turn-on state of a second receiver of the display apparatus in response to the received off command, generating a first synchronization signal of the PSR mode based on a clock signal
  • the first image may be a moving image
  • the second image may be a static image
  • the PSR packet may be transmitted during a vertical blanking period of a frame of the PSR mode.
  • the method may further include changing the driving mode of the display apparatus from the PSR mode to a normal mode in response to an exit command received from the graphic processor, and turning on the first receiver in response to an on-command received from the graphic processor.
  • the method may further include transmitting, using the display apparatus, the first synchronization signal of the PSR mode to the graphic processor, and generating, using the graphic processor, a second synchronization signal of the normal mode based on the first synchronization signal.
  • the second synchronization signal may be synchronized with the first synchronization signal.
  • FIG. 1 is a block diagram illustrating a display system according to an exemplary embodiment of the present inventive concept
  • FIG. 2 is a flowchart diagram illustrating a start period of a panel self refresh (PSR) mode according to an exemplary embodiment of the present inventive concept
  • FIG. 3 is a waveform diagram of input and output signals of a timing controller during the start period of the PSR mode according to an exemplary embodiment of the present inventive concept
  • FIG. 4 is a flowchart illustrating an end period of the PSR mode according to an exemplary embodiment of the present inventive concept
  • FIG. 5 is a waveform diagram of input and output signals of a timing controller during the end period of the PSR mode according to an exemplary embodiment of the present inventive concept
  • FIG. 6A is a diagram illustrating display images through a display apparatus
  • FIG. 6B is a diagram illustrating display images through a display apparatus according to an exemplary embodiment of the present invention.
  • FIG. 7 is a waveform diagram of input and output signals of a timing controller during the end period of the PSR mode according to an exemplary embodiment of the present inventive concept.
  • FIGS. 8A and 8B are diagrams illustrating display images through a display apparatus according to an exemplary embodiment of the present inventive concept.
  • FIG. 1 is a block diagram illustrating a display system according to an exemplary embodiment of the present inventive concept.
  • the display system may include a graphic processor 100 and a display apparatus 200 .
  • the graphic processor 100 and the display apparatus 200 may use a display port (DP) interface standard such as DP 1.2a, DP 1.3, embedded DP (eDP) 1.3, eDP1.4, or the like.
  • DP display port
  • eDP embedded DP
  • the graphic processor 100 may include a first controller 110 and a transmitter 120 .
  • the first controller 110 is configured to generate a mode command corresponding to a normal mode in which the display apparatus 200 displays a normal image, or a mode command corresponding to a panel self refresh (PSR) mode in which the display apparatus 200 displays a static image (e.g., a refresh image) based on a mode control signal.
  • the static image may include a text graphic in a state before a text or a cursor is updated when editing a text document.
  • the normal image may include an image that is not a static image. For example, the normal image may include a moving image.
  • the first controller 110 is configured to generate a synchronization signal of the normal mode.
  • the synchronization signal of the normal mode is synchronized with a synchronization signal of the PSR mode based on synchronization data of the PSR mode.
  • the synchronization data of the PSR mode may include a frame rate and a synchronization signal of the PSR mode transmitted from the display apparatus 200 when a driving mode of the display apparatus 200 is changed from the PSR mode to the normal mode.
  • the synchronization signal (e.g., synchronization signal of the PSR mode or the synchronization signal of the normal mode) may include a horizontal synchronization signal, a vertical synchronization signal, a data enable signal, or the like.
  • the transmitter 120 is configured to transmit an image signal, a synchronization signal and a command through a main channel MCH and an auxiliary channel ACH based on a predetermined interface mode to the display apparatus 200 .
  • the image signal may be transmitted through the main channel MCH.
  • the synchronization signal and the command may be transmitted through the auxiliary channel ACH.
  • the display apparatus 200 may include a timing controller 210 , a data driving circuit 230 , a gate driving circuit 250 and a display panel 270 .
  • the timing controller 210 may include a second controller 211 , a receiver 212 , a frame buffer 213 , a data processor 214 , an auxiliary receiver 215 , a signal generator 216 and a mode register (MR) 217 .
  • a second controller 211 may include a second controller 211 , a receiver 212 , a frame buffer 213 , a data processor 214 , an auxiliary receiver 215 , a signal generator 216 and a mode register (MR) 217 .
  • MR mode register
  • the second controller 211 is configured to control an operation of the timing controller 210 .
  • the second controller 211 is configured to control the timing controller 210 such that the timing controller 210 transmits the synchronization data (e.g., the frame rate and the synchronization signal of the PSR mode) of the PSR mode to the graphic processor 100 when the driving mode of the display apparatus 200 is changed from the PSR mode to the normal mode.
  • the synchronization data e.g., the frame rate and the synchronization signal of the PSR mode
  • the receiver 212 is connected to the transmitter 110 of the graphic processor 100 through the main channel MCH.
  • the receiver 212 is configured to receive the image signal from the graphic processor 100 through the main channel MCH.
  • the receiver 212 may transmit the synchronization data (e.g., the frame rate and the synchronization signal of the PSR mode) of the PSR mode to the graphic processor 100 when the driving mode of the display apparatus 200 is changed from the PSR mode to the normal mode.
  • the frame buffer 213 is configured to store a static image signal corresponding to the static image received through the receiver 212 .
  • the display apparatus 200 displays the static image using the static image signal stored in the frame buffer 213 .
  • the data processor 214 is configured to process an image signal (e.g., the static image signal) to correspond to a resolution of the display panel 270 .
  • the data processor 214 is configured to compensate the image signal using various algorithms and to provide the data driving circuit 230 with the compensated image signal DATA.
  • the auxiliary receiver 215 is connected to the transmitter 110 of the graphic processor 100 through the auxiliary channel ACH.
  • the auxiliary receiver 215 transmits the synchronization signal and the command to the graphic processor 100 through the auxiliary channel ACH and receives the synchronization signal and the command from the graphic processor 100 through the auxiliary channel ACH.
  • the signal generator 216 is configured to generate a synchronization signal for displaying the normal image in the display panel 270 based on the synchronization signal received through the auxiliary receiver 215 from the graphic processor 100 .
  • the synchronization signals for driving the data driving circuit 230 and the gate driving circuit 250 may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, a clock signal, a vertical start signal, or the like.
  • the signal generator 216 is configured to generate a synchronization signal for displaying the static image in the display panel 270 based on a clock signal generated from an oscillator of the display apparatus 200 .
  • the mode register (MR) 217 is configured to store predetermined values respectively corresponding to driving modes (e.g., the normal mode and the PSR mode) of the display apparatus 200 .
  • the display apparatus 200 may be driven according to a driving mode corresponding to a predetermined value stored in the mode register 217 .
  • the data driving circuit 230 is configured to convert the data signal DATA into a data voltage and to provide a data line DL of the display panel 270 with the data voltage based on the synchronization signal (e.g., synchronization signal of the PSR mode or the synchronization signal of the normal mode).
  • the synchronization signal e.g., synchronization signal of the PSR mode or the synchronization signal of the normal mode.
  • the gate driving circuit 250 is configured to generate a gate signal and to provide a gate line GL of the display panel 270 with the gate signal based on the synchronization signal (e.g., synchronization signal of the PSR mode or the synchronization signal of the normal mode).
  • the synchronization signal e.g., synchronization signal of the PSR mode or the synchronization signal of the normal mode.
  • FIG. 2 is a flowchart diagram illustrating a start period of a PSR mode according to an exemplary embodiment of the present inventive concept.
  • FIG. 3 is a waveform diagram of input and output signals of a timing controller during the start period of the PSR mode according to an exemplary embodiment of the present inventive concept.
  • the graphic processor 100 is configured to transmit a command (e.g., an entry command) for starting the PSR mode to the receiver 212 of the timing controller 210 of the display apparatus 200 based on a control signal PSR_ENTRY.
  • a driving mode of the display apparatus 200 is changed from the normal mode to the PSR mode (Step S 101 ). This operation may be referred to as a “PSR mode Entry”.
  • the static image may include a text graphic in a state before a text or a cursor is updated when editing a text document.
  • the graphic processor 100 is configured to detect predetermined values stored in the mode register 217 .
  • the graphic processor 100 detects a first value of the predetermined values stored in the mode register 217 (Step S 102 ). Detecting the predetermined value may be performed through the auxiliary channel ACH.
  • the first controller 110 of the graphic processor 100 is configured to generate a PSR active packet PSR_ACT and to transmit the PSR active packet PSR_ACT to the receiver 212 of the timing controller 210 (Step S 103 ).
  • the PSR active packet PSR_ACT may be transmitted through the main channel MCH.
  • the PSR active packet PSR_ACT may be transmitted during a vertical blanking period of a frame, as shown in FIG. 3 .
  • the timing controller 210 is configured to store an image signal (e.g., a static image signal) of a present frame received through the main channel MCH to the frame buffer 213 in response to the PSR active packet PSR_ACT (Step S 104 ).
  • the frame buffer 213 is configured to store an image signal corresponding to an n-th frame.
  • the image signal corresponding to an n-th frame may correspond to the static image.
  • n is a positive integer.
  • the timing controller 210 is configured to change the predetermined value of the mode register 217 into a second value corresponding to the PSR mode in response to the PSR active packet PSR_ACT.
  • the display apparatus 200 may display the static image (Step S 105 ).
  • the graphic processor 100 When storing the image signal of the n-th frame to the frame buffer 213 is finished, the graphic processor 100 is configured to transmit an OFF command to the timing controller 210 (Step S 106 ).
  • the OFF command is a command for turning off a power of the receiver 212 such that a communication between the transmitter 120 and the receiver 212 is cut off.
  • the OFF command may be transmitted through the main channel MCH or the auxiliary channel ACH. Therefore, the power of the receiver 212 is turned off and the main channel MCH is blocked. In addition, power of the auxiliary receiver 215 and the auxiliary channel ACH remain turn on state.
  • the signal generator 216 of the timing controller 210 is configured to generate a synchronization signal (e.g., a data enable signal OUTPUT_DE) of the PSR mode in which the display panel 270 displays the static image.
  • the signal generator 216 may be configured to generate the synchronization signal of the PSR mode based on a clock signal generated from an oscillator of the timing controller 210 .
  • the data enable signal OUTPUT_DE corresponding to the PSR mode may be equal to a data enable signal INPUT_DE corresponding to the n-th frame.
  • the data enable signal OUTPUT_DE may have a predetermined frame rate different from that of the data enable signal INPUT_DE corresponding to the n-th frame.
  • the display apparatus 200 is configured to begin to output the image signal (e.g., the static image signal) corresponding to the n-th frame stored in the frame buffer 213 to the display panel 270 in response to an (n+1)-th frame.
  • the image signal e.g., the static image signal
  • the display apparatus 200 begins to be driven according to the PSR mode in response to the (n+1)-th frame such that the static image corresponding to the image signal (e.g., the static image signal) corresponding to the n-th frame is displayed in the display panel 270 .
  • the static image corresponding to the image signal e.g., the static image signal
  • the static image is displayed with the PSR mode in which the receiver 212 is turned off, and thus, electrical power consumption of the display apparatus 200 may be decreased.
  • FIG. 4 is a flowchart illustrating an end period of the PSR mode according to an exemplary embodiment of the present inventive concept.
  • FIG. 5 is a waveform diagram of input and output signals of a timing controller during the end period of the PSR mode according to an exemplary embodiment of the present inventive concept.
  • the graphic processor 100 is configured to transmit a command (e.g., an exit command) for ending the PSR mode to the timing controller 210 of the display apparatus 200 based on a control signal PSR_EXIT.
  • a driving mode of the display apparatus 200 is changed from the PSR mode to the normal mode (Step S 201 ).
  • This operation may be referred to as a “PSR mode Exit”.
  • the exit command may be transmitted through the auxiliary channel ACH.
  • the graphic processor 100 is configured to transmit a wake-up command to the timing controller 210 through the auxiliary channel ACH which is in a turn-on state during the PSR mode (Step S 202 ).
  • the timing controller 210 may respond to the wake-up command through the auxiliary channel ACH.
  • the graphic processor 100 is configured to transmit an ON command (for turning on the power source of the receiver 212 ) to the timing controller 210 when the timing controller 210 wakes up (Step S 203 ).
  • the ON command may be transmitted through the main channel MCH or the auxiliary channel ACH.
  • the timing controller 210 is configured to transmit the synchronization data of the PSR mode (e.g., the frame rate and the synchronization signal of the PSR mode) to the graphic processor 100 (Step S 204 ).
  • the synchronization data of the PSR mode may be referred to as “PSR synchronization data”.
  • the PSR synchronization data may be transmitted to the graphic processor 100 through the main channel MCH or the auxiliary channel ACH.
  • the first controller 110 of the graphic processor 100 is configured to control (or generate) a frame rate and a synchronization signal of the normal mode based on the PSR synchronization data.
  • the graphic processor 100 is configured to transmit an idle image pattern to the timing controller 210 prior to transmitting an image signal (e.g., a normal image signal) of the normal image.
  • an image signal e.g., a normal image signal
  • the graphic processor 100 is configured to transmit a PSR inactive packet PSR_INACT to the timing controller 210 (Step S 205 ).
  • the PSR inactive packet PSR_INACT may be transmitted through the main channel MCH or the auxiliary channel ACH.
  • the PSR inactive packet PSR_INACT may be transmitted during a vertical blanking period of a frame, as shown in FIG. 53 .
  • the timing controller 210 is configured to change the predetermined value of the mode register MS to the first value corresponding to the normal mode.
  • the graphic processor 100 is configured to start a transmission of the image signal corresponding to the normal image.
  • the image signal corresponding to the normal image may be transmitted to the receiver 212 of the timing controller 210 through the main channel MCH.
  • the graphic processor 100 is configured to generate a synchronization signal (e.g., a data enable signal INPUT DE) of the normal mode synchronized with the PSR synchronization signal of the PSR mode, and to transmit the generated synchronization signal (e.g., INPUT DE) of the normal mode to the timing controller 210 through the auxiliary channel ACH (Step S 206 ).
  • the graphic processor 100 may generate the synchronization signal (e.g., a data enable signal INPUT DE) of the normal mode based on the synchronization signal of the PSR mode.
  • the signal generator 216 of the timing controller 210 is configured to generate a synchronization signal (e.g., a data enable signal OUTPUT DE) of the normal mode based on the synchronization signal (e.g., INPUT DE) of the normal mode received from the graphic processor 100
  • the display apparatus 200 is configured to display the normal image based on the synchronization signal (e.g., OUTPUT DE) of the normal mode generated by the signal generator 216 , in synchronization with the synchronization signal of the PSR mode (Step S 207 ).
  • FIG. 6A is a diagram illustrating display images through a display apparatus
  • FIG. 6B is a diagram illustrating display images through a display apparatus according to an exemplary embodiment of the present invention.
  • a display apparatus displays the static image with a frame rate (e.g., 60 Hz) during the PSR mode.
  • a graphic processor receives a mode control signal PSR_EXIT that changes a driving mode of the display apparatus from the PSR mode to the normal mode
  • the display apparatus displays a normal image with a predetermined frame rate (for example, 50 Hz) during a re-synchronization period, which corresponds to, for example, about 4 to 5 frames, in response to the mode control signal PSR_EXIT.
  • the display apparatus displays the normal image with the frame rate of 60 Hz. For example, referring to the display images of FIG.
  • the frame rate (e.g., 50 Hz) during the re-synchronization period is different from the frame rate (e.g., 60 Hz) during periods of the PSR mode and the normal mode, and thus, the flicker defect occurs due to a difference in frame rate between the re-synchronization period and the period of the PSR mode or between the re-synchronization period and the period of the normal mode.
  • the display apparatus 200 displays the static image with a frame rate (e.g., 60 Hz) during the PSR mode.
  • the graphic processor 100 receives the mode control signal PSR_EXIT that changes a driving mode of the display apparatus 200 from the PSR mode to the normal mode, the display apparatus 200 transmits the PSR synchronization data to the graphic processor 100 .
  • the graphic processor 100 generates the synchronization signal of the normal mode synchronized with the synchronization signal of the PSR mode, and transmits the generated synchronization signal of the normal mode to the display apparatus 200 .
  • the graphic processor 100 may generate the synchronization signal of the normal mode based on the synchronization signal of the PSR mode.
  • the display apparatus 200 may display the normal image based on the synchronization signal of the normal mode transmitted from the graphic processor 100 , in synchronization with the synchronization signal of the PSR mode. Therefore, display defects (e.g., flickers) occurring due to a de-synchronization between the PSR mode and the normal mode may be eliminated or decreased.
  • display defects e.g., flickers
  • the re-synchronization period positioned between the PSR mode and the normal mode as described with reference to FIG. 6A may be omitted, and thus, the flicker defect may be eliminated or decreased.
  • FIG. 7 is a waveform diagram of input and output signals of a timing controller during the end period of the PSR mode according to an exemplary embodiment of the present inventive concept.
  • a method of driving the display system is described when the display image is changed from the static image with a first frame rate (e.g., 50 Hz) to the normal image (e.g., a moving image) with a second frame rate (e.g., 60 Hz).
  • a first frame rate e.g., 50 Hz
  • the normal image e.g., a moving image
  • a second frame rate e.g. 60 Hz
  • the graphic processor 100 When the mode control signal PSR_EXIT for changing a display image from the static image with the first frame rate (e.g., 50 Hz) to the normal image with the second frame rate (e.g., 60 Hz) is received (e.g., PSR mode Exit operation begins), the graphic processor 100 is configured to transmit an exit command for ending the PSR mode to the timing controller 210 of the display apparatus 200 based on the mode control signal PSR_EXIT.
  • the mode control signal PSR_EXIT for changing a display image from the static image with the first frame rate (e.g., 50 Hz) to the normal image with the second frame rate (e.g., 60 Hz) is received (e.g., PSR mode Exit operation begins)
  • the graphic processor 100 is configured to transmit an exit command for ending the PSR mode to the timing controller 210 of the display apparatus 200 based on the mode control signal PSR_EXIT.
  • the graphic processor 100 is configured to transmit a wake-up command to the timing controller 210 through the auxiliary channel ACH which is in a turn-on state during the PSR mode.
  • the timing controller 210 may respond to the wake-up command through the auxiliary channel ACH.
  • the graphic processor 100 is configured to transmit an ON command for turning on the power source of the receiver 212 to the timing controller 210 , when the timing controller 210 wakes up.
  • the ON command may be transmitted through the main channel MCH or the auxiliary channel ACH.
  • the timing controller 210 is configured to transmit the synchronization data of the PSR mode (e.g., the frame rate of 50 Hz and the synchronization signal of the PSR mode) to the graphic processor 100 .
  • the PSR synchronization data may be transmitted to the graphic processor 100 through the main channel MCH or the auxiliary channel ACH.
  • the graphic processor 100 is configured to transmit an idle image pattern to the timing controller 210 prior to transmitting an image signal (e.g., a normal image signal) of the normal image with the second rate (e.g., 60 Hz).
  • an image signal e.g., a normal image signal
  • the second rate e.g. 60 Hz
  • the graphic processor 100 is configured to transmit a PSR inactive packet PSR_INACT to the timing controller 210 .
  • the PSR packet PSR_INACT may be transmitted through the main channel MCH or the auxiliary channel ACH.
  • the PSR inactive packet PSR_INACT may be transmitted in a vertical blanking period of a frame, as shown in FIG. 7 .
  • the timing controller 210 is configured to change the predetermined value in the mode register MS to the first value corresponding to the normal mode of the display apparatus 200 .
  • the graphic processor 100 is configured to start a transmission of the image signal corresponding to the normal image.
  • the image signal corresponding to the normal image may be transmitted to the receiver 212 of the timing controller 210 through the main channel MCH.
  • the graphic processor 100 is configured to generate a plurality of synchronization signals of the normal mode based on the synchronization data of the PSR mode (e.g., the frame rate and the synchronization signal of the PSR mode).
  • the plurality of synchronization signals of the normal mode may correspond to a plurality of frame rates, respectively, which is gradually changed from the first frame rate (e.g., 50 Hz) corresponding to the static image to the second frame rate (e.g., 60 Hz) corresponding to the normal image during a predetermined period FVP (e.g., a first normal mode period) disposed between the PSR mode driven with the first frame rate and the normal mode driven with the second frame rate.
  • FVP e.g., a first normal mode period
  • the graphic processor 100 may sequentially generate the synchronization signals of the normal mode based on the synchronization data of the PSR mode.
  • the graphic processor 100 is configured to transmit the synchronization signals generated to respectively correspond to the plurality of frame rates during the predetermined period FVP to the timing controller 210 .
  • the timing controller 210 is configured to display the normal images on the display panel 270 based on the synchronization signals of the normal mode respectively corresponding to the plurality of frame rates ranging between the first frame rate (e.g., 50 Hz) and the second frame rate (e.g., 60 Hz).
  • the timing controller 210 may be configured to display the normal images on the display panel 270 based on a synchronization signal corresponding to the second frame rate (e.g., 60 Hz).
  • the display panel 270 sequentially displays the static images with the first frame rate (e.g., 50 Hz), the normal images with the frame rates (e.g., 51 Hz to 59 Hz) changing between the first frame rate and the second frame rate (e.g., 60 Hz), and the normal images with the second frame rate.
  • the first frame rate e.g., 50 Hz
  • the normal images with the frame rates e.g., 51 Hz to 59 Hz
  • the second frame rate e.g. 60 Hz
  • a plurality of normal images frame rates of which are gradually changed from the first frame rate (e.g., 50 Hz) of the static image to the second frame rate (e.g., 60 Hz) of the normal image, is inserted between the PSR mode in which the static image is displayed with the first frame rate and the normal mode in which the normal image is displayed with the second frame rate, and thus, the flicker defect of the display apparatus 200 may be eliminated or decreased.
  • FIG. 7 illustrates that frame rates of a static image and a normal image are 50 Hz and 60 Hz, respectively, the present inventive concept is not limited thereto.
  • FIGS. 8A and 8B are diagrams illustrating display images through a display apparatus according to an exemplary embodiment of the present inventive concept.
  • the graphic processor receives the synchronization data of the PSR mode (e.g., the first frame rate of 50 Hz and the synchronization signal having the first frame rate) from the display apparatus in response to the mode control signal PSR_EXIT.
  • the graphic processor generates a synchronization signal of 60 Hz synchronized with the synchronization signal of 50 Hz, which, for example, included in the synchronization data of the PSR mode received from the display apparatus, and transmits the generated synchronization signal of 60 Hz to the display apparatus.
  • the graphic processor may generate the synchronization signal of 60 Hz based on the synchronization signal of 50 Hz.
  • the display apparatus displays the normal image with the second frame rate (e.g., 60 Hz) based on the synchronization signal of 60 Hz generated through the graphic processor, in synchronization with the synchronization signal of 50 Hz.
  • the graphic processor receives the synchronization data (e.g., the first frame rate and the synchronization signal having the first frame rate) of the PSR mode from the display apparatus in response to the mode control signal PSR_EXIT.
  • the graphic processor generates a plurality of synchronization signals respectively corresponding to a plurality of frame rates based on the synchronization data (e.g., the first frame rate and the synchronization signal having the first frame rate) of the PSR mode.
  • the plurality of frame rates may be increased in a gradual manner from the first frame rate (e.g., 50 Hz) corresponding to the static image to the second frame rate (e.g., 60 Hz) corresponding to the normal image during a predetermined period FVP disposed between the PSR mode and the normal mode.
  • the graphic processor may sequentially generate the synchronization signals respectively corresponding to the plurality of frame rates (e.g., 51 Hz to 59 Hz) based on the synchronization data of the PSR mode.
  • the graphic processor transmits the generated synchronization signals respectively corresponding to the plurality of frame rates during the predetermined period to the timing controller (e.g., 210 of FIG. 1 ).
  • the frame rate may suddenly be changed from the first frame rate (e.g., 50 Hz) corresponding to the PSR mode and of the second frame rate corresponding to the normal mode (e.g., 60 Hz), and thus, the flicker defect may occur due to the abrupt change in the frame rate.
  • the first frame rate e.g., 50 Hz
  • the second frame rate e.g. 60 Hz
  • a plurality of normal images frame rates of which are gradually changed from the first frame rate (e.g., 50 Hz) of the static image to the second frame rate (e.g., 60 Hz) of the normal image, is inserted between the PSR mode driven with the first frame rate (e.g., 50 Hz) and the normal mode driven with the second frame rate (e.g., 60 Hz), and thus, the flicker defect may be eliminated or decreased.
  • FIG. 8 illustrates that frame rates of a static image and a normal image are 50 Hz and 60 Hz, respectively, the present inventive concept is not limited thereto.
  • the display apparatus transmits synchronization data (e.g., the frame rate and the synchronization signal) of the PSR mode to the graphic processor (e.g., 100 of FIG. 1 ).
  • the graphic processor generates a synchronization signal of the normal mode synchronized with the synchronization signal of the PSR mode, which is received from, e.g., the display apparatus, and transmits the generated synchronization signal of the normal mode to, e.g., the display apparatus (e.g., 200 of FIG. 1 ).
  • the graphic processor may generate the synchronization signal of the normal mode based on the synchronization signal of the PSR mode. Therefore, the display apparatus displays a normal image based on the synchronization signal of the normal mode generated in synchronization with the synchronization signal of the PSR mode, and thus, display defects (e.g., flickers) occurring due to a change of the frame rate between the PSR mode and the normal mode may be eliminated or decreased.
  • display defects e.g., flickers

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