US9692427B2 - Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock - Google Patents

Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock Download PDF

Info

Publication number
US9692427B2
US9692427B2 US14/610,025 US201514610025A US9692427B2 US 9692427 B2 US9692427 B2 US 9692427B2 US 201514610025 A US201514610025 A US 201514610025A US 9692427 B2 US9692427 B2 US 9692427B2
Authority
US
United States
Prior art keywords
holdover
pll
clock signal
control circuit
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US14/610,025
Other languages
English (en)
Other versions
US20150222273A1 (en
Inventor
Gordon John Allan
Justin L. Fortier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hittite Microwave LLC
Original Assignee
Hittite Microwave LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hittite Microwave LLC filed Critical Hittite Microwave LLC
Priority to US14/610,025 priority Critical patent/US9692427B2/en
Priority to US14/613,271 priority patent/US9281829B2/en
Assigned to HITTITE MICROWAVE CORPORATION reassignment HITTITE MICROWAVE CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ALLAN, GORDON JOHN, FORTIER, JUSTIN L.
Publication of US20150222273A1 publication Critical patent/US20150222273A1/en
Assigned to HITTITE MICROWAVE LLC reassignment HITTITE MICROWAVE LLC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: HITTITE MICROWAVE CORPORATION
Application granted granted Critical
Publication of US9692427B2 publication Critical patent/US9692427B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/146—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers

Definitions

  • Embodiments of the invention relate to electronic circuits, and more particularly, to phase-locked loops (PLLs).
  • PLLs phase-locked loops
  • PLLs Phase-locked loops
  • PLLs are used in a variety of applications for generating an output clock signal having a controlled phase and frequency relationship to a reference clock signal.
  • PLLs can be used in, for example, frequency synthesizers, telecommunications systems, and/or chip-to-chip communication.
  • Clock generation circuits frequently include a PLL used to lock an output clock signal generated by the PLL's voltage controlled oscillator (VCO) to the phase of an incoming reference clock signal.
  • VCO voltage controlled oscillator
  • a high precision tunable oscillator can be phase-locked to a noisy reference clock signal, and the PLL can operate to suppress phase noise and to attenuate jitter.
  • an apparatus in one aspect includes a first phase-locked loop (PLL), a control circuit, a holdover circuit, and a variable resistor.
  • the first PLL is configured to receive an input clock signal, and includes a loop filter.
  • the control circuit is configured to receive one or more reference clock signals and to generate the input clock signal based on the one or more reference clock signals.
  • the holdover circuit is configured to generate a holdover voltage at an output.
  • the variable resistor is electrically connected in series between the output of the holdover circuit and an input to the loop filter.
  • the control circuit is further configured to generate a resistance control signal to control a resistance of the variable resistor.
  • a method of clock signal generation includes generating an input clock signal for a PLL using a control circuit, generating a holdover voltage at an output of a holdover circuit that is electrically connected to an input of a loop filter of the PLL via a variable resistor, and controlling a resistance of the variable resistor using the control circuit.
  • a clock system in another aspect, includes a PLL, a control circuit, a holdover circuit, and a variable resistor.
  • the PLL is configured to receive an input clock signal, and includes a loop filter.
  • the control circuit is configured to receive one or more reference clock signals and to generate the input clock signal.
  • the control circuit is further configured to control the PLL to one of a plurality of operating modes including a holdover mode and a phase locking mode.
  • the holdover circuit is configured to generate a holdover voltage at an output.
  • the variable resistor is electrically connected between the output of the holdover circuit and an input to the loop filter.
  • the control circuit is further configured to control a resistance of the variable resistor.
  • FIG. 1 is a schematic diagram of a clock system according to one embodiment.
  • FIG. 2 is a schematic diagram of a clock generation circuit according to one embodiment.
  • FIG. 3 is a schematic diagram of a portion of a clock generation circuit according to one embodiment.
  • FIG. 4 is a schematic diagram of a portion of a clock generation circuit according to another embodiment.
  • FIG. 5 is a timing diagram for a clock generation circuit in accordance with one embodiment.
  • a phase-locked loop can include a holdover circuit to control the PLL's operation during periods when an active reference clock signal becomes lost or invalid.
  • the PLL can receive two or more reference clock signals, and can switch from a first reference clock signal to a second reference clock signal when the first reference clock signal is determined to be unreliable.
  • the PLL can operate in a holdover mode in which the tuning voltage of the PLL's VCO can be held substantially constant by the holdover circuit to inhibit the VCO's oscillation frequency from changing.
  • the PLL's feedback loop can be disabled, such as by disconnecting the output of the PLL's charge pump from the input of the PLL's loop filter.
  • the PLL can operate open-loop during holdover.
  • a PLL can receive a single reference clock signal, and can operate during holdover when the reference clock signal is determined to be unreliable. The PLL can remain the holdover mode until the reference clock signal is determined to be reliable.
  • Communication systems such as those operating in a network or cellular infrastructures, can be specified to generate a stable clock signal generated from one or more noisy reference clock signals.
  • one or more of the communication system's reference clock signals can correspond to a clock signal recovered from a noisy and/or intermittent data stream using a clock and data recovery (CDR) circuit.
  • CDR clock and data recovery
  • the communication system can include a cascade of two or more PLLs to meet overall phase noise and/or jitter specifications.
  • a first PLL can be used to generate a stable reference clock signal from a noisy reference clock signal
  • the second PLL can provide frequency synthesis or multiplication using the stable reference clock signal.
  • Generating a reference clock signal from a noisy signal source can result in the reference clock signal regularly becoming lost or invalid.
  • multiple reference clock signals can be provided to a PLL for redundancy.
  • the PLL's reference clock signal can be changed or switched and the PLL's holdover circuit can maintain the oscillation frequency of the PLL's VCO substantially constant during the change of reference clock signals. After the reference clock signal is switched, the PLL can reacquire phase-lock.
  • a PLL operates in holdover while a reference clock signal is unreliable, and reacquires phase-lock to the reference clock signal once the reference clock signal becomes reliable.
  • the PLL can be a low-jitter PLL having a loop filter designed for low loop bandwidth, which in turn causes a slow loop response.
  • the slow loop response can cause the PLL's output clock signal to have large frequency variations during the transient period when the PLL reacquires phase lock.
  • transient frequency variation namely frequency perturbations
  • the PLL's output clock signal can be used to modulate or demodulate radio frequency signals, and frequency perturbations can generate spurious emissions, transmissions out-of-band, communication errors, and/or dropped calls.
  • a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor.
  • the control circuit generates an input clock signal for the PLL based on a selected reference clock signal.
  • the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch to provide an electrical connection from the output of the holdover circuit to the input of the PLL's loop filter through the variable resistor.
  • the control circuit After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock. For example, the control circuit can incrementally increase the variable resistor's resistance during the transition such that the holdover circuit sinks or sources a smaller portion of the charge pump's output current over time. Thus, operation of the holdover circuit is gradually phased out, and the PLL operates with a soft transition from holdover to reacquiring phase lock.
  • Configuring a PLL to have a soft transition from holdover to reacquiring phase lock can enhance the clock system's performance. For example, using a soft transition can prevent large voltage perturbations in the VCO's tuning voltage, which can limit a change to the VCO's oscillation frequency during the transition.
  • a PLL that operates without soft transition may have a VCO tuning voltage that reaches a power high or power low supply voltage rail during the transition from holdover to reacquiring phase lock. Accordingly, the PLL's herein can exhibit enhanced transient performance, increased stability, and/or smaller phase noise and jitter during the transition from holdover to reacquiring phase lock.
  • variable resistor refers to a resistor having a controllable resistance, including not only analog controlled resistors, but also digitally controlled resistors such as programmable/selectable resistors.
  • FIG. 1 is a schematic diagram of a clock system 100 according to one embodiment.
  • the clock system 100 includes a clock generation circuit 102 , a clock and data recovery (CDR) circuit 104 , a first reference clock generator 106 , a second reference clock generator 108 , a third reference clock generator 110 , a high precision tunable oscillator or VCXO 112 , a serializer/deserializer (SerDes) circuit 114 , a field programmable gate array (FPGA)/digital signal processor (DSP) 116 , analog-to-digital converter (ADC) circuits 118 , digital-to-analog converter (DAC) circuits 120 , downstream dividers 122 , a first mixer 124 , and a second mixer 126 .
  • CDR clock and data recovery
  • ADC analog-to-digital converter
  • DAC digital-to-analog converter
  • the clock system 100 can be used in a variety of applications, including, for example, cellular infrastructure applications.
  • the clock system 100 can represent a portion of a base station.
  • the clock generation circuit 102 receives a plurality of clock reference clock signals including a first reference clock signal RCLK 1 , a second reference clock signal RLCK 2 , and a third clock signal RCLKN.
  • FIG. 1 illustrates the clock generation circuit 102 as receiving three reference clock signals
  • the clock generation circuit 102 can receive more or fewer reference clock signals.
  • the clock generation circuit 102 receives N reference clock signals, where N is selected to be in the range of about 1 to about 4.
  • the reference clock signals are derived from the CDR circuit 104 .
  • the reference clock signals can correspond to recovered clock signals from clock and data recovery operations of the CDR circuit 104 on a data stream (DATA).
  • the clock generation circuit 102 can generate output clock signals based on a selected or active reference clock signal chosen from the reference clock signals RCLK 1 -RCLKN.
  • the clock generation circuit 102 can use one active or primary reference signal, for example, the first reference clock signal RCLK 1 , which is used to generate the output clock signals.
  • the other reference clock signals RCLK 2 -RCLKN can serve as back-up clock reference signals should the first reference clock signal RCLK 1 become invalid or dropped.
  • the clock generation circuit 102 can generate stable high-frequency low-jitter clock signals for a variety of circuits. For example, in the illustrated configuration, the clock generation circuit 102 generates clock signals for the SerDes circuit 114 , the FPGA/DSP 116 , the ADC circuits 118 , the DAC circuits 120 , the downstream dividers 122 , and first and second mixers 124 , 126 for modulating in-phase (I) and quadrature-phase (Q) components of an intermediate frequency (IF) signal. In certain configurations, one or more output clock signals generated by the clock generation circuit 102 can be further processes to generate additional clock signals.
  • the downstream dividers 122 provide division operations to generate a plurality of clock signals (CLK 1 , CLK 2 , . . . , CLK 13 , CLK 14 , in this example).
  • CLK 1 , CLK 2 , . . . , CLK 13 , CLK 14 in this example.
  • the clock generation circuit 102 can generate clock signals for other circuitry.
  • the illustrated clock system 100 depicts various non-limiting examples of circuitry that can receive clock signals from the clock generation circuit 102 .
  • the clock generation circuit 102 can include a low loop bandwidth PLL 143 , which can be used to lock the phase of the VCXO 112 to the selected reference clock signal.
  • the VCXO 112 comprises a tunable crystal oscillator.
  • teachings herein are applicable to other types of controllable oscillators, including, for example, inductor-capacitor (LC) tank oscillators, ring oscillators, and/or rotary traveling wave oscillators (RTWOs).
  • LC inductor-capacitor
  • RTWOs rotary traveling wave oscillators
  • the clock generation circuit 102 includes a holdover circuit 140 , a holdover switch 141 , and a variable resistor 142 .
  • the holdover switch 141 can be closed or turned on to place the low loop bandwidth PLL 143 into holdover, in which an oscillation frequency of the VCXO 112 is maintained substantially constant while the selected reference clock signal is changed.
  • the feedback loop of the low loop bandwidth PLL 143 can be disabled, the holdover switch 141 can be turned on, and a tuning voltage at the input of the VCXO 112 can be held substantially constant by the holdover circuit 140 .
  • the low loop bandwidth PLL 143 can reacquire phase lock with the updated reference clock signal. Additionally, while the holdover switch 141 remains turned on and the feedback loop of the PLL 143 is enabled, the resistance of the variable resistor 142 is controlled over time to provide the PLL 143 with a soft transition from holdover to reacquiring phase lock. For example, the variable resistor's resistance can be incrementally increased during the transition from holdover to reacquiring phase lock such that operation of the holdover circuit 141 is gradually phased out, and the PLL 143 operates with a soft transition from holdover to reacquiring phase lock.
  • FIG. 2 is a schematic diagram of a clock generation circuit 200 according to one embodiment.
  • the clock generation circuit 200 includes a first PLL 204 a , a second PLL 204 b , a holdover circuit 240 , a holdover switch 241 , a variable resistor 242 , a first reference clock buffer 202 a , a second reference clock buffer 202 b , a third reference clock buffer 202 c , a fourth reference clock buffer 202 d , a first reference clock divider 203 a , a second reference clock divider 203 b , a third reference clock divider 203 c , a fourth reference clock divider 203 d , a PLL control circuit 205 , a first VCXO divider 227 , an array of output dividers 282 , a first output clock buffer 284 a , a second output clock buffer 284 b , a third output clock buffer 284 c , and a fourth output clock buffer
  • the first reference clock buffer 202 a is used to buffer the first reference clock signal RCLK 1 to generate a first buffered reference clock signal, which is divided using the first reference clock divider 203 a to generate a first divided reference clock signal RCX 1 for the PLL control circuit 205 .
  • the second reference clock buffer 202 b and the second reference clock divider 203 b are used to buffer and divide the second reference clock signal RCLK 2 to generate a second divided reference clock signal RCX 2 for the PLL control circuit 205 .
  • the third reference clock buffer 202 c and the third reference clock divider 203 c are used to buffer and divide the third reference clock signal RCLK 3 to generate a third divided reference clock signal RCX 3 for the PLL control circuit 205 .
  • the fourth reference clock buffer 202 d and the fourth reference clock divider 203 d are used to buffer and divide the fourth reference clock signal RCLK 4 to generate a fourth divided reference clock signal RCX 4 for the PLL control circuit 205 .
  • the illustrated configuration illustrates one example of clock signal conditioning that can occur on one or more reference clock signals before they are provided to a PLL control circuit. However, the teachings herein are applicable to other configurations, including implementations in which one or more of the reference clock signals are not conditioned.
  • the PLL control circuit 205 generates a first input clock signal RC 1 , which is provided as an input to the first PLL 204 a .
  • the first input clock signal RC 1 can be generated based on a selected reference clock signal chosen from the divided reference clock signals RCX 1 -RCX 4 by the PLL control circuit 205 .
  • the PLL control circuit 205 can be used to monitor one or more of the divided reference clock signals RCX 1 -RCX 4 to determine when the chosen reference clock signal is unreliable.
  • the first PLL 204 a generates a local clock signal LCLK from the first input clock signal RC 1 .
  • the first PLL 204 a can be implemented to have a relatively low loop bandwidth to provide a relatively high amount of jitter attenuation.
  • the first input clock signal RC 1 can be a noisy and/or intermittent signal, and implementing the first PLL 204 a with relatively low loop bandwidth can decrease jitter of the local clock signal LCLK.
  • the second PLL 204 b uses a buffered version of the local clock signal LCLK as a reference clock signal for frequency synthesis.
  • FIG. 2 illustrates a configuration using a cascade of two PLLs, the teachings herein are applicable to clock generation circuits using more or fewer PLLs.
  • the first PLL 204 includes a first input clock divider 206 a , a first phase-frequency detector and charge pump (PFD/CP) 207 a , a charge pump output switch 217 a , a first loop filter 208 a , a VCXO 216 a , a clock buffer 219 a , and a first feedback divider 218 a .
  • the first input clock divider 206 a divides the first input clock signal RC 1 to generate a first PFD/CP reference clock signal REF.
  • the clock buffer 219 a buffers the local clock signal LCLK to generate a buffered clock signal BCLK, which is divided using the first feedback divider 218 a to generate a first feedback clock signal FBK for the first PFD/CP 207 a .
  • the first PFD/CP 207 a generates a charge pump output signal (CPS), which is provided as an input to the charge pump output switch 217 a .
  • the charge pump output switch 217 a receives a tristate signal TRI, which is used to selectively disable the feedback loop of the first PLL 204 a .
  • the charge pump output switch 217 a further generates a loop filter input signal CPO, which is provided as an input to the first loop filter 208 a .
  • the output of the holdover circuit 240 is also electrically connected to the input of the first loop filter 208 a via the holdover switch 241 and the variable resistor 242 .
  • the first loop filter 208 a generates a first tuning voltage Vtune, which is provided as an input to the VCXO 216 a .
  • the VCXO 216 a generates the local clock signal LCLK, which can have a frequency of oscillation that changes with a voltage level of the tuning voltage Vtune.
  • FIG. 2 illustrates a configuration in which the first PLL 204 a includes the charge pump output switch 217 a for selectively disabling the first PLL's feedback loop
  • the PLL control circuit 205 disables or enables the first PLL's feedback loop by providing the tristate signal TRI to the first PFD/CP 207 a .
  • the tristate signal TRI can be used to control pump up and pump down signals to turn off positive and negative current sources in the PFD/CP's charge pump when the PLL's feedback loop is disabled.
  • the second PLL 204 b can be a high frequency PLL designed to receive the buffered input clock BCLK of low frequency, for instance 122.88 MHz, and to provide a second local clock signal LCLK 2 of higher frequency, for instance 2457.6 MHz, to the array of output dividers 282 .
  • the array of output dividers 282 can generate divided output clock signals, which can be buffered by the output clock buffers 284 a - 284 d to generate a plurality of high frequency output clock signals OCLK 1 -OCLK 4 .
  • the PLL control circuit 205 generates a variety of control signals for controlling operation of the first PLL 204 a , including a tristate signal TRI, a resistance control signal CRES, a first holdover control signal CHA, and a second holdover control signal CHB.
  • the PLL control circuit 205 controls an operating mode of the first PLL 204 a to one of a plurality of operating modes including a holdover mode and a phase locking mode.
  • the PLL control circuit 205 operates the first PLL 204 a in the holdover mode, the PLL control circuit 205 turns on the holdover switch 241 and disables a feedback loop of the first PLL 204 a by turning off the charge pump output switch 217 a .
  • the PLL control circuit 205 operates the first PLL 204 a in the phase locking mode, the PLL control circuit 205 enables the feedback loop of the first PLL 204 a by turning on the charge pump output switch 217 a.
  • the tristate signal TRI can be used to selectively break or disable the first PLL's feedback loop. For example, when the charge pump output switch 217 a is opened or turned off using the tristate signal TRI, the feedback loop of the first PLL 204 a can be disabled. However, when the charge pump output switch 217 a is closed or turned on using the tristate signal TRI, the charge pump output signal CPS can be provided to the first loop filter 208 a .
  • the first holdover control signal CHA can be used to open or close the holdover switch 241 , thereby selectively activating an electrical path between the output of the holdover circuit 240 and the input to the first loop filter 208 a .
  • the resistance control signal CRES can be used to control a resistance value of the variable resistor 242 , and can be controlled over time to provide a soft transition from the holdover mode to the phase locking mode, as will be described further below.
  • the second holdover control signal CHB can be used to control the holdover circuit 240 , including, for example, to establish a desired holdover voltage when the first PLL 204 a operates in the holdover mode.
  • the second PLL 204 b includes a second VCXO divider 215 , a second input clock divider 206 b , a second PFD/CP 207 b , a second loop filter 208 b , a voltage controlled oscillator (VCO) 216 b , and a second feedback divider 218 b .
  • the second VCXO divider 215 receives the buffered clock signal BCLK from the first PLL 204 a and generates a second input clock signal RC 2 , which is provided as an input to the second input clock divider 206 b .
  • the second input clock divider 206 b divides the second input clock signal RC 2 to generate a second PFD/CP reference clock signal REF 2 , which is provided as an input to the second PFD/CP 207 b .
  • Including the second VCXO divider 215 can enhance the flexibility of the second PLL 204 b .
  • other configurations are possible, such as implementations in which the second VCXO divider 215 is omitted.
  • the second PFD/CP 207 b receives a second feedback clock signal FBK 2 from the second feedback divider 218 b , and generates a second loop filter input signal CPO 2 .
  • the second loop filter 208 b receives the second loop filter input signal CPO 2 , and generates a second tuning voltage for controlling an oscillation frequency of the VCO 216 b .
  • the VCO 216 b generates a second local clock signal LCLK 2 , which is provided as an input to the second feedback divider 218 b and as an input to the array of output dividers 282 .
  • the first input clock signal RC 1 is generated by the PLL control circuit 205 based on a selected reference clock signal chosen from the reference clock signals RCLK 1 -RCLK 4 , which are conditioned in this example with buffering and optional frequency dividing. As discussed earlier, all or a portion of the reference clock signals RCLK 1 -RCLK 4 can be noisy and/or intermittent. In certain configurations, one of the reference clock signals, for instance, the first reference clock signal RCLK 1 , serves as a primary reference clock signal while the additional reference clock signals serve as backup reference clock signals.
  • the illustrated clock generation circuit 200 includes the PLL control circuit 205 , which generates control signals for controlling the mode of operation of the first PLL 204 a .
  • the first PLL 204 a can be phase-locked to the first input clock signal RC 1 , which is generated based on a selected reference clock signal chosen from the reference clock signals RCLK 1 -RCLK 4 .
  • the PLL control circuit 205 can monitor one or more of the reference clock signals RCLK 1 -RCLK 4 or clock signals derived therefrom to determine when a particular reference clock signal is valid. For example, in certain configurations, the PLL control circuit 205 monitors the first input clock signal RC 1 to determine whether or not the first input clock signal RC 1 is reliable. In the illustrated configuration, the PLL control circuit 205 can further receive a clock signal from the first VCXO divider 227 , which can aid in determining the reliability of a reference clock signal.
  • the PLL control circuit 205 can compare the clock signal from the first VCXO divider 227 to the first input clock signal RC 1 to determine when the first input clock signal RC 1 has become unsuitable for use as a reference.
  • the first input clock signal RC 1 can be determined to be unreliable for a variety of reasons, including, for example, when the first input clock signal RC 1 has a phase noise greater than a threshold and/or when the first input clock signal RC 1 does not toggle for a certain duration of time.
  • the PLL control circuit 205 can turn off the charge pump output switch 217 a and turn on the holdover switch 241 to operate the first PLL 204 a in the holdover mode.
  • FIG. 2 illustrates a configuration that includes the holdover switch 241 for selectively operating the first PLL 204 a in the holdover mode
  • the holdover switch 241 is omitted, and the PLL control circuit 205 can control the resistance of the variable resistor 242 to a high resistance value to disconnect the output of the holdover circuit 240 from the input of the first loop filter 208 a .
  • the resistance of the variable resistor 242 can be controlled to selectively operate the first PLL 204 a in the holdover mode.
  • the holdover circuit 240 can generate a holdover voltage Va 1 , which is provided to the input of the first loop filter 208 a via the variable resistor 242 and the holdover switch 241 . In this manner, the holdover voltage Va 1 is provided to the input of the first loop filter 208 a , and the first tuning voltage Vtune can be stabilized to inhibit the oscillation frequency of the VCXO 216 a from changing.
  • the PLL control circuit 205 can change or update the reference clock signal, such that the first input clock signal RC 1 is generated by the chosen reference clock signal.
  • FIG. 2 illustrates a configuration in which the holdover switch 241 is electrically connected between the output of the holdover circuit 240 and the variable resistor 242
  • the teachings herein are applicable to other configurations, such as configurations in which the variable resistor 242 is electrically connected between the output of the holdover circuit 240 and the holdover switch 241 .
  • the order of the holdover switch 241 and the variable resistor 242 in the series can be reversed.
  • the PLL control circuit 205 can control the first PLL 204 a to reacquire phase lock by transitioning the first PLL 204 a from the holdover mode to the phase locking mode.
  • the PLL control circuit 205 controls a resistance of the variable resistor 242 over time to provide a soft transition from the holdover mode to the phase locking mode.
  • the PLL control circuit 205 can maintain both the holdover switch 241 and the charge pump output switch 217 a turned on, and can increase the resistance of the variable resistor 242 over time to provide the first PFD/CP 207 a with increasingly greater control over the voltage level of the tuning voltage Vtune.
  • the PLL control circuit 205 can incrementally increase the variable resistor's resistance over time such that a greater amount of the charge generated at the output of the first PFD/CP 207 a reaches the input of the first loop filter 208 a .
  • Configuring the first PLL 204 a to have a soft transition from holdover to reacquiring phase lock can prevent large voltage perturbations in the tuning voltage Vtune during the transition from the holdover mode to the phase locking mode.
  • a PLL that operates without soft transition may have a VCO tuning voltage that reaches a power high or power low supply voltage rail during the transition.
  • the PLL control circuit 205 can turn off or open the holdover switch 241 while maintaining the charge pump output switch 217 a closed. Thus, the PLL control circuit 205 can return the first PLL 204 a to normal operation once phase lock has been reacquired.
  • FIG. 3 is a schematic diagram of a portion of a clock generation circuit according to one embodiment.
  • the illustrated diagram includes the VCXO 216 a , the charge pump output switch 217 a , the holdover circuit 240 , the holdover switch 241 , and the variable resistor 242 , which can be as described earlier.
  • the illustrated diagram further includes a PFD/CP 307 and a loop filter 308 .
  • the loop filter 308 includes a first capacitor 311 (C 1 ), a first resistor 312 (R 1 ), and a second capacitor 314 (C 2 ).
  • the first resistor 312 and the first capacitor 311 are electrically connected in series between an input of the loop filter 308 and a power low supply voltage V 1
  • the second capacitor 314 is electrically connected in parallel to the series combination of the first resistor 312 and the first capacitor 311 between the loop filter's input and the power low supply voltage V 1 .
  • the loop filter 308 illustrates one example of a suitable loop filter for a PLL, the teachings herein are applicable to other configurations of loop filters, including, for example, active loop filters or passive loop filters.
  • the illustrated PFD/CP 307 includes a phase-frequency detector (PFD) 304 , a first or positive current source 308 , a second or negative current source 310 , a first current source switch 303 , and a second current source switch 305 .
  • the PFD 307 compares timing of the PFD/CP reference clock signal REF to timing of the first feedback clock signal FBK to generate a pump up signal UP and a pump down signal DOWN, which control the first and second current source switches 303 , 305 , respectively. As shown in FIG.
  • the positive current source 308 is electrically connected in series with the first current source switch 303 between a power high supply voltage V 2 and the output of the PFD/CP 307
  • the negative current source 310 is electrically connected in series with the second current source switch 305 between the power low supply voltage V 1 and the output of the PFD/CP 307
  • the positive current source 308 is operable to source current
  • the negative current source 310 is operable to sink current
  • the PFD 304 controls the first and second current source switches 303 , 305 using the pump up signal UP and the pump down signal DOWN to control a charge pump output current I CP generated by the PFD/CP 307 .
  • both the holdover switch 241 and the charge pump output switch 217 a are illustrated in the closed or turned on state.
  • the charge pump output current I CP can correspond to a sum of a loop filter input current I_Lpf flowing into the loop filter 208 a and a holdover current I HOLD flowing into the holdover circuit 240 .
  • the VCXO 216 a is implemented with high input impedance, and a current flowing into the input of the VCXO 216 a is relatively small and not shown.
  • other configurations are possible.
  • variable resistor 241 is electrically connected between the output of the holdover circuit 240 and the input of the loop filter 308 .
  • the resistance of the variable resistor 242 can be controlled to control a ratio of the loop filter input current I_Lpf to the holdover current I HOLD .
  • a PLL control circuit (for example, the PLL control circuit 205 of FIG. 2 ) can provide a PLL with a soft transition from holdover to reacquiring phase lock.
  • the PLL control circuit can close both the holdover switch 241 and the charge pump output switch 217 a , and gradually increase the resistance of the variable resistor 242 to reduce a fraction of the charge pump current I CP that flows into or out of the holdover circuit 240 over time.
  • control over the oscillation frequency of the VCXO 216 a can be gradually passed from the holdover circuit 240 to the PFD/CP 307 to reduce frequency perturbations during the transition from holdover to reacquiring phase lock.
  • a PLL control circuit when transitioning from holdover to reacquiring phase lock, a PLL control circuit (for example, the PLL control circuit 205 of FIG. 2 ) initially controls the resistance control signal CRES to set the variable resistor's resistance to an initial or low resistance value. Thereafter, the PLL control circuit incrementally increases the resistance of the variable resistor 242 using the resistor control signal CRES from the low resistance value to a final or large resistance value. In certain configurations, the large resistance value is at least a factor of 10,000 times greater than the low resistance value. In this manner, the holdover current I HOLD transitions from a large fraction of the charge pump current I CP to a small fraction of the charge pump current I CP over time to provide a soft transition. Providing soft transition in this manner can inhibit large variation in the loop filter's input voltage.
  • the holdover circuit 240 can provide a holdover voltage Va 1 at an output of the holdover circuit 240 .
  • the holdover voltage Va 1 can be controlled to a desired loop filter input voltage.
  • the holdover circuit 240 generates the holdover voltage Va 1 based on monitoring the input voltage of the loop filter 308 .
  • FIG. 4 is a schematic diagram of a portion of a clock generation circuit according to another embodiment.
  • the illustrated diagram includes the first PFD/CP 207 a , the first loop filter 208 a , the VCXO 216 a , the charge pump output switch 217 a , the holdover switch 241 , and the variable resistor 242 , which can be as described earlier.
  • the illustrated diagram further includes a holdover circuit 400 .
  • the illustrated holdover circuit 400 includes an analog-to-digital converter (ADC) 404 , a digital averaging circuit 406 , and a digital-to-analog converter 402 .
  • ADC analog-to-digital converter
  • the DAC 402 and the ADC 404 receive the second holdover control signal CHB, which can be used to control conversion operations of the DAC 402 and the ADC 404 .
  • the ADC 404 and the digital average 402 can be used to generate a digital representation of the average loop filter voltage at the input of the loop filter 208 a .
  • the holdover circuit 400 can use the average loop filter voltage to generate the holdover voltage Va 1 when the PLL is operated in the holdover mode.
  • the DAC 402 can be used to convert the digital representation of the average loop filter voltage to the holdover voltage Va 1 .
  • the holdover voltage Va 1 corresponds to an average value of the input voltage to the loop filter 208 a over a window of time.
  • the second holdover control signal CHB can be used to maintain the holdover voltage Va 1 substantially constant during the holdover mode.
  • FIG. 4 illustrates one embodiment of a holdover circuit
  • teachings herein are applicable to other configurations of holdover circuits.
  • FIG. 5 is a timing diagram for a clock generation circuit in accordance with one embodiment.
  • the timing diagram has been annotated to mark a first time interval 502 in which the first PLL 204 a of FIG. 2 operates normally with the holdover switch 241 turned off and the feedback loop of the first PLL 204 a enabled. Additionally, the timing diagram has been annotated to mark a second time interval 504 , corresponding to when the first PLL 204 a of FIG. 2 operates in a holdover mode. Furthermore, the timing diagram includes a third time interval 506 in which a soft transition to reacquiring phase lock is provided, and a fourth time interval 508 in which the first PLL 204 a returns to normal operation.
  • the PLL control circuit 205 of FIG. 2 generates the first input clock signal RC 1 based on the first reference clock signal RCLK 1 .
  • the first reference clock signal RCLK 1 becomes unreliable and no longer toggles at a time 211 .
  • the PLL control circuit 205 determines that the first reference clock signal RCLK 1 is unreliable, the PLL control circuit 205 operates the first PLL 204 a in the holdover mode by controlling the first holdover control signal CHA and the tristate signal TRI to turn on the holdover switch 241 and turn off the charge pump output switch 217 a .
  • the resistor control signal CRES has an initial or zero setting during the holdover mode.
  • the PLL control circuit 205 of FIG. 2 closes the charge pump output switch 217 a and gradually increments the resistance value of the variable resistor 242 over time.
  • the PLL control circuit 205 provides a soft transition between holdover and reacquiring phase lock by gradually incrementing the resistor control signal CRES from the initial value ( 0 ) to a maximum value (max). Thereafter, the PLL control circuit 205 turns off the holdover switch 241 to return the first PLL 204 a to normal operation.
  • the tuning voltage Vtune changes slightly. This change in the tuning voltage Vtune can correspond to a difference in the holdover voltage Va 1 relative to a voltage level of the tuning voltage Vtune during phase lock.
  • the third time interval 506 shows the sequence of waveforms in transitioning from holdover to reacquiring phase lock.
  • the loop filter input current I_Lpf initially is low and of long duration. Additionally, the peak loop filter input current I_Lpf increases over time but is active for a shorter duration as the first PLL 204 a of FIG. 2 becomes closer to acquiring phase lock.
  • the maximum variation of the tuning port voltage can be, for example, within 50 mV.
  • Devices employing the above described clock generation circuits can be implemented into various electronic devices.
  • Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, etc.
  • Examples of the electronic devices can also include circuits of optical networks or other communication networks.
  • the consumer electronic products can include, but are not limited to, an automobile, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multifunctional peripheral device, etc.
  • the electronic device can include unfinished products, including those for industrial, medical and automotive applications.

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
US14/610,025 2014-01-31 2015-01-30 Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock Active US9692427B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/610,025 US9692427B2 (en) 2014-01-31 2015-01-30 Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock
US14/613,271 US9281829B2 (en) 2014-01-31 2015-02-03 Apparatus and methods for fast charge pump holdover on signal interruption

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201461933971P 2014-01-31 2014-01-31
US14/610,025 US9692427B2 (en) 2014-01-31 2015-01-30 Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock

Publications (2)

Publication Number Publication Date
US20150222273A1 US20150222273A1 (en) 2015-08-06
US9692427B2 true US9692427B2 (en) 2017-06-27

Family

ID=52423659

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/610,025 Active US9692427B2 (en) 2014-01-31 2015-01-30 Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock

Country Status (3)

Country Link
US (1) US9692427B2 (de)
EP (1) EP2903164B1 (de)
CN (1) CN104821819B (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11177815B2 (en) 2020-03-13 2021-11-16 Analog Devices International Unlimited Company Timing alignment systems with gap detection and compensation

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8299826B2 (en) * 2009-08-25 2012-10-30 Sitime Corporation Phase locked loop circuitry having switched resistor loop filter circuitry, and methods of operating same
EP2903163B1 (de) * 2014-02-04 2019-08-21 Hittite Microwave LLC Vorrichtung und Verfahren zum Holdover von Signalunterbrechung bei einer Schnellladungspumpe
US9509490B1 (en) * 2015-09-21 2016-11-29 Apple Inc. Reference clock sharing
CN111418158B (zh) * 2017-12-08 2024-04-09 深圳开阳电子股份有限公司 时钟系统、电子装置、处理方法
US20200195262A1 (en) * 2018-12-12 2020-06-18 Industrial Technology Research Institute Frequency synthesizer and method thereof
US10516403B1 (en) 2019-02-27 2019-12-24 Ciena Corporation High-order phase tracking loop with segmented proportional and integral controls
US10735007B1 (en) 2019-05-28 2020-08-04 Harris Global Communications, Inc. Method of limiting frequency overshoot in a timing recovery loop
US11265009B2 (en) * 2019-05-30 2022-03-01 Texas Instruments Incorporated Waveform synthesizer using multiple digital-to-analog converters
US10727844B1 (en) * 2019-05-31 2020-07-28 Silicon Laboratories Inc. Reference clock frequency change handling in a phase-locked loop
US10693475B1 (en) 2019-05-31 2020-06-23 Silicon Laboratories Inc. Gradual frequency transition with a frequency step
CN117544164B (zh) * 2024-01-08 2024-04-09 芯耀辉科技有限公司 基于开环控制的闭环稳定性的校正方法、设备及介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0652642A1 (de) 1993-11-05 1995-05-10 AT&T Corp. Verfahren und Vorrichtung für eine Phasenregelschleife mtit Überbrückungsmodus
EP1006662A2 (de) 1998-12-04 2000-06-07 Fujitsu Limited Integrierte Halbleiterschaltung
US6259328B1 (en) * 1999-12-17 2001-07-10 Network Equipment Technologies, Inc. Method and system for managing reference signals for network clock synchronization
US20020021178A1 (en) * 1999-02-25 2002-02-21 Toshiro Yoshida Phase-locked loop circuit having rate-of-change detector
US20100244914A1 (en) * 2009-03-30 2010-09-30 Chul-Woo Kim Clock generator to reduce long term jitter
US20120280735A1 (en) * 2011-05-02 2012-11-08 National Semiconductor Corporation Apparatus and method to hold pll output frequency when input clock is lost

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1898268B1 (de) * 2005-06-27 2013-07-31 Sakata Inx Corporation Verfahren zur herstellung eines flüssigen entwicklers und in diesem verfahren hergestellter flüssiger entwickler
CN101964655B (zh) * 2009-07-22 2012-06-06 河南森源电气股份有限公司 一种平衡误差消除式的高精度数字锁相方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0652642A1 (de) 1993-11-05 1995-05-10 AT&T Corp. Verfahren und Vorrichtung für eine Phasenregelschleife mtit Überbrückungsmodus
EP1006662A2 (de) 1998-12-04 2000-06-07 Fujitsu Limited Integrierte Halbleiterschaltung
US20020021178A1 (en) * 1999-02-25 2002-02-21 Toshiro Yoshida Phase-locked loop circuit having rate-of-change detector
US6259328B1 (en) * 1999-12-17 2001-07-10 Network Equipment Technologies, Inc. Method and system for managing reference signals for network clock synchronization
US20100244914A1 (en) * 2009-03-30 2010-09-30 Chul-Woo Kim Clock generator to reduce long term jitter
US20120280735A1 (en) * 2011-05-02 2012-11-08 National Semiconductor Corporation Apparatus and method to hold pll output frequency when input clock is lost

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Extended European Search Reported received in European Patent Application No. 15153213.2, dated Jun. 12, 2015, in 5 pages.
Office Action Issued in Chinese Application No. 201510047905.9, dated May 4, 2017, in 9 pages.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11177815B2 (en) 2020-03-13 2021-11-16 Analog Devices International Unlimited Company Timing alignment systems with gap detection and compensation

Also Published As

Publication number Publication date
US20150222273A1 (en) 2015-08-06
CN104821819A (zh) 2015-08-05
CN104821819B (zh) 2018-11-02
EP2903164B1 (de) 2016-08-24
EP2903164A1 (de) 2015-08-05

Similar Documents

Publication Publication Date Title
US9692427B2 (en) Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock
US9281829B2 (en) Apparatus and methods for fast charge pump holdover on signal interruption
US7948286B2 (en) Bandwidth control apparatus for phase lock loop and method thereof
US20130106476A1 (en) Temperature compensation in a pll
US7869769B2 (en) Method and apparatus for reconfigurable frequency generation
US8283984B2 (en) Method and apparatus of phase locking for reducing clock jitter due to charge leakage
CN103297042A (zh) 一种可快速锁定的电荷泵锁相环电路
KR100965764B1 (ko) 위상고정루프 및 그 제어방법
CN210899136U (zh) 一种锁相环电路、芯片、电路板以及电子设备
US8629728B2 (en) VCO control circuit and method thereof, fast locking PLL and method for fast locking PLL
US7295824B2 (en) Frequency multiplier pre-stage for fractional-N phase-locked loops
EP1474872B1 (de) Schwingungsarme phasenregelschleife
WO2023124558A1 (zh) 锁相环电路、控制方法、电荷泵及芯片
US7782104B2 (en) Delay element array for time-to-digital converters
US9948312B2 (en) Phase lock loop with a digital charge pump
US8618851B2 (en) Phase-locked loop apparatus and tuning voltage providing circuit thereof
JP2024501878A (ja) フィードバック分周器のない低電力フラクショナルアナログｐｌｌ
US8638141B1 (en) Phase-locked loop
US20090206894A1 (en) Phase-Locked Loop with Adaptive Performance
US9673826B2 (en) Receiving device
WO1998010520A2 (en) Frequency synthesis circuit having a charge pump
JP2013058904A (ja) 位相同期回路及びテレビジョン信号受信回路
CN107979370A (zh) 一种宽频带高精度的锁相环电路
JP2004235833A (ja) 位相同期ループ回路
CN116170012A (zh) 一种具有频率保持和参考频率平滑切换的锁相环电路

Legal Events

Date Code Title Description
AS Assignment

Owner name: HITTITE MICROWAVE CORPORATION, MASSACHUSETTS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ALLAN, GORDON JOHN;FORTIER, JUSTIN L.;REEL/FRAME:034880/0023

Effective date: 20150119

AS Assignment

Owner name: HITTITE MICROWAVE LLC, MASSACHUSETTS

Free format text: CHANGE OF NAME;ASSIGNOR:HITTITE MICROWAVE CORPORATION;REEL/FRAME:039482/0038

Effective date: 20140821

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4