US9577019B2 - Organic light-emitting diode display and method of manufacturing the same - Google Patents

Organic light-emitting diode display and method of manufacturing the same Download PDF

Info

Publication number
US9577019B2
US9577019B2 US14/644,049 US201514644049A US9577019B2 US 9577019 B2 US9577019 B2 US 9577019B2 US 201514644049 A US201514644049 A US 201514644049A US 9577019 B2 US9577019 B2 US 9577019B2
Authority
US
United States
Prior art keywords
electrode
connecting wire
wire
driving
tft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US14/644,049
Other languages
English (en)
Other versions
US20160111484A1 (en
Inventor
Jinsung An
Juwon YOON
Jeongsoo LEE
Jiseon Lee
Choongyoul Im
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AN, JINSUNG, IM, CHOONGYOUL, Lee, Jeongsoo, LEE, JISEON, YOON, JUWON
Publication of US20160111484A1 publication Critical patent/US20160111484A1/en
Application granted granted Critical
Publication of US9577019B2 publication Critical patent/US9577019B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H01L27/3276—
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • the described technology generally relates to an organic light-emitting diode (OLED) display and a method of manufacturing the same.
  • OLED organic light-emitting diode
  • OLED displays do not require a separate light source, and thus their thickness and weight are generally less than those of liquid crystal displays (LCDs). Also, OLED displays have other favorable characteristics, such as low power consumption, high luminance, and high response speed.
  • One inventive aspect is an OLED display and a method of manufacturing the same.
  • each of the plurality of pixels includes: a plurality of wires that include a first wire extending in a first direction and a second wire extending in a second direction; a plurality of switching thin-film transistors that are connected to the plurality of wires; a driving thin-film transistor that supplies a driving current to each of the plurality of pixels; a storage capacitor that is connected to the plurality of wires and the driving thin-film transistor; and a connecting wire that connects the driving thin-film transistor and any one of the plurality of switching thin-film transistors and is formed adjacent to the second wire, wherein the connecting wire is formed on a different layer from the second wire.
  • the first wire can include a scanning line transmitting a scanning signal
  • the second wire can include a data line transmitting a data signal
  • the connecting wire can be formed below the second wire.
  • the connecting wire can be formed above a driving gate electrode of the driving thin-film transistor.
  • the connecting wire can be formed on a same layer as a second electrode of the storage capacitor.
  • a first electrode of the storage capacitor can be connected to a driving gate electrode of the driving thin-film transistor, and the connecting wire can include one end connected to any one of the plurality of switching thin-film transistors via a contact hole, and another end contacting the first electrode of the storage capacitor through a contact hole.
  • a second electrode of the storage capacitor can overlap the first electrode of the storage capacitor and include a concave portion at a location corresponding to a region where the other end of the connecting wire and the first electrode of the storage capacitor overlap each other.
  • Each of the plurality of pixels can further include a pixel electrode that is formed on the connecting wire and at least partially overlaps the connecting wire.
  • the display apparatus can further include: a first insulating layer that covers the connecting wire; and a second insulating layer that is formed between the first insulating layer and the pixel electrode.
  • Any one of the plurality of switching thin-film transistors can be an initialization thin-film transistor that transmits an initialization voltage to a gate electrode of the driving thin-film transistor.
  • Another aspect is a method of manufacturing a display device, the method including: forming a connecting wire that connects any one of a plurality of switching thin-film transistors and a driving thin-film transistor comprised in the display apparatus; and forming a second wire that extends in a second direction, crosses a first wire extending in a first direction, is formed adjacent to the connecting wire, and transmits a signal to each of a plurality of pixels included in the display apparatus, wherein the connecting wire and the second wire are formed on different layers.
  • the storage capacitor can include a first electrode and a second electrode, and the forming of the connecting wire can include forming the connecting wire on a same layer as one of the first and second electrodes.
  • the connecting wire can be formed on the same layer as the second electrode of the storage capacitor, and the second electrode of the storage capacitor can include a concave portion formed at a location corresponding to a region where another end of the connecting wire and the first electrode of the storage capacitor overlap each other.
  • the connecting wire can be formed below the second wire.
  • the second wire can include a data line.
  • the method can further include forming a pixel electrode that is formed on the second wire and at least partially overlaps the connecting wire.
  • the method can further include: forming a first insulating layer that is formed between the connecting wire and the second wire; and forming a second insulating layer that is formed on the first insulating layer and below the pixel electrode.
  • Another aspect is a display device comprising a plurality of pixels, wherein each of the pixels comprises a plurality of wires comprising a first wire extending in a first direction and a second wire extending in a second direction crossing the first direction, wherein the second wire has top and bottom portions opposing each other.
  • the pixels also comprise a plurality of switching thin-film transistors (TFTs) electrically connected to the wires, a driving TFT configured to supply a driving current, a storage capacitor electrically connected to the wires and the driving TFT, and a connecting wire electrically connecting the driving TFT to a selected one of the switching TFTs, wherein the connecting wire has top and bottom portions opposing each other, and wherein at least the top portions of the connecting wire and the second wire are formed on different layers.
  • TFTs switching thin-film transistors
  • the first wire comprises a scanning line configured to provide a scanning signal
  • the second wire comprises a data line configured to provide a data signal
  • the top portion of the connecting wire is formed below the top portion of the second wire.
  • the driving TFT comprises a driving gate electrode, and wherein the connecting wire is formed over the driving gate electrode.
  • the storage capacitor comprises first and second electrodes, wherein the top portion of the connecting wire is formed on the same layer as at least a portion of the second electrode.
  • the driving TFT comprises a driving gate electrode, wherein the first electrode of the storage capacitor is electrically connected to the driving gate electrode, and wherein the connecting wire has i) one lateral end electrically connected to the one of the switching TFTs via a first contact hole and ii) another lateral end electrically connected to the first electrode of the storage capacitor through a second contact hole.
  • the second electrode of the storage capacitor at least partially overlaps the first electrode of the storage capacitor and has a concave portion formed where the another lateral end of the connecting wire and the first electrode of the storage capacitor overlap each other.
  • each of the pixels further comprises a pixel electrode formed over the connecting wire and at least partially overlapping the connecting wire.
  • the above display device further comprises a first insulating layer at least partially covering the connecting wire and a second insulating layer formed between the first insulating layer and the pixel electrode.
  • the driving TFT includes a gate electrode, wherein the selected switching TFT includes an initialization TFT configured to supply an initialization voltage to the gate electrode.
  • the bottom portions of the connecting wire and the second wire are formed in the same layer.
  • Another aspect is a method of manufacturing a display device comprising a plurality of switching thin film transistors (TFTs), a driving TFT and a plurality of pixels, the method comprising forming a connecting wire configured to electrically connect a selected one of the switching TFTs to the driving TFT, wherein the connecting wire has top and bottom portions opposing each other.
  • the method also comprises forming a first wire extending in a first direction and forming a second wire extending in a second direction crossing the first direction, wherein the second wire is formed adjacent to the connecting wire and configured to transmit a signal to each of the pixels, wherein the second wire has top and bottom portions opposing each other, and wherein at least the top portions of the connecting wire and the second wire are formed on different layers.
  • the above method further comprises forming a storage capacitor including a first electrode and a second electrode, and wherein the forming of the connecting wire comprises forming the top portion of the connecting wire on the same layer as at least a portion of one of the first and second electrodes.
  • the second electrode of the storage capacitor has a concave portion formed where one lateral end of the connecting wire and the first electrode of the storage capacitor overlap each other.
  • the top portion of the connecting wire is formed below the top portion of the second wire.
  • the second wire comprises a data line.
  • the above method further comprises forming a pixel electrode formed over the second wire and at least partially overlapping the connecting wire.
  • the above method further comprises forming a first insulating layer between the connecting wire and the second wire and forming a second insulating layer over the first insulating layer and below the pixel electrode.
  • a display device comprising a scan driver configured to provide a scan signal through a scan line extending in a first direction.
  • the display device also comprises a data driver configured to provide a data signal through a data line extending in a second direction crossing the first direction, wherein the data line has top and bottom portions opposing each other.
  • the display device further comprises a pixel electrically connected to the scan line and the data line, wherein each pixel comprises a switching thin-film transistor (TFT) configured to receive the scan signal and the data signal so as to generate a driving signal.
  • TFT switching thin-film transistor
  • the pixel also comprises a driving TFT configured to receive the driving signal so as to generate a driving current.
  • the pixel further comprises a connecting wire electrically connecting the driving TFT to the switching TFT, wherein the connecting wire has top and bottom portions opposing each other, and wherein top portions of the connecting wire and the data lines are formed on different layers.
  • the height of the data line is greater than that of the connecting wire.
  • FIG. 1 is a block diagram schematically illustrating an OLED display according to an exemplary embodiment.
  • FIG. 2 is an equivalent circuit diagram of one pixel of an OLED display, according to an exemplary embodiment.
  • FIG. 3 is a plan view schematically illustrating one pixel included in an OLED display, according to an exemplary embodiment.
  • FIG. 4 shows cross-sectional views of the pixel of FIG. 3 taken along lines A-A′ and B-B′.
  • FIGS. 5 through 12 are views for describing a method of forming one pixel of an OLED display, according to an exemplary embodiment.
  • a specific process order can be performed differently from the described order.
  • two consecutively described processes can be performed substantially at the same time or performed in an order opposite to the described order.
  • the term “substantially” includes the meanings of completely, almost completely or to any significant degree under some applications and in accordance with those skilled in the art.
  • “formed on” can also mean “formed over.”
  • the term “connected” can include an electrical connection.
  • FIG. 1 is a block diagram schematically illustrating an OLED display according to an exemplary embodiment.
  • the OLED display includes a display unit 10 including a plurality of pixels 1 , a scan driver 20 , a data driver 30 , and a controller 40 .
  • the display unit 10 includes the pixels 1 that are arranged approximately in a matrix shape by being located at intersections of a plurality of first through nth scanning lines SL 1 through SLn, a plurality of first through mth data lines DL 1 through DLm, and a plurality of first through nth emission control lines EL 1 through ELn.
  • the first through nth scanning lines SL 1 through SLn and the first through nth emission control lines EL 1 through ELn extend in a first direction, e.g., a row direction.
  • the first through mth data lines DL 1 through DLm and a plurality of driving voltage lines PL extend in a second direction, e.g., a column direction.
  • a value of n in the first through nth scanning lines SL 1 through SLn and a value of n in the first through nth emission control lines EL 1 through ELn can be different from each other.
  • Each pixel 1 is connected to two of the first through nth scanning lines SL 1 through SLn transmitted to the display unit 10 .
  • a scanning line corresponding to a current pixel line and a scanning line corresponding to a previous pixel line are connected to each pixel 1 , but an embodiment is not limited thereto.
  • Each pixel 1 is connected to one of the first through mth data lines DL 1 through DLm, and one of the first through nth emission control lines EL 1 through ELn. Also, each pixel 1 is connected to one of a plurality of initialization voltage line VL that supply an initialization voltage, and one of the driving voltage lines PL that supply a first power voltage ELVDD. Although not illustrated, the two adjacent pixels 1 from among the pixels 1 can share one initialization voltage line VL, according to an exemplary embodiment.
  • the scan driver 20 generates and transmits two corresponding scanning signals to each pixel 1 through the first through nth scanning lines SL 1 through SLn. For example, the scan driver 20 transmits a first scanning signal Sn through a scanning line corresponding to a row line of each pixel 1 and a second scanning signal Sn ⁇ 1 through a scanning line corresponding to a previous row line of the row line. For example, the scan driver 20 transmits the first scanning signal Sn to the pixel 1 formed on the mth column line and the nth row line through the nth scanning line SLn, and the second scanning signal Sn ⁇ 1 through the n ⁇ 1th scanning line SLn ⁇ 1. Also, the scan driver 20 can generate and transmit an emission control signal to each pixel 1 through the first through nth emission control lines EL 1 through ELn.
  • a scanning signal and an emission control signal are generated by the same scan driver 20 , but alternatively, the OLED display can further include an emission control driver (not shown), and an emission control signal can be generated by the emission control driver.
  • the data driver 30 transmits a data signal to each pixel 1 through the first through mth data lines DL 1 through DLm.
  • the controller 40 changes a plurality of image signals R, G, and B received from an external source to a plurality of image data signals DR, DG, and DB, and transmits the image data signals DR, DG, and DB to the data driver 30 . Also, the controller 40 generates a control signal for controlling driving of the scan driver 20 and the data driver 30 upon receiving a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK. The controller 40 transmits the control signal to each of the scan driver 20 and the data driver 30 . For example, the controller 40 generates and transmits a scan driving control signal SCS and a emission driving control signal ECS to the scan driver 20 The controller 40 can also generate and transmit a data driving control signal DCS to the data driver 30 .
  • Each pixel 1 receives the first power voltage ELVDD and a second power voltage ELVSS from an external source.
  • the first power voltage ELVDD can be a certain high level voltage and the second power voltage ELVSS can be a ground voltage or a voltage less than the first power voltage ELVDD.
  • Each of the pixels 1 emits light having certain luminance by a driving current Id supplied to an OLED of FIG. 2 according to data signals received through the first through mth data lines DL 1 through DLm.
  • FIG. 2 is an equivalent circuit diagram of one pixel 1 of an OLED display, according to an exemplary embodiment.
  • the pixel 1 includes a pixel circuit 2 that includes a plurality of thin-film transistors (TFTs) and a storage capacitor Cst.
  • the pixel 1 can include the OLED that receives a driving voltage through the pixel circuit 2 to thereby emit light.
  • the TFTs include a driving TFT T 1 and a plurality of switching TFTs.
  • the switching TFTs include a data transmission TFT T 2 , a compensation TFT T 3 , a first initialization TFT T 4 , a first emission control TFT T 5 , a second emission control TFT T 6 , and a second initialization TFT T 7 .
  • the pixel 1 includes a first scanning line 14 through which the first scanning signal Sn is transmitted to the data transmission TFT T 2 and the compensation TFT T 3 .
  • the pixel 1 also includes a second scanning line 24 through which the second scanning signal Sn ⁇ 1 is transmitted to the first initialization TFT T 4 and the second initialization TFT T 7 .
  • the pixel 1 also includes an emission control line 15 through which an emission control signal En is transmitted to the first emission control TFT T 5 and the second emission control TFT T 6
  • the pixel 1 further includes a data line 16 through which a data signal Dm is transmitted, a driving voltage line 26 through which the first power voltage ELVDD is transmitted, and an initialization voltage line 22 through which an initialization voltage VINT that initialize the driving TFT T 1 is transmitted.
  • a driving gate electrode G 1 of the driving TFT T 1 is connected to a first electrode 51 of the storage capacitor Cst.
  • a driving source electrode S 1 of the driving TFT T 1 is connected to the first emission control TFT T 5 to be electrically connected to the driving voltage line 26 .
  • a driving drain electrode D 1 of the driving TFT T 1 is connected to the second emission control TFT T 6 to be electrically connected to a pixel electrode (anode electrode) of the OLED.
  • the driving TFT T 1 receives the data signal Dm according to a switching operation of the data transmission TFT T 2 to supply the driving current Id to the OLED.
  • a data transmission gate electrode G 2 of the data transmission TFT T 2 is connected to the first scanning line 14 .
  • a data transmission source electrode S 2 of the data transmission TFT T 2 is connected to the data line 16 .
  • a data transmission drain electrode D 2 of the data transmission TFT T 2 is connected to the driving source electrode S 1 of the driving TFT T 1 and is electrically connected to the first emission control TFT T 5 to be connected to the driving voltage line 26 .
  • the data transmission TFT T 2 is turned on according to the first scanning signal Sn received through the first scanning line 14 so as to perform a switching operation whereby the data signal Dm transmitted to the data line 16 is transmitted to the driving source electrode S 1 of the driving TFT T 1 .
  • a compensation gate electrode G 3 of the compensation TFT T 3 is connected to the first scanning line 14 .
  • a compensation source electrode S 3 of the compensation TFT T 3 is connected to the driving drain electrode D 1 of the driving TFT T 1 and is electrically connected to the second emission control TFT T 6 to be connected to the anode electrode of the OLED.
  • a compensation drain electrode D 3 of the compensation TFT T 3 is also connected to the first electrode 51 of the storage capacitor Cst, a first initialization source electrode S 4 of the first initialization TFT T 4 , and the driving gate electrode G 1 of the driving TFT T 1 .
  • the compensation TFT T 3 is turned on according to the first scanning signal Sn to connect the driving gate electrode G 1 to the driving drain electrode D 1 of the driving TFT T 1 , thereby diode-connecting the driving TFT T 1 .
  • a first initialization gate electrode G 4 of the first initialization TFT T 4 is connected to the second scanning line 24 .
  • a first initialization drain electrode D 4 of the first initialization TFT T 4 is connected to the initialization voltage line 22 .
  • the first initialization source electrode S 4 is also connected to the first electrode 51 , the compensation drain electrode D 3 , and the driving gate electrode G 1 .
  • the first initialization TFT T 4 is turned on according to the second scanning signal Sn ⁇ 1 to transmit an initialization voltage VINT to the driving gate electrode G 1 , thereby performing an initialization operation of initializing a voltage of the driving gate electrode G 1 .
  • a first emission control gate electrode G 5 of the first emission control TFT T 5 is connected to the emission control line 15 .
  • a first emission source electrode S 5 of the first emission control TFT T 5 is connected to the driving voltage line 26 .
  • a first emission drain electrode D 5 of the first emission control TFT T 5 is connected to the driving source electrode S 1 and the data transmission drain electrode D 2 .
  • a second emission control gate electrode G 6 of the second emission control TFT T 6 is connected to the emission control line 15 .
  • a second emission control source electrode S 6 of the second emission control TFT T 6 is connected to the driving drain electrode D 1 and the compensation source electrode S 3 .
  • a second emission control drain electrode D 6 of the second emission control TFT T 6 is electrically connected to the anode electrode of the OLED.
  • the first emission control TFT T 5 and the second emission control TFT T 6 are substantially simultaneously turned on according to the emission control signal En received through the emission control line 15 so that the first power voltage ELVDD is transmitted to the OLED, and the driving current Id flows through the OLED.
  • a second initialization gate electrode G 7 of the second initialization TFT T 7 is connected to the second scanning line 24 .
  • a second initialization source electrode S 7 of the second initialization TFT T 7 is connected to the anode electrode of the OLED.
  • a second initialization drain electrode D 7 of the second initialization TFT T 7 is connected to the initialization voltage line 22 .
  • the second initialization TFT T 7 is turned on according to the second scanning signal Sn ⁇ 1 received through the second scanning line 24 , thereby initializing the anode electrode of the OLED.
  • the first initialization TFT T 4 and the second initialization TFT T 7 are connected to the second scanning line 24 , but alternatively, the first initialization TFT T 4 can be connected to the second scanning line 24 to be driven according to the second scanning signal Sn ⁇ 1, and the second initialization TFT T 7 can be connected to a separate third scanning line to be driven according to a third scanning signal Sn+1.
  • a second electrode 52 of the storage capacitor Cst is connected to the driving voltage line 26 .
  • the first electrode 51 is connected to the driving gate electrode G 1 , the compensation drain electrode D 3 , and the first initialization source electrode S 4 .
  • a cathode electrode of the OLED is connected to the second power voltage ELVSS.
  • the OLED receives the driving current Id from the driving TFT T 1 to emit light, thereby displaying an image.
  • FIG. 3 is a plan view schematically illustrating the pixel 1 included in an OLED display, according to an exemplary embodiment.
  • the pixel 1 includes a plurality of wires, the driving TFT T 1 , the switching TFTs, the capacitor Cst, and a pixel electrode 210 .
  • the wires can include the first and second scanning lines 14 and 24 and the initialization voltage line 22 , which extend in a first direction.
  • the wires can also include data line 16 and the driving voltage line 26 both extending in a second direction to cross the first and second scanning lines 14 and 24 .
  • the first and second scanning lines 14 and 24 can be formed on the same layer as gate electrodes of the TFTs, and the initialization voltage line 22 can be formed on the same layer as the pixel electrode 210 .
  • the driving TFT T 1 includes a driving semiconductor layer A 1 , the driving gate electrode G 1 , the driving source electrode S 1 , and the driving drain electrode D 1 .
  • the driving source electrode S 1 corresponds to an impurity-doped driving source region in the driving semiconductor layer A 1
  • the driving drain electrode D 1 corresponds to an impurity-doped driving drain region in the driving semiconductor layer A 1 .
  • a region between the impurity-doped driving source region and the driving drain electrode D 1 corresponds to a driving channel region.
  • the driving gate electrode G 1 is connected to the storage capacitor Cst, the compensation drain electrode D 3 , and the first initialization source electrode S 4 .
  • the driving gate electrode G 1 also controls operations of the first electrode 51 .
  • the data transmission TFT T 2 includes a data transmission semiconductor layer A 2 , the data transmission gate electrode G 2 , the data transmission source electrode S 2 , and the data transmission drain electrode D 2 .
  • the data transmission source electrode S 2 corresponds to an impurity-doped switching source region in the data transmission semiconductor layer A 2
  • the data transmission drain electrode D 2 corresponds to an impurity-doped switching drain region in the data transmission semiconductor layer A 2 .
  • the data transmission source electrode S 2 is connected to the data line 16 through a third contact hole Cnt 3 .
  • the data transmission drain electrode D 2 is connected to the driving TFT T 1 and the first emission control TFT T 5 .
  • the data transmission gate electrode G 2 is formed as a part of the first scanning line 14 .
  • the compensation TFT T 3 includes a compensation semiconductor layer A 3 , the compensation gate electrode G 3 , the compensation source electrode S 3 , and the compensation drain electrode D 3 .
  • the compensation source electrode S 3 corresponds to an impurity-doped compensation source region in the compensation semiconductor layer A 3
  • the compensation drain electrode D 3 corresponds to an impurity-doped compensation drain region in the compensation semiconductor layer A 3 .
  • the compensation gate electrode G 3 prevents a leakage current by forming a dual-gate electrode by using a part of the first scanning line 14 and a part of wire protruding and extending from the first scanning line 14 .
  • the first initialization TFT T 4 includes a first initialization semiconductor layer A 4 , the first initialization gate electrode G 4 , the first initialization source electrode S 4 , and the first initialization drain electrode D 4 .
  • the first initialization source electrode S 4 corresponds to an impurity-doped first initialization source region in the first initialization semiconductor layer A 4
  • the first initialization drain electrode D 4 corresponds to an impurity-doped first initialization drain region in the first initialization semiconductor layer A 4 .
  • the first initialization drain electrode D 4 can be connected to the second initialization TFT T 7
  • the first initialization source electrode S 4 can be connected to the driving gate electrode G 1 through a connecting wire 36 .
  • the first initialization gate electrode G 4 is formed as a part of the second scanning line 24 .
  • the connecting wire 36 can extend in the second direction and can be formed adjacent to the data line 16 .
  • the connecting wire 36 can electrically connect the first initialization TFT T 4 to the driving TFT T 1 through first and second contact holes Cnt 1 and Cnt 2 .
  • the first emission control TFT T 5 includes a first emission control semiconductor layer A 5 , the first emission control gate electrode G 5 , the first emission control source electrode S 5 , and the second emission control drain electrode D 5 .
  • the first emission control source electrode S 5 corresponds to an impurity-doped first emission control source region in the first emission control semiconductor layer A 5 .
  • the second emission control drain electrode D 5 corresponds to an impurity-doped first emission control drain region in the first emission control semiconductor layer A 5 .
  • the first emission control source electrode S 5 can be connected to the driving voltage line 26 through a fourth contact hole Cnt 4 .
  • the first emission control gate electrode G 5 is formed as a part of the emission control line 15 .
  • the second emission control TFT T 6 includes a second emission control semiconductor layer A 6 , the second emission control gate electrode G 6 , the second emission control source electrode S 6 , and the second emission control drain electrode D 6 .
  • the second emission control source electrode S 6 corresponds to an impurity-doped second emission control source region in the second emission control semiconductor layer A 6
  • the second emission control drain electrode D 6 corresponds to an impurity-doped second emission control drain region in the second emission control semiconductor layer A 6 .
  • the second emission control drain electrode D 6 is connected to a first cover metal CM 1 through a fifth contact hole Cnt 5
  • the first cover metal CM 1 is connected to the pixel electrode 210 of the OLED through a first via hole via 1 .
  • the second emission control gate electrode G 6 is formed as a part of the emission control line 15 .
  • the second initialization TFT T 7 includes a second initialization semiconductor layer A 7 , the second initialization gate electrode G 7 , the second initialization source electrode S 7 , and the second initialization drain electrode D 7 .
  • the second initialization source electrode S 7 corresponds to an impurity-doped second initialization source region in the second initialization semiconductor layer A 7
  • the second initialization drain electrode D 7 corresponds to an impurity-doped second initialization drain region in the second initialization semiconductor layer A 7 .
  • the second initialization drain electrode D 7 is connected to a second cover metal CM 2 through a sixth contact hole Cnt 6 .
  • the second cover metal CM 2 can be connected to the initialization voltage line 22 through a second via hole via 2 .
  • the second initialization source electrode S 7 is connected to the pixel electrode 210 of the OLED via the first cover metal CM 1 .
  • the first electrode 51 of the storage capacitor Cst is directly connected to the driving gate electrode G 1 , and is formed to at least partially overlap the driving semiconductor layer A 1 .
  • the first electrode 51 is connected to the first initialization TFT T 4 through the connecting wire 36 contacting through the second contact hole Cnt 2 .
  • the driving gate electrode G 1 can also control operations of the first electrode 51 of the storage capacitor Cst.
  • the second contact hole Cnt 2 is formed on the driving gate electrode G 1 to expose a part of the driving gate electrode G 1 (or the first electrode 51 of the storage capacitor Cst).
  • the second electrode 52 of the storage capacitor Cst is formed to at least partially overlap the first electrode 51 .
  • the second electrode 52 and the connecting wire 36 are formed on the same layer.
  • One end of the connecting wire 36 is connected to the first initialization TFT T 4 through the first contact hole Cnt 1 as described above, and another end of the connecting wire 36 is electrically connected to the first electrode 51 (or the driving gate electrode G 1 ) through the second contact hole Cnt 2 . Accordingly, the other end of the connecting wire 36 partially overlaps the first electrode 51 , and the second electrode 62 includes a concave portion g formed at a location corresponding to a region where the other end of the connecting wire 36 and the first electrode 51 overlap each other.
  • the pixel electrode 210 is formed to overlap at least a part of the driving TFT T 1 , the storage capacitor Cst, and the connecting wire 36 , and is connected to the second emission control TFT T 6 through the first via hole via 1 .
  • FIG. 4 shows cross-sectional views of the pixel of FIG. 3 taken along lines A-A′ and B-B′ of FIG. 3 .
  • a buffer layer 101 is formed on a substrate 100 , and semiconductor layers are formed on the buffer layer 101 .
  • the first initialization source electrode S 4 and the data transmission source electrode S 2 which are partial regions of an impurity-doped semiconductor layer, are shown in the cross-sectional view taken along the line A-A′, and the driving semiconductor layer A 1 is shown in the cross-sectional view taken along the line B-B′.
  • a first gate insulating layer 102 , a first conductive layer including the first electrode 51 , a second gate insulating layer 103 , a second conductive layer including the connecting wire 36 and the second electrode 52 of the storage capacitor Cst, an interlayer insulating layer 104 , a third conductive layer including the data line 16 and the driving voltage line 26 of FIG. 3 , and a planarization film 105 are sequentially formed on the semiconductor layers.
  • the first gate insulating layer 102 , the second gate insulating layer 103 , the interlayer insulating layer 104 , and the planarization film 105 all have insulating properties, and include an inorganic material and/or an organic material.
  • the connecting wire 36 and the data line 16 are formed adjacent to each other, but on different layers. As described above with reference to FIG. 3 , the connecting wire 36 , the data line 16 , and the driving voltage line 26 all extend in the second direction. The data line 16 and the connecting wire 36 are formed adjacent to each other.
  • connecting wire 36 and the data line 16 are formed on the same layer, parasitic capacitance is formed in a horizontal direction, and crosstalk can be generated.
  • the connecting wire 36 and the data line 16 are formed adjacent to each other but on the different layers, parasitic capacitance is prevented or reduced, thereby preventing or reducing crosstalk.
  • the connecting wire 36 is not formed on the same layer as the data line 16 but below the data line 16 , a plurality of insulating layers, such as the interlayer insulating layer 104 and the planarization film 105 , can be formed between the connecting wire 36 and the pixel electrode 210 . If the connecting wire 36 is formed on the same layer as the data line 16 , a distance between the connecting wire 36 and the pixel electrode 210 is relatively short, and thus potential deviation is generated in the driving gate electrode G 1 by parasitic capacitance between the connecting wire 36 and the pixel electrode 210 , thereby generating a spot or color variation.
  • the connecting wire 36 is formed on a different layer from the data line 16 , for example, below the data line 16 , parasitic capacitance is prevented or reduced, thereby preventing or reducing a spot or color variation.
  • FIGS. 5 through 12 are views for describing a method of forming one pixel 1 of an OLED display, according to an exemplary embodiment.
  • the semiconductor layers i.e., the driving semiconductor layer A 1 , the data transmission semiconductor layer A 2 , the compensation semiconductor layer A 3 , the first initialization semiconductor layer A 4 , the first emission control semiconductor layer A 5 , the second emission control semiconductor layer A 6 , and the second initialization semiconductor layer A 7 , are formed on the substrate 100 where the buffer layer 101 is formed.
  • the semiconductor layers can be an amorphous silicon layer, a polycrystalline silicon layer, or an oxide semiconductor layer, such as (In2O3)a(Ga2O3)b(ZnO)c layer (G-I—Z—O layer), wherein a, b, and c are real numbers satisfying a ⁇ 0, b ⁇ 0, and c ⁇ 0.
  • the driving semiconductor layer A 1 having the driving channel region is curved or bent such that the driving channel region is elongated in a narrow space. Since the driving channel region of the driving TFT T 1 can be elongated, a driving range of a gate voltage applied to the driving gate electrode G 1 can be increased. Thus, by changing a level of a driving gate voltage, grayscale of light emitted from the OLED can be substantially precisely controlled. Accordingly, resolution and display quality of the OLED display can be improved.
  • the driving channel region of the driving TFT T 1 can be curved or bent in a variety of shapes.
  • the first gate insulating layer 102 is formed on the semiconductor layers.
  • the first gate insulating layer 102 at least partially covers the semiconductor layers and is formed on substantially the entirety of the surface of the substrate 100 .
  • the first gate insulating layer 102 can be formed of an organic and/or inorganic insulating material.
  • the first gate insulating layer 102 is formed of silicon nitride (SiNx), silicon oxide (SiO2), hafnium oxide (HfO), or aluminum oxide (AlO).
  • the first conductive layer including gate electrodes i.e., the driving gate electrode G 1 , the data transmission gate electrode G 2 , the compensation gate electrode G 3 , the first initialization gate electrode G 4 , the first emission control gate electrode G 5 , the second emission control gate electrode G 6 , and the second initialization gate electrode G 7 ), the first and second scanning lines 14 and 24 , and the emission control line 15 are formed on the first gate insulating layer 102 .
  • the gate electrodes, the first and second scanning lines 14 and 24 , and the emission control lines 15 are formed on the same layer and of the same material as each other.
  • the first scanning line 14 operates as the compensation gate electrode G 3 and the data transmission gate electrode G 2 respectively of the compensation TFT T 3 and the data transmission TFT T 2 .
  • the second scanning line 24 operates as the first initialization gate electrode G 4 and the second initialization gate electrode G 7 respectively of the first initialization TFT T 4 and the second initialization TFT T 7 .
  • the emission control line 15 operates as the first emission control gate electrode G 5 and the second emission control gate electrode G 6 respectively of the first emission control TFT T 5 and the second emission control TFT T 6 .
  • the driving gate electrode G 1 also operates as the first electrode 51 of the storage capacitor Cst.
  • the driving gate electrode G 1 is a floating electrode, and at least partially overlaps a channel region of the driving semiconductor layer A 1 of the driving TFT T 1 .
  • the source electrodes i.e., the driving source electrode S 1 , the data transmission source electrode S 2 , the compensation source electrode S 3 , the first initialization source electrode S 4 , the first emission source electrode S 5 , the second emission control source electrode S 6 , and the second initialization source electrode S 7
  • the drain electrodes i.e., the driving drain electrode D 1 , the data transmission drain electrode D 2 , the compensation drain electrode D 3 , the first initialization drain electrode D 4 , the first emission drain electrode D 5 , the second emission control drain electrode D 6 , and the second initialization drain electrode D 7
  • the impurities can differ according to a type of a TFT, and can be an N-type or a P-type.
  • the second gate insulating layer 103 is formed on the gate electrodes throughout the substrate 100 .
  • the second gate insulating layer 103 can be formed of an organic and/or inorganic insulating material. According to an exemplary embodiment, the second gate insulating layer 103 is formed of SiNx, SiO2, HfO, or AlO.
  • the first and second contact holes Cnt 1 and Cnt 2 penetrating through the second gate insulating layer 103 are formed.
  • the first contact hole Cnt 1 can expose the first initialization source electrode S 4
  • the second contact hole Cnt 2 can expose the driving gate electrode G 1 .
  • the second conductive layer including the connecting wire 36 and the second electrode 52 of the storage capacitor Cst is formed.
  • the connecting wire 36 and the second electrode 52 are formed on the same layer and of the same material.
  • the one end of the connecting wire 36 contacts the first initialization source electrode S 4 of the first initialization TFT T 4 through the first contact hole Cnt 1 , and the other end of the connecting wire 36 contacts the driving gate electrode G 1 (or the first electrode 51 of the storage capacitor Cst) through the second contact hole Cnt 2 .
  • the second electrode 52 overlaps the first electrode 51 .
  • the capacity of the storage capacitor Cst is determined by the second gate insulating layer 103 formed between the first electrode 51 and the second electrode 52 .
  • the second electrode 52 includes the concave portion g at the location corresponding to the region where the other end of the connecting wire 36 and the first electrode 51 overlap each other.
  • the interlayer insulating layer 104 is formed to cover the connecting wire 36 and the second electrode 52 .
  • the interlayer insulating layer 104 can be formed of an organic and/or inorganic insulating material.
  • the third through seventh contact holes Cnt 3 through Cnt 7 that penetrate through the interlayer insulating layer 104 are formed.
  • the third contact hole Cnt 3 exposes the data transmission source electrode S 2
  • the fourth contact hole Cnt 4 exposes the first emission control source electrode S 5
  • the fifth contact hole Cnt 5 exposes the second emission control drain electrode D 6
  • the sixth contact hole Cnt 6 exposes the second initialization drain electrode D 7 .
  • the seventh contact hole Cnt 7 exposes the second electrode 52 of the storage capacitor Cst.
  • the third conductive layer including the data line 16 , the driving voltage line 26 , and the first and second cover metals CM 1 and CM 2 is formed.
  • the data line 16 , the driving voltage line 26 , and the first and second cover metals CM 1 and CM 2 are formed on the same layer and of the same material.
  • the data line 16 , the driving voltage line 26 , and the first and second scanning lines 14 and 24 extend in the second direction to cross the first and second scanning lines 14 and 24 , and the data line 16 is formed adjacent to the connecting wire 36 .
  • the data line 16 is formed per pixel 1 .
  • the driving voltage line 26 is connected to the second electrode 52 of the storage capacitor Cst through the seventh contact hole Cnt 7 to form a mesh structure, and maintains electric potential of the second electrode 52 of the storage capacitor at a uniform level.
  • the driving voltage line 26 can be shared with a neighboring pixel. For example, one driving voltage line 26 transmits a driving voltage to adjacent pixels.
  • the data line 16 is connected to the data transmission source electrode S 2 through the third contact hole Cnt 3
  • the driving voltage line 26 is connected to the first emission control source electrode S 5 through the fourth contact hole Cnt 4
  • the first cover metal CM 1 is connected to the second emission control drain electrode D 6 through the fifth contact hole Cnt 5
  • the second cover metal CM 2 is connected to the second initialization drain electrode D 7 through the sixth contact hole Cnt 6 .
  • planarization film 105 covering the data line 16 , the driving voltage line 26 , and the first and second cover metals CM 1 and CM 2 are formed.
  • the planarization film 105 can be a single layer film or a multilayer film formed of an inorganic material, an organic material, or an organic/inorganic complex.
  • the first and second via holes via 1 and via 2 penetrating through the planarization film 105 are formed.
  • the first via hole via 1 is formed at a location corresponding to the fifth contact hole Cnt 5 to expose the first cover metal CM 1 .
  • the second via hole via 2 is formed at a location corresponding to the sixth contact hole Cnt 6 to expose the second cover metal CM 2 .
  • the pixel electrode 210 and the initialization voltage line 22 are formed.
  • the pixel electrode 210 and the initialization voltage line 22 are formed on the same layer and of the same material.
  • the pixel electrode 210 contacts the first cover metal CM 1 through the first via hole via 1 , and is connected to the second emission control TFT T 6 by using the first cover metal CM 1 as a medium.
  • the pixel electrode 210 is formed to overlap at least parts of the driving TFT T 1 , the storage capacitor Cst, and the connecting wire 36 .
  • the initialization voltage line 22 is connected to the second initialization TFT T 7 through the second via hole via 2 .
  • a pixel-defining film having an opening that exposes a top portion of the pixel electrode 210 is formed on the planarization film 105 , and an organic film including an emission layer is formed on the pixel electrode 210 that is exposed through the opening of the pixel-defining film. Also, a counter electrode covering the organic film and an entire surface of the substrate 100 is formed.
  • the connecting wire 36 is formed on a different layer from the data line 16 , for example, below the data line 16 . Accordingly, parasitic capacitance between the connecting wire 36 and the data line 16 can be reduced, and parasitic capacitance between the connecting wire 36 and the pixel electrode 210 can be reduced. Consequently, crosstalk, spots, or color variation can be prevented or reduced, and thus a high quality image can be provided.
  • the storage capacitor Cst overlaps the driving TFT T 1 , and thus sufficient capacity can be obtained while high resolution is realized.
  • an OLED display can have low parasitic capacitance, thereby providing a high quality image.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
US14/644,049 2014-10-16 2015-03-10 Organic light-emitting diode display and method of manufacturing the same Active 2035-04-23 US9577019B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2014-0140176 2014-10-16
KR1020140140176A KR102313855B1 (ko) 2014-10-16 2014-10-16 유기 발광 표시 장치 및 그 제조 방법

Publications (2)

Publication Number Publication Date
US20160111484A1 US20160111484A1 (en) 2016-04-21
US9577019B2 true US9577019B2 (en) 2017-02-21

Family

ID=55749689

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/644,049 Active 2035-04-23 US9577019B2 (en) 2014-10-16 2015-03-10 Organic light-emitting diode display and method of manufacturing the same

Country Status (2)

Country Link
US (1) US9577019B2 (ko)
KR (1) KR102313855B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216585A (zh) * 2018-09-17 2019-01-15 京东方科技集团股份有限公司 显示基板和显示装置

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102471113B1 (ko) * 2015-11-18 2022-11-28 삼성디스플레이 주식회사 표시장치
KR102600620B1 (ko) * 2016-05-16 2023-11-09 삼성디스플레이 주식회사 디스플레이 장치 및 이의 제조 방법
KR102593534B1 (ko) * 2018-10-10 2023-10-25 삼성디스플레이 주식회사 디스플레이 장치
CN109830208B (zh) * 2019-03-28 2020-08-25 厦门天马微电子有限公司 像素电路及其驱动方法、显示面板和显示装置
KR20200136520A (ko) * 2019-05-27 2020-12-08 삼성디스플레이 주식회사 표시 장치
CN111063301B (zh) * 2020-01-09 2024-04-12 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板及显示装置
CN111696484B (zh) * 2020-07-10 2021-10-08 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板及显示装置
KR20220060622A (ko) * 2020-11-04 2022-05-12 삼성디스플레이 주식회사 표시 장치
CN112634833A (zh) * 2021-01-07 2021-04-09 武汉华星光电半导体显示技术有限公司 像素电路及其驱动方法、显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080047948A (ko) 2006-11-27 2008-05-30 엘지디스플레이 주식회사 유기 전계발광 표시 장치 및 그 제조방법
US20100295758A1 (en) 2007-12-10 2010-11-25 Global Oled Technology, Llc Pixel circuit
US20110164019A1 (en) 2010-01-07 2011-07-07 Samsung Mobile Display Co., Ltd. Organic light emitting diode display
US8232935B2 (en) * 2007-06-13 2012-07-31 Sony Corporation Display apparatus, driving method for display apparatus and electronic apparatus
US20140034923A1 (en) 2012-08-02 2014-02-06 Samsung Display Co., Ltd Organic light emitting diode display
US20140084293A1 (en) 2012-09-21 2014-03-27 Kookmin University Industry Academy Cooperation Foundation Thin film transistor array panel and method of manufacturing the same
US9165993B2 (en) * 2013-04-04 2015-10-20 Samsung Display Co., Ltd. Capacitor device, organic light emitting display apparatus including the capacitor device, and method of manufacturing the organic light emitting display apparatus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101973164B1 (ko) * 2012-10-08 2019-08-27 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 이를 포함하는 표시 장치
KR101980757B1 (ko) * 2012-12-13 2019-05-21 엘지디스플레이 주식회사 유기발광 표시장치

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080047948A (ko) 2006-11-27 2008-05-30 엘지디스플레이 주식회사 유기 전계발광 표시 장치 및 그 제조방법
US8232935B2 (en) * 2007-06-13 2012-07-31 Sony Corporation Display apparatus, driving method for display apparatus and electronic apparatus
US20100295758A1 (en) 2007-12-10 2010-11-25 Global Oled Technology, Llc Pixel circuit
US20110164019A1 (en) 2010-01-07 2011-07-07 Samsung Mobile Display Co., Ltd. Organic light emitting diode display
KR20110080905A (ko) 2010-01-07 2011-07-13 삼성모바일디스플레이주식회사 유기 발광 표시 장치
US20140034923A1 (en) 2012-08-02 2014-02-06 Samsung Display Co., Ltd Organic light emitting diode display
KR20140018623A (ko) 2012-08-02 2014-02-13 삼성디스플레이 주식회사 유기 발광 표시 장치
US20140084293A1 (en) 2012-09-21 2014-03-27 Kookmin University Industry Academy Cooperation Foundation Thin film transistor array panel and method of manufacturing the same
US9165993B2 (en) * 2013-04-04 2015-10-20 Samsung Display Co., Ltd. Capacitor device, organic light emitting display apparatus including the capacitor device, and method of manufacturing the organic light emitting display apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216585A (zh) * 2018-09-17 2019-01-15 京东方科技集团股份有限公司 显示基板和显示装置

Also Published As

Publication number Publication date
KR102313855B1 (ko) 2021-10-19
US20160111484A1 (en) 2016-04-21
KR20160045232A (ko) 2016-04-27

Similar Documents

Publication Publication Date Title
US9577019B2 (en) Organic light-emitting diode display and method of manufacturing the same
US11990092B2 (en) Organic light-emitting display apparatus
USRE49201E1 (en) Organic light-emitting display device and manufacturing method of the same
US10177209B2 (en) Organic light-emitting diode (OLED) display
US9231000B2 (en) Thin film transistor array substrate and organic light-emitting display apparatus including the same
US7742025B2 (en) Display apparatus and driving method thereof
US11482173B2 (en) Display device
US9847055B2 (en) Organic light emitting display apparatus
US10181480B2 (en) Thin film transistor substrate and display apparatus
US20160064411A1 (en) Thin film transistor substrate and display apparatus including the same
US10008517B2 (en) Display device having reduced parasitic capacitance and cross-talk and method of manufacturing the same
TWI690104B (zh) 薄膜電晶體陣列基板與有機發光顯示裝置
US9799718B2 (en) Display apparatus
US20160133684A1 (en) Display device and method of manufacturing the same
US20150372070A1 (en) Organic light-emitting diode (oled) display
US9293482B2 (en) Thin-film transistor array substrate, display apparatus including same, and method of manufacturing thin-film transistor array substrate
KR20220076173A (ko) 전계 발광 표시 장치 및 이의 제조 방법

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG DISPLAY CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AN, JINSUNG;YOON, JUWON;LEE, JEONGSOO;AND OTHERS;REEL/FRAME:035276/0775

Effective date: 20150304

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4