US9525411B2 - Power supply circuits for gate drivers - Google Patents

Power supply circuits for gate drivers Download PDF

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Publication number
US9525411B2
US9525411B2 US14/540,762 US201414540762A US9525411B2 US 9525411 B2 US9525411 B2 US 9525411B2 US 201414540762 A US201414540762 A US 201414540762A US 9525411 B2 US9525411 B2 US 9525411B2
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power supply
circuit
supply circuit
voltage
power
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US20160142049A1 (en
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Kenneth G. Richardson
Ryan SCHNELL
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Analog Devices Inc
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Analog Devices Inc
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Assigned to ANALOG DEVICES, INC. reassignment ANALOG DEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RICHARDSON, KENNETH G., Schnell, Ryan
Priority to DE102015119492.9A priority patent/DE102015119492B4/de
Priority to CN201510770261.6A priority patent/CN105610303B/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
    • H02M2001/0006—

Definitions

  • Load driving circuits are used to drive loads in a variety of applications, such as within polyphase systems to drive electric motors. Many such load driving applications necessitate galvanic or other forms of isolation between the load system and another system delivering power, control and data inputs. Isolation is typically necessitated for a variety of reasons, including safety and reliability concerns associated with higher voltage levels present in the load system.
  • a load driving circuit can include a half bridge circuit having a pair of NMOS power transistors connected to the load at respective source and drain terminals to provide corresponding high and low side driving.
  • NMOS transistors to provide both high and low side driving can be advantageous due to the typically lower on resistance, higher power capability, and faster switching of NMOS transistors in comparison to PMOS transistors.
  • using NMOS transistors to provide high side driving creates the need to provide a functionally isolated or electrically floating supply voltage to a gate driver driving the high side NMOS transistor, as the source of the NMOS transistor is connected to the load.
  • One difficulty in providing an electrically floating supply voltage to a high side gate driver is that the gate driver draws energy from the source of the supply voltage while driving the load, potentially decreasing the supply voltage to levels that impact the performance of the gate driver itself.
  • Another difficulty is that initializing the electrically floating supply voltage has typically required an undesirably prolonged startup sequence involving the low side gate driver.
  • FIG. 1 is a schematic diagram depicting an embodiment of a system having an augmented power supply circuit and a half bridge circuit.
  • FIG. 2 is a schematic diagram depicting another embodiment of the system having the augmented power supply circuit and the half bridge circuit.
  • FIG. 3( a ) is a signal diagram depicting an embodiment of an output signal of a gate driver circuit.
  • FIG. 3( b ) is a signal diagram depicting another embodiment of an output signal of a gate driver circuit.
  • FIG. 3( c ) is a signal diagram depicting an embodiment of a supply voltage of an unaugmented bootstrap power supply circuit.
  • FIG. 3( d ) is a signal diagram depicting an embodiment of a supply voltage of the augmented power supply circuit.
  • FIG. 3( e ) is a signal diagram depicting another embodiment of the supply voltage of the augmented power supply circuit.
  • FIG. 3( f ) is a signal diagram depicting another embodiment of the supply voltage of the augmented power supply circuit.
  • FIG. 3( g ) is a signal diagram depicting another embodiment of the supply voltage of the augmented power supply circuit.
  • FIG. 3( h ) is a signal diagram depicting another embodiment of the supply voltage of the augmented power supply circuit.
  • FIG. 4( a ) is a signal diagram depicting another embodiment of an output signal of a gate driver circuit.
  • FIG. 4( b ) is a signal diagram depicting another embodiment of an output signal of a gate driver circuit.
  • FIG. 4( c ) is a signal diagram depicting another embodiment of a supply voltage of an unaugmented bootstrap power supply circuit.
  • FIG. 4( d ) is a signal diagram depicting another embodiment of the supply voltage of the augmented power supply circuit.
  • FIG. 5 is a graph depicting embodiments of power characteristics of the augmented power supply circuit.
  • FIG. 6( a ) is a signal diagram depicting another embodiment of an output signal of a gate driver circuit.
  • FIG. 6( b ) is a signal diagram depicting another embodiment of an output signal of a gate driver circuit.
  • FIG. 6( c ) is a signal diagram depicting another embodiment of the supply voltage of the augmented power supply circuit.
  • FIG. 7 is a schematic diagram depicting an embodiment of a control circuit that can be used to implement one or more control circuits of the augmented power supply circuit.
  • FIG. 8 is a schematic diagram depicting an embodiment of a polyphase system having a plurality of half bridge modules including the augmented power supply.
  • FIG. 9 is a schematic diagram depicting an embodiment of a system having the augmented power supply circuit and a single-switch load driving circuit.
  • FIG. 10 is a schematic diagram depicting another embodiment of a system having the augmented power supply circuit and a single-switch load driving circuit.
  • An embodiment of a power supply circuit to generate a supply voltage for a gate driver circuit can include an isolated power supply circuit to receive a first voltage in a first isolated system and provide power to a cyclic charging power supply circuit, the cyclic charging power supply circuit providing a supply voltage to the gate driver circuit in a second isolated system, the isolated power supply circuit providing the power to the cyclic charging power supply circuit while the gate driver circuit drives a transistor in an on state.
  • the isolated power supply circuit can include a control circuit to regulate the power provided so as to maintain or increase the supply voltage provided by the cyclic charging power supply circuit while the gate driver circuit drives the transistor in the on state.
  • the control circuit may regulate the power supplied to maintain or increase the supply voltage while the gate driver drives the transistor in the on state by one or more of: limiting a current supplied by the isolated power supply circuit to the cyclic charging power supply circuit to a current level below a predetermined level; limiting the supply voltage controlled by the isolated power supply circuit to a voltage at a predetermined voltage level below a peak supply voltage level provided by the cyclic charging power supply circuit; limiting the power provided by the isolated power supply circuit to below a predetermined substantially constant power level; limiting the power provided as a function of a temperature of the isolated power supply; selecting an impedance connecting the isolated power supply circuit to the cyclic charging power supply circuit.
  • the power supply circuit can also include the cyclic charging power supply circuit.
  • the cyclic charging power supply circuit may receive a second voltage in the second isolated system and provide an electrically floating supply voltage to the gate driver circuit while the gate driver circuit drives the transistor in the on state.
  • the cyclic charging power supply circuit can include one or more of a bootstrap power supply circuit or a charge pump power supply circuit.
  • the isolated power supply may supply power to the bootstrap power supply circuit to initially charge a capacitor of the bootstrap power supply circuit upon startup or reset of the power supply circuit.
  • the isolated power supply may supply this power to initially charge the capacitor of the bootstrap power supply while gate drivers for driving a load circuit are inactive.
  • FIG. 1 depicts an embodiment of a system 20 for driving a load 36 .
  • the system 20 can include an augmented power supply circuit 24 , a channel drive circuit 28 , a half bridge circuit 32 , and the load 36 .
  • the augmented power supply circuit 24 may supply a supply voltage VAPS to a gate driver circuit 40 - 1 of the channel drive circuit 28 .
  • the channel drive circuit 28 may deliver gate drive signals to the half bridge circuit 32 .
  • the half bridge circuit 32 may drive the load 36 .
  • the augmented power supply circuit 24 can include an isolated power supply circuit 44 and a cyclic charging power supply circuit 48 .
  • the isolated power supply circuit 44 may receive a first voltage V 1 in an isolated system on a first side of one or more isolation barriers 60 and supply power to the cyclic charging power supply circuit 48 in an isolated system on a second side of the one or more isolation barriers 60 .
  • the isolated power supply circuit 44 can include a power control circuit 52 to control the power delivered by the isolated power supply circuit 44 to the cyclic charging power supply circuit 48 .
  • the cyclic charging power supply circuit 48 may receive a second voltage V 2 in the isolated system on the second side of the one or more isolation barriers 60 and provide the supply voltage VAPS to the gate driver circuit 40 - 1 .
  • the cyclic charging power supply circuit 48 may provide the supply voltage VAPS as a function of a cyclic charging of a capacitive energy storage element such as a capacitor.
  • the second voltage V 2 can include one or more of a generated supply voltage or a voltage from a node of the system 20 .
  • the channel drive circuit 28 can include first and second isolated signal channel circuits 68 - 1 , 68 - 2 and first and second gate driver circuits 40 - 1 , 40 - 2 .
  • the isolated signal channel circuits 68 - 1 , 68 - 2 may receive respective input data signals from one or more data sources 72 - 1 , 72 - 2 in an isolated system on a first side of one more isolation barriers 76 and provide respective output data signals to the corresponding gate driver circuits 40 - 1 , 40 - 2 in an isolated system on a second side of the one or more isolation barriers 76 .
  • the gate driver circuits 40 - 1 , 40 - 2 may provide respective gate drive signals to corresponding transistors N 1 , N 2 of the half bridge circuit 32 in response to the output data signals received from the isolated signal channel circuits 68 - 1 , 68 - 2 .
  • the first gate driver circuit 40 - 1 may drive a gate of a first NMOS transistor N 1 of the half bridge circuit 32 to voltages ranging between the supply voltage VAPS received from the augmented power supply circuit 60 and a voltage VL at the load 36 .
  • the second gate driver circuit 40 - 2 may drive a gate of a second NMOS transistor N 2 of the half bridge circuit 32 to voltages ranging between the second voltage V 2 and a ground in the isolated system on the second side of the one or more isolation barriers 60 , 76 .
  • the half bridge circuit 32 can include the first and second NMOS transistors N 1 , N 2 to drive the load 36 .
  • the first NMOS transistor N 1 can include a gate connected to and receiving the gate drive signal from the first gate driver circuit 40 - 1 , a source connected to the load 36 , and a drain connected to a power bus VBUS on the second side of the one or more isolation barriers 60 , 76 .
  • the second NMOS transistor N 2 can include a gate connected to and receiving the gate drive signal from the second gate driver circuit 40 - 2 , a source connected to a ground on the second side of the one or more isolation barriers 60 , 76 , and a drain connected to the load 36 .
  • FIG. 2 depicts another embodiment of the system 20 for driving the load 36 , showing further details regarding embodiments of the augmented power supply circuit 24 and channel and driver circuits 28 .
  • the cyclic charging power supply circuit 48 can include a bootstrap power supply circuit 48 A.
  • the bootstrap power supply circuit 48 A of the augmented power supply circuit 24 may control a voltage at or a current supplied to the supply voltage node to provide a functionally isolated and/or electrically floating supply voltage VAPS to the first gate driver circuit 40 - 1 to enable the first gate driver circuit 40 - 1 to drive the first NMOS transistor N 1 of the half bridge circuit 32 .
  • the bootstrap power supply circuit 48 A can include a bootstrap capacitor C 1 , connected between terminals of the bootstrap power supply circuit 48 A, and a diode D 1 and a resistor R 1 connected in series between the second voltage V 2 of the isolated system and the bootstrap capacitor C 1 .
  • the terminals of the bootstrap power supply circuit 48 A may be connected to an upper and lower supply terminals of the first gate driver circuit 40 - 1 , with the lower terminal of the first gate driver circuit 40 - 1 and the bootstrap capacitor C 1 also connected to the source of the first NMOS transistor N 1 of the half bridge circuit 32 .
  • the first gate driver circuit 40 - 1 may drive the first NMOS transistor N 1 of the half bridge circuit 32 in an electrically non-conducting off state, the voltage VL at the load 36 and the lower terminal of the bootstrap capacitor C 1 may be driven toward the ground of the isolated system, and a current may flow through the diode D 1 and resistor R 1 of the bootstrap power supply circuit 48 from the second voltage V 2 of the isolated system to the upper terminal of the bootstrap capacitor C 1 to charge the bootstrap capacitor C 1 to a voltage approaching that of the second voltage V 2 minus a diode voltage drop.
  • the first gate driver circuit 40 - 1 may drive the first NMOS transistor N 1 into an on state, the voltage VL at the load 36 may no longer be driven toward ground, a current may no longer flow through the diode D 1 and resistor R 1 of the bootstrap power supply circuit 48 , and the bootstrap capacitor C 1 may instead provide the supply voltage VAPS that is functionally isolated and/or electrically floating relative to the voltage supply and ground (instead referenced from the voltage VL at the load 36 , the source of first NMOS transistor N 1 , and the lower terminal of the first gate drive circuit 40 - 1 ).
  • the bootstrap power supply circuit 48 A may thus provide a functionally isolated and/or electrically floating supply voltage VAPS to the first gate driver circuit 40 - 1 to enable the first gate driver circuit 40 - 1 to drive the first NMOS transistor N 1 in an on state.
  • a supply voltage provided by a bootstrap power supply operating alone to power a gate driver circuit may decrease over time as the gate driver circuit draws power from a bootstrap capacitor to drive a half bridge circuit. This may in turn limit the duty cycle variation of the half bridge circuit, as the gate driver circuit may no longer be able to drive the half bridge circuit when the bootstrap capacitor voltage falls below a certain threshold.
  • a bootstrap power supply operating alone may also require an undesirable lengthy startup sequence before the bootstrap power supply is able to supply a suitable supply voltage to a high side gate driver circuit, the sequence including a low side gate driver circuit and corresponding data channel circuits being activated and operated to turn on a low side transistor of the half bridge circuit before charging of the bootstrap capacitor can begin.
  • the isolated power supply circuit 44 may augment operation of the bootstrap power supply circuit 48 A within the augmented power supply circuit 24 to provide the supply voltage VAPS to the first gate drive circuit 40 - 1 in an improved manner to enable both an arbitrary duty cycle of the half bridge circuit 32 and an accelerated startup time of the system 20 , among other advantages.
  • the isolated power supply circuit 44 can include a power delivery circuit 82 and the power control circuit 52 .
  • the power delivery circuit 82 may deliver power to the bootstrap power supply circuit 48 A, including to the bootstrap capacitor C 1 , from the first voltage V 1 on the first side of the one or more first isolation barriers 60 , across the one or more isolation barriers 60 , and optionally via one or more components of the power control circuit 52 .
  • the power control circuit 52 may control the power delivered to the bootstrap power supply circuit 48 A by the isolated power supply circuit 44 .
  • the power delivery circuit 82 can include a driver circuit 86 , an isolator device 90 , and a rectifier circuit 94 .
  • the driver circuit 86 may drive the isolator device 90 as a function of an oscillation signal.
  • the driver circuit 86 can include an oscillator to provide the oscillation signal.
  • the isolator device 90 may provide communication across the one or more isolation barriers 60 .
  • the isolator device 90 can include an inductive isolator device such as one or more of a transformer or a coupled pair of inductors (which may be overlapping categories of devices).
  • the one or more isolation barriers 60 may provide galvanic isolation between the systems on either side of the isolation barriers 60 , and can include a layer of material such as polyimide.
  • the rectifier circuit 94 may rectify a signal received from the isolator device 90 to provide a rectified voltage.
  • the rectifier circuit 94 can include one or more diodes to perform the rectification.
  • the power delivery circuit 82 can also optionally include a filter circuit (not shown) that may filter the rectified signal.
  • the filter can include a capacitor. The filter can alternatively be omitted or incorporated into an output circuit 122 of the power control circuit 52 .
  • the power control circuit 52 can include one or more of a primary side power control circuit 98 or a secondary side power control circuit 102 .
  • the primary side power control circuit 98 may control the power delivered by the isolated power supply circuit 44 to the bootstrap power supply circuit 48 A by controlling operation of the driver circuit 86 on the first side of the one or more isolation barriers 60 .
  • the secondary side power control circuit 102 may control the power delivered by the isolated power supply circuit 44 to the bootstrap power supply circuit 48 A by controlling operation of an output circuit 122 of the secondary side power control circuit 102 on the second side of the one or more isolation barriers 60 .
  • the primary side power control circuit 98 can include a transmit circuit 106 , an isolator device 110 , a receive circuit 114 and a control circuit 118 .
  • the transmit circuit 106 may receive the rectified signal from the rectifier circuit 94 and drive a signal based on the rectified signal onto the isolator device 110 .
  • the transmit circuit may receive a sense signal from a sense circuit 126 (discussed below) of the secondary side power control circuit 102 and drive a signal based on the sense signal onto the isolator device 110 in addition to or instead of the rectified signal.
  • the transmit circuit 106 can include one or more components to encode and/or modulate the rectified signal to produce the drive signal.
  • the isolator device 110 may provide communication across the one or more isolation barriers 60 .
  • the isolator device 110 can include an inductive isolator device such as one or more of a transformer or a coupled pair of inductors.
  • the receive circuit 114 may receive a signal from the isolator device 110 and provide a signal based on the received signal to the control circuit 118 .
  • the receive circuit 114 can include one or more components to decode and/or demodulate the received signal to produce the signal provided to the control circuit 118 .
  • the control circuit 118 may control operation of the driver circuit 86 in response to the signal provided by the receive circuit 114 to control the power delivered by the power delivery circuit 82 to the bootstrap power supply circuit 48 A, as discussed further below.
  • the control circuit 118 can take a variety of forms, such as including circuitry configured to control operation of the driver circuit 86 .
  • the secondary side power control circuit 102 can include an output circuit 122 , a sense circuit 126 , and a control circuit 130 .
  • the output circuit 122 may provide an output signal for delivery to the bootstrap power supply circuit 48 A based on the rectified signal and any control signal received from the control circuit 130 .
  • the output circuit 122 can include one or more of a conductor, a resistor, a transistor, or other circuit components, according to embodiments discussed herein.
  • the sense circuit 126 may sense one or more of a voltage level or a current level of the output signal provided by the output circuit 122 and provide a signal representative of the sensed output signal to the control circuit 130 .
  • the sense circuit 126 can include one or more of a conductor, a voltage sensor, or a current sensor, according to embodiments discussed herein.
  • the control circuit 130 may control operation of the output circuit 122 in response to the signal provided by the sense circuit 126 to control the power delivered by the output circuit 122 to the bootstrap power supply circuit 48 A.
  • the control circuit 130 can take a variety of forms, such as including circuitry configured to control operation of the output circuit 122 as a function of the sensed signal.
  • Embodiments of the power control circuit 52 can optionally include only the primary side power control circuit 98 , only the secondary side power control circuit 102 , or both the primary and secondary side power control circuits 98 , 102 .
  • the functionality of the power control circuit 52 to control the power delivered by the isolated power supply circuit 44 to the bootstrap power supply circuit 48 can correspondingly be performed entirely by the primary side power control circuit 98 , entirely by the secondary side power control circuit 102 , or selectively distributed between the primary and secondary side power control circuits 98 , 102 .
  • the isolated power supply circuit 44 may augment operation of the bootstrap power supply circuit 48 A to enable provision of the supply voltage VAPS to the first gate drive circuit 40 - 1 in an improved manner by selectively supplying power to the bootstrap power supply circuit 48 A to augment the power developed and supplied by the bootstrap power supply circuit 48 A.
  • the isolated power supply circuit 44 may augment operation of the bootstrap power supply circuit 48 A by supplying power to the bootstrap power supply circuit 48 A during and in response to a phase of the first gate driver circuit 40 - 1 to drive the first NMOS transistor N 1 of the half bridge circuit 32 in an on state.
  • the isolated power supply circuit 44 also may not supply power to the bootstrap power supply circuit 48 A during and in response to a phase of the first gate driver circuit 40 - 1 to drive the first NMOS transistor N 1 of the half bridge circuit 32 in an off state.
  • the isolated power supply circuit 44 may supply power to the bootstrap power supply circuit 48 A during the phase of the first gate driver circuit 40 - 1 to drive the first NMOS transistor N 1 of the half bridge circuit 32 in the on state as a function of the supply voltage VAPS during this phase and as discussed below.
  • FIG. 3 is a diagram depicting embodiments of signals of the augmented power supply circuit 24 and gate driver circuits 40 - 1 , 40 - 2 . Note that FIG. 3 , as well as FIGS. 4 and 6 , discussed below, may not show voltage level relationships of and/or between various depicted signals to scale, and instead may exaggerate certain voltage level relationships for purposes of illustration.
  • FIG. 3( a ) depicts an embodiment of a logical representation of an output voltage VA of the first gate driver circuit 40 - 1 and FIG. 3( b ) depicts an embodiment of a logical representation of an output voltage VB of the second gate driver circuit 40 - 2 .
  • the first gate driver circuit 40 - 1 outputs a voltage representing a logical high signal, turning the first NMOS transistor N 1 of the half bridge circuit 32 on, and the second gate driver circuit 40 - 2 outputs a voltage representing a logical low signal, keeping the second NMOS transistor N 2 of the half bridge circuit 32 off.
  • the first gate driver circuit 40 - 1 outputs a voltage representing a logical low signal, turning the first NMOS transistor N 1 off.
  • the first NMOS transistor N 1 drives the load 36 and the second NMOS transistor N 2 is deactivated.
  • the second gate driver circuit 40 - 2 outputs a voltage representing a logical high signal, turning the second NMOS transistor N 2 on, and the first gate driver circuit 40 - 1 continues to output a voltage representing a logical low signal, keeping the first NMOS transistor N 1 off.
  • the second gate driver circuit 40 - 2 outputs a voltage representing a logical low signal, turning the second NMOS transistor N 2 off.
  • the second NMOS transistor N 2 drives the load 36 and the first NMOS transistor N 1 is deactivated. This cycle can repeat periodically, for example as at times t 5 , t 6 , t 7 and t 8 .
  • the duty cycles and/or on times of the outputs of the first and second gate driver circuits 40 - 1 , 40 - 2 and the half bridge circuit 32 can vary during operation of the half bridge circuit 32 to drive the load 36 .
  • the duty cycles of the outputs of the first and second gate driver circuits 40 - 1 , 40 - 2 are relatively equal.
  • FIG. 4 is a diagram depicting additional embodiments of signals of the augmented power supply circuit 24 and the gate driver circuits 40 - 1 , 40 - 2 .
  • 4( a ) and 4( b ) depict embodiments of logical representations of output voltages of the first and second gate driver circuits 40 - 1 , 40 - 2 , respectively, in which the duty cycles of the outputs of the first and second gate driver circuits 40 - 1 , 40 - 2 are fairly unequal, with the output of the first gate driver circuit 40 - 1 having a much higher duty cycle than the output of the second gate driver circuit 40 - 2 .
  • FIG. 3( c ) depicts an embodiment of a supply voltage VS provided by a bootstrap power supply circuit without augmentation by the isolated power supply circuit.
  • the bootstrap power supply circuit Prior to time t 1 , the bootstrap power supply circuit has generated a supply voltage VS.
  • a gate driver circuit begins to draw power from a bootstrap capacitor of the bootstrap power supply circuit to drive a half bridge circuit, and the supply voltage VS supplied by the bootstrap power supply circuit accordingly suffers an immediate sharp decrease followed by a more gradual further decrease over time.
  • FIG. 4( c ) depicts another embodiment of a supply voltage VS provided by a bootstrap power supply circuit without augmentation by the isolated power supply circuit, in which the supply voltage VS does decrease below the threshold voltage VTH due to the relatively higher duty cycle depicted, thereby adversely affecting operation of the gate driver circuit and half bridge circuit.
  • the isolated power supply circuit 44 may operate to selectively provide power to the bootstrap power supply circuit 48 A to maintain or increase the supply voltage VAPS provided to the first gate driver circuit 40 - 1 and enable an arbitrary duty cycle variation and/or on time of the first gate driver circuit 40 - 1 and half bridge circuit 32 .
  • the power control circuit 52 may operate in various different power control modes, including one or more of a current regulation mode, a voltage regulation mode, a power regulation mode, a temperature regulation mode, an impedance regulation mode, or a startup/reset mode.
  • the power control circuit 52 may operate to control the power provided by the isolated power supply circuit 44 as a function of an output current IO supplied by the isolated power supply circuit 44 to the bootstrap power supply circuit 48 A.
  • the current regulation mode can include operation by the power control circuit 52 to control the supply of power to power levels corresponding to an output current IO at or below a selected predetermined current level.
  • FIGS. 3( d ), 3( e ) and 3( f ) depict embodiments of the supply voltage VAPS provided by operation of the bootstrap power supply circuit 48 A augmented by the isolated power supply circuit 44 operating in the current regulation mode.
  • the isolated power supply 44 in response to the first gate driver circuit 40 - 1 driving the first NMOS transistor of the half bridge circuit 32 in the on state, the isolated power supply 44 begins to deliver power to the bootstrap power supply circuit 48 A at an output current limited to a selected current level.
  • the isolated power supply circuit 44 prevents the supply voltage VAPS from decreasing as the first gate driver circuit 40 - 1 draws power, and even supplies enough power to gradually increase the supply voltage VAPS while the first gate driver circuit 40 - 1 is driving the first NMOS transistor N 1 in the on state.
  • FIGS. 3( e ) and 3( f ) show similar scenarios, with the power being supplied in the same fashion but at a higher predetermined current limit in FIG. 3( e ) , and the power being supplied in a current-limited manner showing a time constant characteristic in FIG. 3( f ) , such as may result from specific forms of the output circuit 122 .
  • the power control circuit 52 may operate to control the power provided by the isolated power supply circuit 44 as a function of the output voltage VO supplied by the isolated power supply circuit 44 to the bootstrap power supply circuit 48 A.
  • the voltage regulation mode can include operation by the power control circuit 52 to control the supply of power to power levels corresponding to an output voltage VO at a selected predetermined voltage level.
  • FIGS. 3( g ) and 3( h ) depict embodiments of the supply voltage VAPS provided by operation of the bootstrap power supply circuit 48 augmented by the isolated power supply circuit 44 operating in the voltage regulation mode.
  • the isolated power supply circuit 44 in response to the first gate driver circuit 40 - 1 driving the first NMOS transistor N 1 of the half bridge circuit 32 in the on state, delivers power to the bootstrap power supply circuit 48 A at a level to increase the supply voltage VAPS until the supply voltage VAPS reaches a selected predetermined voltage limit VLIM 1 , at which point the isolated power supply circuit 44 delivers power to the bootstrap power supply circuit 48 A at a level to only maintain the supply voltage VAPS at the predetermined voltage limit.
  • FIG. 3( h ) shows a similar scenario, but involving a relatively higher selected predetermined voltage limit VLIM 2 .
  • the predetermined voltage level at which the power control circuit 52 can control the isolated power supply circuit 44 to provide power may be selected to have a predetermined relationship to the peak level of the supply voltage VAPS provided by the bootstrap power supply circuit 48 A at the beginning of phase during which the gate driver circuit 40 - 1 drives the transistor N 1 in the on state.
  • the predetermined voltage level can be selected to be lower than the peak level of the supply voltage VAPS provided by the bootstrap power supply 48 A, which may enable the bootstrap power supply circuit 48 A to act as a primary source of supply power for the gate driver circuit 40 - 1 and the isolated power supply circuit to act as a supplemental source of supply power for the gate driver circuit 40 - 1 .
  • Such a division of primary and supplemental supply power delivery may advantageously utilize strengths and offset weaknesses in operation of the augmented power supply circuit 24 in some instances, such as by avoiding overheating of the isolated power supply circuit 44 that may accompany excessive power delivery by the isolated power supply circuit 44 .
  • the power control circuit 52 may implement a negative feedback setpoint control scheme having the selected predetermined voltage level as a setpoint.
  • the power control circuit 52 may operate to control the power provided by the isolated power supply circuit 44 as a function of the output power supplied by the isolated power supply circuit 44 to the bootstrap power supply circuit 48 A.
  • the current regulation mode can include operation by the power control circuit 52 to control the supply of power at power levels at or below a selected predetermined level of the output power.
  • FIG. 5 is a graph depicting embodiments of power characteristics of the isolated power supply circuit 44 .
  • the x- and y-axes represent the output current IO and the output voltage VO, respectively, of the isolated power supply 44 .
  • a first plot shows an embodiment of the power transfer characteristic 150 of the isolated power supply 44 without any regulation.
  • a second plots shows an embodiment of a first constant power characteristic 154 representing combinations of output voltages and output currents resulting in a first constant power level.
  • a third plots shows an embodiments of a second constant power characteristic 158 representing combinations of output voltages and output currents resulting in a second constant power level greater than the first constant power level.
  • the power control circuit 52 can limit the output voltage VO and the output current IO to levels underneath a constant power characteristic corresponding to the selected predetermined power level. For example, to supply power at power levels at or below the first constant power level depicted in FIG. 5 , the power control circuit 52 can limit the output voltage VO to levels below a first constant-power voltage level VCP 1 and the output current IO to levels below a first constant-power current level ICP 1 . Similarly, to supply power at power levels at or below the second constant power level depicted in FIG. 5 , the power control circuit can limit the output voltage VO to levels below a second constant power-voltage level VCP 2 and the output current IO to levels below a second constant-power current level ICP 2 .
  • the power control circuit 52 may select the predetermined power level for purpose of limiting the power supplied by the isolated power supply 44 as a function of various factors. For example, the power control circuit 52 may select the predetermined power level for purpose of limiting the power supplied by the isolated power supply 44 as a function of an actual or estimated operating temperature of the isolated power supply 44 . In such a scenario, the power control circuit 52 may select one or more relatively higher predetermined power level limits for relatively lower temperatures of the isolated power supply 44 , and one or more relatively lower predetermined power level limits for relatively higher temperatures of the isolated power supply 44 .
  • the power control circuit 52 may operate to control the power provided by the isolated power supply circuit 44 as a function of an actual or estimated operating temperature of the isolated power supply circuit 44 .
  • the temperature regulation mode can include operation by the power control circuit 52 to control the supply of power to power levels corresponding to operating temperatures of the isolated power supply circuit 44 at or below a selected predetermined temperatures.
  • the augmented power supply circuit 24 or another component of the system 20 can optionally include a temperature sensor or temperature estimation circuit for use in measuring or estimated the temperature of the isolated power supply circuit 44 as discussed above.
  • the power control circuit 52 may operate to control the power provided by the isolated power supply circuit 44 as a function of an impedance of the isolated power supply circuit 44 .
  • the impedance regulation mode can include operation by the power control circuit 52 to control the supply of power by the use and/or selection of an impedance in the output circuit 122 in the path of connection of the power delivery circuit 82 to the bootstrap power supply circuit 48 A.
  • the impedance regulation mode may include use, selection or control by the power control circuit of an impedance in the output circuit 122 having a relatively higher impedance level, such as a relatively higher resistance, to supply power at a relatively lower power lower; and use, selection or control by the power control circuit 52 of an impedance in the output circuit 122 having a relatively lower impedance level, such as a relatively lower resistance, to supply power at a relatively higher power lower.
  • Embodiments of the power, temperature and impedance regulation modes may produce supply voltages VAPS having characteristics resembling those depicted in FIGS. 3( d )-3( h ) in some respects.
  • the isolated power supply circuit 44 may operate to limit the power supplied to the bootstrap power supply circuit 48 A for relatively large duty cycles and/or on times of the first gate driver circuit 40 - 1 and the half bridge circuit 32 . Limiting the power supplied in such circumstances can further enable arbitrary duty cycles of the gate driver circuits 40 - 1 , 40 - 2 and half bridge circuit 32 by preventing the development of too large of supply voltage.
  • FIG. 4( d ) depicts an embodiment of the supply voltage VAPS supplied by the augmented power supply circuit 24 for a relatively large duty cycle and/or on time of the first gate driver circuit 40 - 1 and first NMOS transistor N 1 .
  • FIG. 4( d ) depicts an embodiment of the supply voltage VAPS supplied by the augmented power supply circuit 24 for a relatively large duty cycle and/or on time of the first gate driver circuit 40 - 1 and first NMOS transistor N 1 .
  • the supply voltage VAPS upon the first gate driver circuit 40 - 1 driving the first NMOS transistor N 1 into the on state, the supply voltage VAPS initially increases but after a time period reaches a maximum level VMAX and no longer increases.
  • the isolated power supply circuit 44 can implement the maximum supply voltage level VMAX as either a configured natural limit of the isolated power supply circuit 44 to augment the bootstrap power supply circuit 48 A to boost the supply voltage VAPS, or by using one of the operating modes of the power control circuit 52 as discussed above, such as the voltage regulation mode.
  • the augmented power supply circuit 24 may also operate to enable an improved startup sequence of the system 20 by providing an initial charging of the bootstrap capacitor C 1 of the bootstrap power supply circuit 48 A by the isolated power supply circuit 44 upon startup, reset or in other operational scenarios of the system 20 .
  • FIG. 6 is a signal diagram depicting embodiments of signals of the gate driver circuits 40 - 1 , 40 - 2 and the augmented power supply circuit 24 .
  • FIG. 6( a ) depicts an embodiment of a logical representation of an output voltage VA of the first gate driver circuit 40 - 1
  • FIG. 6( b ) depicts an embodiment of a logical representation of an output voltage VB of the second gate driver circuit 40 - 2
  • FIG. 6( c ) depicts an embodiment of the supply voltage VAPS provided by the augmented power supply circuit 24 .
  • the system 20 is activated from a deactivated state, at which time the outputs VA, VB of both of the first and second gate driver circuits 40 - 1 , 40 - 2 remain in a logic low state, the first and second NMOS transistors N 1 , N 2 of the half bridge circuit 32 remain off, and the bootstrap capacitor C 1 is in a substantially uncharged state.
  • the isolated power supply circuit 44 becomes fully active and begins to supply power to the bootstrap power supply circuit 48 A and charge the bootstrap capacitor C 1 , and thus the supply voltage VAPS begins to increase, while the outputs VA, VB of both of the first and second gate driver circuits 40 - 1 , 40 - 2 remaining in a logic low state and the first and second NMOS transistors N 1 , N 2 remain off.
  • the bootstrap capacitor C 1 reaches a fully charged level and the supply voltage VAPS reaches a fully activated value, again with the outputs VA, VB of both of the first and second gate driver circuits 40 - 1 , 40 - 2 remaining in a logic low state and the first and second NMOS transistors N 1 , N 2 remaining off.
  • the output VA of the first gate driver circuit 40 - 1 may transition to a logic high value, activating the first NMOS transistor N 1 for the first time after the startup or reset.
  • a bootstrap power supply operating alone may require an undesirable lengthy startup sequence before the bootstrap power supply is able to supply a suitable supply voltage to a high side gate driver circuit, as a low side gate driver circuit and corresponding data channel circuits must be activated and operated to turn on a low side transistor of the half bridge circuit before charging of the bootstrap capacitor can begin.
  • the power control circuit 52 of the isolated power supply 44 can be configured in a variety of different ways to provide one or more of the functions of the isolated power supply 44 discussed above.
  • the power control circuit 52 can be hardwired to provide one or more of these functions.
  • the power control circuit 52 can be programmable to provide one or more of these functions.
  • FIG. 7 depicts an embodiment of a control circuit 162 that can be used to implement one or both of the control circuits 118 , 130 of the primary and secondary power control circuits 98 , 102 .
  • the control circuit 162 can include one or more of a current regulation module 166 to implement the current regulation mode, a voltage regulation module 170 to implement the voltage regulation mode, a power regulation module 174 to implement the power regulation mode, a temperature regulation module 178 to implement the temperature regulation mode, an impedance regulation module 182 to implement the impedance regulation mode, or a startup/reset module 186 to implement startup functions.
  • the power control circuit 52 can also be configured to take a minimal form necessary to only provide certain selected ones of the functions discussed above.
  • the isolated power supply circuit 44 may be essentially unregulated, such as by omitting feedback regulation, and the power control circuit 52 can include circuitry configured to operate the forward power delivery circuit in an selected essentially unregulated state, such as an embodiment of the control circuit 118 of the primary side power control circuit 98 or an equivalent circuit, and omit other components.
  • the augmented power supply circuit 24 can trigger the isolated power supply circuit 44 to supply power to the bootstrap power supply circuit 48 A in different ways.
  • the isolated power supply circuit 44 can begin and/or stop supplying power to the bootstrap power supply circuit 48 A in response to a trigger event such as one or more of a startup of the isolated system 20 , a change in the logic level output of the first gate drive circuit 40 - 1 , or a value of the supply voltage VAPS passing a predetermined level.
  • the augmented power supply circuit may be used in both single and polyphase systems.
  • embodiments of the system 20 depicted in FIG. 1 or 2 may be used as a single phase system.
  • FIG. 8 depicts an embodiment of a system 188 that may be used as a polyphase system.
  • the system 188 can include a plurality of half bridge modules 190 - 1 , 190 - 2 , 190 - 3 , each of the half bridge modules 190 - 1 , 190 - 2 , 190 - 3 including embodiments of the augmented power supply 24 , channel drive circuit 28 , and half bridge circuit 32 as in FIG. 1 or 2 .
  • Each of the half bridge modules 190 - 1 , 190 - 2 , 190 - 3 can be connected to a load 194 to provide a single phase of a polyphase system.
  • FIG. 8 depicts an embodiment of the system 188 having three half bridge modules 190 - 1 , 190 - 2 , 190 - 3 , and thus may be suitable for use a three phase system, other embodiments of the system 188 can include any number of half bridge modules 190 - 1 , 190 - 2 , 190 - 3 . . . to provide a polyphase system with an arbitrary number of phases.
  • the isolated signal channel circuits 68 - 1 , 68 - 2 can each include a transmit circuit 134 - 1 , 134 - 2 , an isolator device 138 - 1 , 138 - 2 , and a receive circuit 142 - 1 , 142 - 2 .
  • the transmit circuit 134 - 1 , 134 - 2 may receive the input data signal from the data source 72 - 1 , 72 - 2 and drive a signal based on the input data signal onto the isolator device 138 - 1 , 138 - 2 .
  • the transmit circuit 134 - 1 , 134 - 2 can include one or more components to encode and/or modulate the input data signal to produce the drive signal.
  • the isolator device 138 - 1 , 138 - 2 may provide communication across the one or more isolation barriers 76 and can include an inductive isolator device such as one or more of a transformer or a coupled pair of inductors.
  • the one or more isolation barriers 76 may provide galvanic isolation between the systems on either side of the isolation barriers 76 and can include a layer of material such as polyimide.
  • the receive circuit 142 - 1 , 142 - 2 may receive a signal from the isolator device 138 - 1 , 138 - 2 and provide a signal based on the received signal to respective gate drive circuit 40 - 1 , 40 - 2 .
  • the receive circuit 142 - 1 , 142 - 2 can include one or more components to decode and/or demodulate the received signal to produce the signal provided to the gate drive circuit 40 - 1 , 40 - 2 .
  • the ground connections depicted may exist on various sides of the one or more isolation barriers 60 , 76 .
  • the ground connection to the first voltage V 1 may exist on the first side (to the left as depicted) of one or more of the one or more isolation barriers 60 , 76 .
  • the ground connection to the second voltage V 2 may exist on either the first side or a second side (to the right as depicted) of one or more of the one or more isolation barriers 60 , 76 .
  • the ground connection to the transistor N 2 may exist on either the first side or the second side of one or more of the one or more isolation barriers 60 , 76 .
  • the number of isolated systems and isolation barriers may vary.
  • the allocation of circuits and/or systems discussed herein to semiconductor dies may also vary.
  • the augmented power supply circuit 24 may also be used with single-switch load driving circuits and other embodiments of multiple-switch load driving circuits.
  • FIG. 9 depicts an embodiment of a system 200 including the augmented power supply circuit 24 and a single-switch load driving circuit.
  • the single switch load driving circuit can include a single low-side NMOS transistor N 3 to drive a load 204 .
  • the single NMOS transistor N 3 can include a gate connected to and receiving a gate drive signal from a gate driver circuit 40 - 3 , a drain connected to the load 204 , and a source connected to ground.
  • a bootstrap power supply circuit 48 B of the augmented power supply circuit 24 can include a bootstrap capacitor C 2 , a diode D 3 , a capacitor C 3 , a resistor R 2 , a diode D 3 , and a shunt regulator 208 .
  • the bootstrap power supply circuit 48 B may charge the bootstrap capacitor C 2 while the transistor N 3 is driven in an on state by the gate driver 40 - 3 through a path from the load voltage VLA including the resistor R 2 , capacitor C 3 and diode D 2 , so that the bootstrap power supply circuit 48 B may provide a functionally isolated and/or electrically floating supply voltage VAPSA to the gate driver circuit 40 - 3 when the gate driver circuit 40 - 3 is driving the NMOS transistor N 3 in the on state as a function of the load voltage VLA, which may be referred to as a self bootstrap operation.
  • the isolated power supply circuit 44 of the augmented power supply circuit 24 may provide power to the bootstrap power supply circuit 48 B while the gate driver circuit 40 - 3 is driving the NMOS transistor N 3 in the on state and to initially charge the capacitor C 2 upon startup or reset of the augmented power supply circuit 24 as variously discussed herein.
  • the augmented power supply circuit 24 may also be used with other embodiments of single switch load driving circuits.
  • Such single switch load driving circuits can include one or more of a single low-side NMOS transistor connected to and driving a load (such as, e.g., the single low-side NMOS transistor configuration depicted in FIG. 9 , discussed above), a single high-side NMOS transistor connected to and driving a load (such as, e.g., the single high-side NMOS transistor configuration depicted in FIG.
  • a single floating NMOS transistor to provide bi-directional driving of first and second loads such as, e.g., a single floating NMOS transistor including a gate connected to and receiving a gate drive signal from a gate driver circuit, a drain connected to the first load, and a source connected to the second load).
  • the cyclic charging power supply circuit 48 of the augmented power supply circuit 24 may include one or more of a bootstrap power supply circuit, a charge pump power supply circuit, or other cyclic charging power supply circuits.
  • FIG. 10 depicts another embodiment of a system 212 including the augmented power supply circuit 24 and a single-switch load driving circuit.
  • the cyclic charging power supply circuit 48 can include a combined bootstrap and charge pump power supply circuit 48 C.
  • the combined bootstrap and charge pump power supply circuit 48 C can include a bootstrap capacitor C 4 , a diode D 4 , a charge pump capacitor C 5 , a diode D 5 , a diode D 6 , a capacitor C 6 , a resistor R 3 and a shunt regulator 220 .
  • the single switch load driving circuit can include a single high-side NMOS transistor N 4 to drive a load 216 .
  • the single NMOS transistor N 4 can include a gate connected to and receiving a gate drive signal from a gate driver circuit 40 - 4 , a drain connected to the power bus VBUS, and a source connected to the load 216 .
  • the combined bootstrap and charge pump power supply circuit 48 C may charge the charge pump capacitor C 5 while the transistor N 4 is driven in an on state by the gate driver circuit 40 - 4 through a path from the load voltage VLB including the resistor R 3 , capacitor C 6 and diode D 5 .
  • the bootstrap capacitor C 4 may be charged while the transistor N 4 is driven in an off state by the gate driver circuit 40 - 4 , through a path from the capacitor C 5 through the diode D 4 .
  • the combined bootstrap and charge pump power supply circuit 48 C may provide a functionally isolated and/or electrically floating supply voltage VAPSB to the gate driver circuit 40 - 4 when the gate driver circuit 40 - 4 is driving the NMOS transistor N 4 is the on state as a function of the load voltage VLB when the NMOS transistor N 4 is in the off state.
  • the isolated power supply circuit 44 of the augmented power supply circuit 24 may provide power to the combined bootstrap and charge pump power supply circuit 48 C while the gate driver circuit 40 - 4 is driving the NMOS transistor N 4 in the on state and to initially charge the capacitor C 4 upon startup or reset of the augmented power supply circuit 24 as variously discussed herein.
  • Transistors included in load driving circuits operated by utilizing the augmented power supply circuit may be different types of transistors, such as one or more of field effect transistors (FETs) (as depicted in these figures), insulated gate bipolar transistors (IGBTs), bipoloar junction transistors (BJTs) or other types of transistors.
  • FETs field effect transistors
  • IGBTs insulated gate bipolar transistors
  • BJTs bipoloar junction transistors
  • Transistors in embodiments of these load driving circuits can also include one or more of NMOS, PMOS, n-channel IGBT, p-channel IGBT, NPN BJT or PNP BJT transistors.
  • any feature of any of the embodiments of the systems and augmented power supply circuit 24 described herein can optionally be used in any other embodiment of the systems and augmented power supply circuit 24 .
  • embodiments of the systems and augmented power supply circuit 24 can optionally include any subset or ordering of the components or features of the systems and augmented power supply circuit 24 described herein.

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International Rectifier, "High and Low Side Driver", Data Sheet No. PD60147 rev.U, IR2110(-1-2)(S)PbF/IR2113(-1-2) (S)PbF, Mar. 23, 2005, 18 pages.

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DE102015119492A1 (de) 2016-05-19

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