US9118160B2 - VCSEL and manufacturing method of the same - Google Patents

VCSEL and manufacturing method of the same Download PDF

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Publication number
US9118160B2
US9118160B2 US14/195,778 US201414195778A US9118160B2 US 9118160 B2 US9118160 B2 US 9118160B2 US 201414195778 A US201414195778 A US 201414195778A US 9118160 B2 US9118160 B2 US 9118160B2
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layer
disposed
impurity
impurity layer
reflective layer
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US14/195,778
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US20140348194A1 (en
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Hyundai Park
Gyungock Kim
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Electronics and Telecommunications Research Institute ETRI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0218—Substrates comprising semiconducting materials from different groups of the periodic system than the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0421—Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers
    • H01S5/0422—Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers with n- and p-contacts on the same side of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/021—Silicon based substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0215—Bonding to the substrate

Definitions

  • laser light source chips are mounted on a silicon substrate as the following methods. That is, laser light source chips may be manufactured on a substrate formed of direct bandgap materials having superior light generation efficiency. Then, the laser light source chips may be flip-chip bonded on the silicon substrate.
  • the typical methods of manufacturing the laser light source have low throughput per unit time in flip-chip processes of aligning and bonding the laser light source chips to reduce productivity.
  • a height difference between the individual light source chip and the silicon substrate may be about 100 ⁇ m or more.
  • the typical methods of manufacturing the laser light source may have an additional difficulty in packaging processes including an electrical wiring process and the like.
  • the present invention provides a vertical-cavity surface-emitting laser (VCSEL) which is capable of improving productivity and a method of manufacturing the same.
  • VCSEL vertical-cavity surface-emitting laser
  • the present invention also provides a VCSEL and manufacturing method of the same which has a conductive bonding interface having efficient electrical resistance characteristics.
  • the first impurity layer may include conductive impurities doped in the silicon substrate, wherein the lower reflective layer may have the same conductive type as that of the first impurity layer.
  • the VCSELs may further include a lower current aperture disposed between the first impurity layer and the lower reflective layer and disposed on an edge of the first impurity layer and lower reflective layer.
  • the upper current aperture may include an oxide or under cut.
  • the VCSELs may further include a bonding thin film layer between the first impurity layer and the lower reflective layer.
  • the VCSELs may further include: a lower electrode disposed on the first impurity layer outside the lower reflective layer; and an upper electrode disposed on the upper reflective layer.
  • the patterning of the III-V semiconductor light source-active layer may include forming an upper current aperture on an edge of the light generation layer between the lower reflective layer and the upper reflective layer.
  • the lower current aperture may include a second impurity layer doped with first conductive type impurities having a concentration higher than that of the first conductive type impurities doped into the first impurity layer.
  • FIG. 1 is a cross-sectional view of a vertical-cavity surface-emitting laser (VCSEL) according to a first embodiment of the inventive concept;
  • VCSEL vertical-cavity surface-emitting laser
  • FIG. 7 is a cross-sectional view of a VCSEL according to a second embodiment of the inventive concept.
  • FIGS. 8 to 11 are cross-sectional views illustrating a method of manufacturing the VCSEL on the basis of FIG. 7 according to the second embodiment of the inventive concept;
  • the III-V semiconductor light source-active layer 20 may be monolithically integrated on the silicon substrate 10 by wafer bonding.
  • the III-V semiconductor light source layer 20 may have a mesa shape.
  • the III-V semiconductor light source layer 20 may include a lower reflective layer 22 , a light generation layer 24 , an upper reflective layer 26 , and an upper current aperture 28 .
  • the light generation layer 24 may be disposed on the lower reflective layer 22 .
  • the light generation layer 24 may include InGaAsP, InGaAlAs, AlGaAs, InAlAs, InGaP, GaAs, or InGaAs that has a quantum well structure and a quantum dot structure.
  • the upper reflective layer 26 may be disposed on the light generation layer 24 .
  • the upper reflective layer 26 may include InP, AlGaAs, or InGaP that is doped with second conductive type impurities.
  • the second conductive type impurities may have a conductive type opposite to that of the first conductive type impurities.
  • the second conductive type impurities may be a donor.
  • the second conductive type impurities may include phosphorus or arsenic.
  • FIG. 7 is a cross-sectional view of a VCSEL according to a second embodiment of the inventive concept.
  • the VCSEL according to the second embodiment of the inventive concept may include a second impurity layer 16 disposed between a first impurity layer 14 and a lower semiconductor layer 22 .
  • the second impurity layer 16 may be doped with first conductive type impurities.
  • the second impurity layer 16 may be a lower aperture.
  • the second impurity layer 16 may be disposed in an edge of an upper portion of the first impurity layer 14 .
  • the upper current aperture 28 of the first embodiment is omitted, and the second impurity layer 16 of the lower aperture is provided.
  • FIGS. 8 to 11 are cross-sectional views illustrating a method of manufacturing the VCSEL on the basis of FIG. 7 according to the second embodiment of the inventive concept.
  • a portion of the first conductive type impurities in the second impurity layer 16 may be combined with the second conductive type impurities to lose the first conductive property, and the other portion of the first conductive type impurities may remain to give the first conductive property to the second impurity layer 16 .
  • a wafer 60 is bonded on the first and second impurity layers 14 and 16 .
  • the wafer 60 may include a III-V semiconductor substrate 50 and a III-V semiconductor light source-active layer 20 .
  • the III-V semiconductor light source-active layer 20 may be bonded on the first and second impurity layers 14 and 16 .
  • the III-V semiconductor light source-active layer 20 and the first impurity layer 14 may have a conductive bonding interface 42 therebetween.
  • FIG. 13 is a cross-sectional view illustrating a method of manufacturing the VCSEL according to the third embodiment of the inventive concept.
  • the wafer 60 is bonded on the first and second impurity layers 14 and 16 .
  • the upper current aperture 28 is formed on the edge of the light generation layer 24 .
  • the upper and lower electrodes 34 and 32 may be formed on the upper reflective layer 26 and the first impurity layer 14 , respectively.
  • FIG. 14 is a cross-sectional view of a VCSEL according to a fourth embodiment of the inventive concept.
  • the VCSEL according to the fourth embodiment of the inventive concept may include a metal bonding layer 40 between a silicon substrate 10 and a III-V semiconductor light source-active layer 20 .
  • the metal bonding layer 40 may be a bonding thin film layer.
  • the metal bonding layer 40 and silicon substrate 10 may be bonded to each other with an ohmic contact resistance characteristic therebetween.
  • the metal bonding layer 40 and the III-V semiconductor light source-active layer 20 may be bonded to each other with an ohmic contact resistance characteristic therebetween.
  • the silicon substrate 10 and the III-V semiconductor light source-active layer 20 may be electrically connected to each other.
  • the metal bonding layer 40 is provided between the silicon substrate 10 and the III-V semiconductor light source layer 20 of the first embodiment.
  • FIGS. 15 to 18 are cross-sectional views illustrating a method of manufacturing the VCSEL according to the fourth embodiment of the inventive concept.
  • the silicon substrate 10 , the metal bonding layer 40 , and the wafer 60 are bonded to each other.
  • the metal bonding layer 40 may be bonded on the silicon substrate 10 .
  • the metal bonding layer 40 may be bonded on the wafer 60 .
  • the present invention is not limited thereto, and thus various embodiments may be applied to the present invention.
  • the metal bonding layer 40 may be bonded on each of the silicon substrate 10 and the wafer 60 , and then the metal bonding layers 40 of the silicon substrate 10 and the wafer 60 may be bonded to each other.
  • the metal bonding layer 40 may be bonded on the III-V semiconductor light source-active layer 20 of the wafer 60 .
  • an upper current aperture 28 is formed on an edge of a light generation layer 24 .
  • upper and lower electrodes 34 and 32 may be formed on an upper reflective layer 26 and the first impurity layer 14 , respectively.
  • the VCSEL according to the embodiments of the inventive concept may include the silicon substrate and the III-V semiconductor light source-active layer having the conductive bonding interface therebetween.
  • the silicon substrate and the III-V semiconductor light source-active layer may be easily bonded to each other by the wafer bonding.
  • the wafer bonding may efficiently stably provide the thermal and electrical resistance between the silicon substrate and the III-V semiconductor light source-active layer. Therefore, the VCSEL and the method of manufacturing the same according to the embodiments of the inventive concept may improve productivity.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)
US14/195,778 2013-05-24 2014-03-03 VCSEL and manufacturing method of the same Expired - Fee Related US9118160B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20130059190A KR20130062969A (ko) 2013-05-24 2013-05-24 웨이퍼 본딩을 사용한 수직 공진형 표면 방출 레이저 구조 및 제작 방법
KR10-2013-0059190 2013-05-24
KR1020130112714A KR102034740B1 (ko) 2013-05-24 2013-09-23 수직공진 표면방출 레이저 및 그의 제조방법
KR10-2013-0112714 2013-09-23

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107265392A (zh) * 2016-04-01 2017-10-20 英飞凌科技股份有限公司 光发射器装置、光声气体传感器和用于形成光发射器装置的方法
US10389090B2 (en) 2017-11-21 2019-08-20 International Business Machines Corporation Lateral growth of edge-emitting lasers
US10955599B2 (en) 2016-04-01 2021-03-23 Infineon Technologies Ag Light emitter devices, photoacoustic gas sensors and methods for forming light emitter devices

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180015630A (ko) * 2015-06-09 2018-02-13 코닌클리케 필립스 엔.브이. 수직 공동 표면 방사 레이저
KR102160030B1 (ko) * 2019-01-17 2020-09-28 상하이 아스코어 테크놀로지 컴퍼니 리미티드 레이저 소자
KR102631207B1 (ko) * 2022-10-14 2024-01-31 하나옵트로닉스 주식회사 공통 애노드 구조를 갖는 vcsel 및 vcsel 어레이

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128951A (en) * 1991-03-04 1992-07-07 Karpinski Arthur A Laser diode array and method of fabrication thereof
US20020031890A1 (en) * 2000-08-28 2002-03-14 Takayuki Watanabe Semiconductor device of STI structure and method of fabricating MOS transistors having consistent threshold voltages
KR100493148B1 (ko) 1998-12-31 2005-08-04 삼성전자주식회사 Gan계단파장면발광반도체레이저제작방법및그레이저장치
KR100627703B1 (ko) 2004-12-14 2006-09-26 한국전자통신연구원 하이브리드 금속접합 표면방출 레이저 및 그 제작 방법
US7388230B1 (en) * 2005-10-26 2008-06-17 Michael Lebby Selective colored light emitting diode
US7399124B2 (en) 2006-12-08 2008-07-15 Finisar Corporation VCSEL on silicon integrated circuit
US20090003401A1 (en) * 2007-06-29 2009-01-01 Canon Kabushiki Kaisha Surface emitting laser and method of manufacturing the same
US20110176567A1 (en) * 2009-02-17 2011-07-21 Trilumina Corporation Multibeam arrays of optoelectronic devices for high frequency operation
US8313962B2 (en) * 2008-05-22 2012-11-20 Connector Optics Llc Method for attaching optical components onto silicon-based integrated circuits

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128951A (en) * 1991-03-04 1992-07-07 Karpinski Arthur A Laser diode array and method of fabrication thereof
KR100493148B1 (ko) 1998-12-31 2005-08-04 삼성전자주식회사 Gan계단파장면발광반도체레이저제작방법및그레이저장치
US20020031890A1 (en) * 2000-08-28 2002-03-14 Takayuki Watanabe Semiconductor device of STI structure and method of fabricating MOS transistors having consistent threshold voltages
KR100627703B1 (ko) 2004-12-14 2006-09-26 한국전자통신연구원 하이브리드 금속접합 표면방출 레이저 및 그 제작 방법
US7388230B1 (en) * 2005-10-26 2008-06-17 Michael Lebby Selective colored light emitting diode
US7399124B2 (en) 2006-12-08 2008-07-15 Finisar Corporation VCSEL on silicon integrated circuit
US20090003401A1 (en) * 2007-06-29 2009-01-01 Canon Kabushiki Kaisha Surface emitting laser and method of manufacturing the same
US8313962B2 (en) * 2008-05-22 2012-11-20 Connector Optics Llc Method for attaching optical components onto silicon-based integrated circuits
US20110176567A1 (en) * 2009-02-17 2011-07-21 Trilumina Corporation Multibeam arrays of optoelectronic devices for high frequency operation

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
H. Fathollahnejad et al., "Vertical-cavity surface-emitting lasers integrated onto silicon substrates by PdGe contacts", Electronics Letters, Jul. 21, 1994, pp. 1235-1236, vol. 30, No. 15.
Y. Xiong et al., "Oxide-Defined GaAs Vertical-Cavity Surface-Emitting Lasers on Si Substrates", IEEE Photonics Technology Letters, Feb. 2000, pp. 110-112, vol. 12, No. 2. *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107265392A (zh) * 2016-04-01 2017-10-20 英飞凌科技股份有限公司 光发射器装置、光声气体传感器和用于形成光发射器装置的方法
US10955599B2 (en) 2016-04-01 2021-03-23 Infineon Technologies Ag Light emitter devices, photoacoustic gas sensors and methods for forming light emitter devices
US10389090B2 (en) 2017-11-21 2019-08-20 International Business Machines Corporation Lateral growth of edge-emitting lasers

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Publication number Publication date
KR102034740B1 (ko) 2019-10-22
US20140348194A1 (en) 2014-11-27
KR20130112841A (ko) 2013-10-14
KR20130062969A (ko) 2013-06-13

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