US8319334B2 - Embedded laminated device - Google Patents

Embedded laminated device Download PDF

Info

Publication number
US8319334B2
US8319334B2 US12/538,470 US53847009A US8319334B2 US 8319334 B2 US8319334 B2 US 8319334B2 US 53847009 A US53847009 A US 53847009A US 8319334 B2 US8319334 B2 US 8319334B2
Authority
US
United States
Prior art keywords
metal layer
layer
semiconductor chip
metal
laminate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US12/538,470
Other languages
English (en)
Other versions
US20110031611A1 (en
Inventor
Martin Standing
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to US12/538,470 priority Critical patent/US8319334B2/en
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STANDING, MARTIN
Priority to DE102010036915.2A priority patent/DE102010036915B4/de
Publication of US20110031611A1 publication Critical patent/US20110031611A1/en
Priority to US13/618,280 priority patent/US8759156B2/en
Application granted granted Critical
Publication of US8319334B2 publication Critical patent/US8319334B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09718—Clearance holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10643—Disc shaped leadless component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T436/00—Chemistry: analytical and immunological testing
    • Y10T436/18—Sulfur containing
    • Y10T436/182—Organic or sulfhydryl containing [e.g., mercaptan, hydrogen, sulfide, etc.]
    • Y10T436/184—Only hydrogen sulfide

Definitions

  • One aspect relates to electronic devices, and more particularly to the technique of embedding semiconductor components into a substrate such as e.g., into a printed circuit board.
  • Embedding semiconductor devices into a substrate has been realized as a promising technology for applications in which size, thickness and weight of electronic devices are sought to be minimized. Such requirements are often encountered in portable applications such as cell-phones, laptop PCs, palms, PDUs (Personal Digital Assistant) etc., and are also of relevance in other electronic applications such as power devices.
  • FIGS. 1A to 1D are sectional views illustrating an embodiment of a process flow for producing an embodiment of a laminate insert package.
  • FIG. 2 is a sectional view of a laminate insert package embedded in a layer stack substrate.
  • FIG. 3 is a sectional view of an embodiment of an electronic device including a laminate insert package embedded in a layer stack substrate.
  • FIGS. 4A to 4J are sectional views illustrating an embodiment of a process flow for producing an embodiment of a laminate insert package.
  • FIG. 5A to 5E are perspective views corresponding to FIGS. 4A to 4E , respectively.
  • FIG. 6 is a top plan view of an embodiment of a laminate insert package.
  • FIG. 7 is a bottom plan view of the embodiment of the laminate insert package as illustrated in FIG. 6 .
  • FIG. 8 is a partial plan view of the laminate insert package of FIGS. 6 and 7 showing the interior of the package at multiple partial section lines I-I to IV-IV.
  • FIG. 9 is a plan view of the laminate insert package as illustrated in FIGS. 6 to 8 when inserted into a layer stack substrate to form an electronic device according to an embodiment.
  • Coupled and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together; intervening elements may be provided between the “coupled” or “electrically coupled” elements.
  • the semiconductor chips described further below may be of different types, may be manufactured by different technologies and may include for example integrated electrical, electro-optical or electro-mechanical circuits and/or passives.
  • the semiconductor chips may, for example, be configured as power semiconductor chips, such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), power bipolar transistors or power diodes.
  • the semiconductor chips may include control circuits, microprocessors or micro-electromechanical components.
  • semiconductor chips having a vertical structure may be involved, that is to say that the semiconductor chips may be fabricated in such a way that electric currents can flow in a direction perpendicular to the main surfaces of the semiconductor chips.
  • a semiconductor chip having a vertical structure may have contact elements in one embodiment on its two main surfaces, that is to say on its front side and backside.
  • power semiconductor chips may have a vertical structure.
  • the source electrode and gate electrode of a power MOSFET may be situated on one main surface, while the drain electrode of the power MOSFET is arranged on the other main surface.
  • the devices described below may include integrated circuits to control the integrated circuits of other semiconductor chips, for example the integrated circuits of power semiconductor chips.
  • the semiconductor chips need not be manufactured from specific semiconductor material, for example Si, SiC, SiGe, GaAs, and, furthermore, may contain inorganic and/or organic materials that are not semiconductors, such as for example insulators, plastics or metals.
  • the semiconductor chips described herein may include contact elements or contact pads on one or more of their outer surfaces wherein the contact elements serve for electrically contacting the semiconductor chips or other circuits integrated in the semiconductor chip.
  • the contact elements may have the form of lands, i.e. flat contact layers on an outer surface of the semiconductor chip.
  • the contact elements may be situated on the active main surfaces of the semiconductor chips or on other surfaces of the semiconductor chips or on both surfaces.
  • One or more semiconductor chips are embedded in a laminate insert package.
  • Embodiments of the laminate insert package having a plurality of chips may use different types of chips such as e.g., the types mentioned above as well as integrated passives, passives etc.
  • the laminate insert package is embedded in a substrate including a layer stack to form an electronic device.
  • the layer stack may generally be made from a number of layers that are insulating or conductive, the latter are provided with a conductor track structure.
  • Embodiments of the substrate may include substrates of different type and configuration, in one embodiment PCBs (Printed Circuit Boards) and SBU (Sequential Build-Up) laminate substrates.
  • the laminate insert package may thus form a laterally confined “laminate-in-laminate” structure within a subregion of the substrate.
  • at least parts of the conductive metal layers of the layer stack may extend laterally outside the subregion to which the lateral extension of the laminate insert package is confined.
  • the number and positions of conducting and/or insulating layers of the laminate insert package must not correspond to the number and positions of adjacent conducting and/or insulating layers of the layer stack.
  • the electronic device may constitute a power supply containing one or more power MOSFETs or a motherboard of a computer etc.
  • layers or layer stacks are applied to one another or materials are applied or deposited onto layers.
  • any such terms as “applied” or “deposited” are meant to cover literally all kinds and techniques of applying layers onto each other.
  • they are meant to cover techniques in which layers are applied at once as a whole like, for example, laminating techniques as well as techniques in which layers are deposited in a sequential manner like, for example, printing, sputtering, plating, dispensing, molding, CVD (Chemical Vapor Deposition), etc.
  • the laminate insert package and the layer stack of the substrate include metal layers used as wiring layers to make electrical contact with the semiconductor chip.
  • the metal layers may be manufactured with any desired geometric shape and any desired material composition.
  • the metal layers may, for example, be composed of conductor tracks or wires, but may also be in the form of a layer covering an area. Any desired metal, for example copper, aluminum, nickel, palladium, silver, tin or gold, or metal alloy may be used as the material.
  • the metal layers need not be homogenous or manufactured from just one material, that is to say various compositions and concentrations of the materials contained in the metal layers are possible, and different metal layers may be of different materials.
  • FIGS. 1A-D illustrate processes of a first embodiment of a method of producing an insert package 100 intended for integration in a layer stack. It is to be noted that the stages of production illustrated in FIGS. 1A-D may be understood as simplifications since further layers such as dielectric layers, adhesive layers etc. may be used which are not depicted in these figures.
  • the process may start with a first metal layer or foil 101 which may be made of copper or any other appropriate conductive material.
  • the first metal foil 101 may be similar to that conventionally used to produce a PCB laminate.
  • the first metal foil 101 e.g., copper foil, may be finished with an optional organic coating (not illustrated) on the bottom surface 101 a and with an optional chemical preparation (not illustrated) on the top surface 101 b .
  • the chemical preparation may virtually consist of a chemical roughening of the top surface 101 b .
  • the first metal foil 101 is intended to provide a surface (namely top surface 101 b ) that will suit the requirements for connection of a die, i.e. may act similar to a leadframe. Further, as will be explained in greater detail in conjunction with FIG. 4B , the first metal foil 101 may optionally be coated with a dielectric layer (not illustrated) that may be printed selectively on the top surface 101 b of the first metal foil 104 .
  • a structured first insulating layer 103 is then applied to the top surface 101 b of the first metal foil 101 .
  • this first insulating layer 103 may e.g., be manufactured from pre-cut solid material such as e.g., a plastic structure with or without reinforcement or a prepreg structure, the structure having a window corresponding in size to the lateral dimensions of a semiconductor die or chip 102 to be applied.
  • prepreg layers are made of an uncured resin material that liquefies and then cures upon compression or lamination of the structure.
  • the first insulating layer 103 may be selectively printed using a screen, stencil or jet printing technique.
  • the printing image matches the perimeter of the semiconductor chip 102 .
  • the thickness of the first insulating layer 103 may be about the same as the thickness of the semiconductor chip 102 .
  • a die or semiconductor chip 102 is then bonded to the first metal foil 101 and thereby electrically connected thereto. Bonding may be accomplished by a variety of techniques such as gluing with a conductive adhesive, bonding with a low temperature conductive sintering material, soldering etc. As will be explained later in more detail by way of example, a metal (e.g., silver) particle filled epoxy or another conducting polymer may be used for fixing the semiconductor chip 102 to the first metal foil 101 . Such polymer may be applied in liquid form by a printing process such a screen printing, stencil printing or jet printing, or by a dispensing method.
  • first apply the semiconductor chip 102 and then to apply the structured first insulating layer 103 .
  • the above-mentioned chemical preparation of the top surface 101 b of the first metal foil 101 may depend on the constitution of the first insulating layer 103 and is designed to give good adhesion to the first insulating layer 103 .
  • a second metal foil 104 may be made of the same material and may be processed in the same manner as the first metal foil 101 .
  • a first surface 104 a of the second metal foil 104 may be finished with an organic coating (not illustrated) and a second surface 104 b of the second metal foil 104 may be subjected to a chemical preparation (not illustrated).
  • the second metal foil 104 may also be coated with a dielectric layer (not illustrated) that may be printed selectively on the second surface 104 b of the second metal foil 104 .
  • the semiconductor chip 102 is bonded to the second metal foil 104 rather than to the first metal foil 101 . All bonding methods as mentioned above may be applied.
  • the first metal foil 101 carries the first insulating layer 103 acting as a spacer and the second metal foil 104 carries the semiconductor chip 102 (or multiple semiconductor chips).
  • the two foil assemblies a brought together and integrated to form a compound structure by e.g., the use of a lamination press.
  • the lamination press (not illustrated) clamps the foil assemblies at e.g., a constant pressure within e.g., a vacuum environment.
  • the temperature within the lamination press may be profiled to create appropriate conditions for the resin to flow to a limited degree before the resin materials in the compound starts to cure.
  • a solid rigid laminated body is obtained in which the semiconductor chip 102 is sandwiched between two metal foils 101 , 104 and electrically contacted to these foils 101 , 104 .
  • a conducting adhesive is used as a bonding material between semiconductor chip 102 and metal foils 101 , 104 , the electrical contact to the semiconductor chip 102 may be generated by the lamination process.
  • the gate contact and the source contact may be contacted down on the first metal foil 101 and then the drain contact will be bonded to the second metal foil 104 .
  • other types of semiconductor chips forming vertical devices or semiconductor chips 102 which do not form vertical devices may be used.
  • the first and/or second metal foils 101 , 104 may be structured into the desired electrical conductor patterns.
  • the electrical conductor patterns extend laterally beyond the outline or perimeter of the semiconductor chip 102 and are provided in the semiconductor chip outside region with metal-free areas or openings 101 c and 104 c , respectively.
  • Opening 101 c is positioned opposite (in terms of a protection normal to the lamination plane) to a metal area of the electrical conductor pattern formed from the second metal foil 104 .
  • opening 104 c is positioned opposite (in terms of a protection normal to the lamination plane) to a metal area of the electrical conductor pattern formed from the first metal foil 101 .
  • the laminated body with patterned metal foils 101 , 104 will be referred to in the following as (laminated) insert package 100 .
  • a plurality of insert packages 100 may simultaneously be generated from a single laminate panel including a repetitive structure of insert packages 100 . In this case, all aforementioned processes are performed on laminate panel level.
  • the number of insert packages 100 in one laminate panel will depend on the overall laminate panel size and the size of the insert package 100 .
  • the size of the insert package 100 may depend on the number of semiconductor chips which are embedded in one insert package 100 (i.e. single chip as depicted by way of example in FIG. 1D or multi-chip as will be explained later).
  • the insert package 100 may either include number of semiconductor chips 102 and/or passives and at least a partial electrical interconnect structure or may simply include one semiconductor chip 102 and the terminals thereof.
  • the insert packages 100 may be tested within the laminate panel. After testing, the laminate panel may be singularized into single insert packages 100 by e.g., sawing or other dicing techniques.
  • the insert package 100 as illustrated in FIG. 1D , may then represent a final product which may be purchased by the customer and integrated into the PCB or SBU during the lamination process.
  • the insert package 100 may have a simple plate-type geometrical shape such as e.g., a polygon having two parallel, flat surfaces formed by the patterned first and second metal foils 101 , 104 .
  • the unembedded insert package 100 may fail to have any electrical couplings between the electrical conductor patterns formed from the first metal foil 101 and the electrical conductor patterns formed from the second metal foil 104 (except the semiconductor chip(s) 102 bonded between the first and second metal foils 101 , 104 ).
  • the insert package 100 may fail to have any through-holes or vias that electrically interconnect conductor structures or lands patterned from the first and second metal foils 101 , 104 .
  • FIG. 2 is a sectional view showing the laminate insert package 100 integrated into a layer stack substrate 200 .
  • the layer stack substrate 200 may be a PCB.
  • the laminate insert package 100 can easily be integrated into the PCB 200 because it can be treated as any other internal layer of the PCB 200 and only requires an aperture to be cut into an existing layer such as e.g., a prepreg layer (i.e. an uncured resin layer) or a core layer (i.e. a cured resin layer) of the PCB 200 to allow the insert package(s) 100 to be integrated in the PCB 200 lamination structure.
  • a prepreg layer i.e. an uncured resin layer
  • a core layer i.e. a cured resin layer
  • the PCB 200 may for instance be made of a first substrate insulating layer 201 , a first substrate metal layer 202 bonded to the first substrate insulating 201 , a second substrate insulating layer 203 and a second substrate metal layer 204 bonded to the second substrate insulating layer 203 .
  • the PCB 200 may include an embedding insulating layer 205 which is designed to have an aperture which matches with the lateral dimensions of the laminate insert package 100 .
  • the embedding insulating layer 205 may be made of known prepreg materials on the basis of epoxy, polyester or other plastic materials, for instance cotton paper reinforced epoxy, woven glass reinforced epoxy, matte glass reinforced polyester, woven glass reinforced polyester, etc.
  • Core layers made e.g., of fluoropolymer material such as e.g., polytetrafluoroethylene, aramid fibres or carbon fibres may also be used to serve as embedding insulating layer 205 .
  • the embedding insulating layer 205 may be the center insulating layer or may be one of the out-center insulating layers of the layer stack substrate 200 .
  • the insert package 100 may have a constant thickness over its lateral dimensions such that the thickness of the embedding insulating layer 205 may be designed to match with the thickness of the laminate insert package 100 .
  • the first and second substrate insulating layers 201 , 203 may for example be made of conventional interlayer dielectrics such as e.g., polytetrafluoroethylene or other appropriate materials.
  • the layer stack substrate (e.g., PCB) 200 is, by way of example, depicted to include only two substrate metal layers 202 , 204 .
  • the substrate metal layers 202 , 204 are outer (i.e. exposed) layers which may be structured after lamination of the layer stack substrate 200 .
  • the layer stack substrate (e.g., PCB) 200 may also be a multi-layer PCB type substrate. Multi-layer PCBs are formed by bonding together a plurality of substrate insulating layers (prepreg and core layers) and internally structured substrate metal layers bonded to the substrate insulating layers (typically to the core layers).
  • the layer stack substrate 200 embedding the laminate insert package 100 may be regarded as a laminate-in-laminate structure, in which the embedded laminate (i.e. the insert package laminate 100 ) is laterally confined to extend only in a subregion of the surface extent of the layer stack substrate 200 .
  • the layer stack substrate 200 embedding the insert package 100 may be regarded as an n-layer board (n is the number of full-area substrate metal layers 202 , 204 ) which, in a subregion, is provided with k additional metal layers 101 , 104 and one or more semiconductor chips 102 which are directly coupled (i.e. fixed) to some or all of these k additional metal layers.
  • the laminate insert package 100 may effectively transform the n-layer board 200 locally to an n+k layer board within a subregion where enhanced functionality is to be integrated.
  • substrate metal layers may be effected (i.e. cut out) by the integration of the laminate insert package 100 .
  • FIG. 3 illustrates an electronic device 300 made by electrically connecting the laminate insert package 100 to the layer stack substrate (e.g., PCB) 200 .
  • the design of the laminate insert package 100 and in one embodiment the location of the openings 101 c and 104 c of the first and second metal foils 101 , 104 , respectively, allows for electrically connecting the laminate insert package 100 by global vias 301 , 302 (i.e. through-connections running from one side of the layer stack substrate 200 to the other side of the layer stack substrate 200 ).
  • Global vias 301 , 302 (which completely penetrate the layer stack substrate 200 ) may be generated by laser-drilling or conventional drilling. The hole may then be made conductive by through hole plating.
  • these global vias are inexpensive compared to other types of vias as multiple layer stack substrates 200 can be drilled in a stack meaning that several layer stack substrates 200 can be drilled in a single operation.
  • the laminate insert package 100 is electrically connected to the layer stack substrate 200 exclusively by global vias 301 , 302 .
  • This does not necessarily exclude that blind vias (which connect an internal metal layer to an outer metal layer) or buried vias (which connect two internal metal layers) are provided in the electronic device 300 in other regions.
  • only global vias are used for interconnecting substrate metal layers 202 , 204 of the layer stack substrate 200 and for interconnecting the laminate insert package 100 to the layer stack substrate 200 .
  • the possibility to exclusively use global vias 301 , 302 for electrically connecting the insert package 100 is achieved by the specific design of the electrical conductor patterns of the first and second metal foils 101 , 104 of the laminate insert package 100 .
  • the layer stack substrate manufacturer who has to design the electronic device 300 and in one embodiment the global vias 301 , 302 , will work in collaboration with an insert package designer who is in charge of structuring the first and second metal foils 101 , 104 to electrical conductor patterns including the openings 101 c and 104 c , respectively, at the right places.
  • the global vias 301 , 302 when producing the global vias 301 , 302 , they are positioned to meet or intersect metal layers where a connection is required and to miss metal layers where no connection is desired. So whilst a global via 301 , 302 may go through a number of physically present metal layers, it is not necessarily connected to all of these layers. In this way, a part or all of the necessary electrical connections in the electronic device 300 may be made exclusively by global vias.
  • the substrate 300 may be an SBU laminate substrate.
  • An SBU laminate substrate may include a core that is similar to the design of a PCB 200 (with integrated insert package) as illustrated in FIG. 2 .
  • the core corresponding to PCB 200
  • build-up layers typically are formed by applying alternating dielectric films and metallizations to the core. These build-up layers may be formed by thin-film techniques such as lithography and etching and typically serve to provide additional rewiring structures to the PCB.
  • the insert package 100 is integrated in an SBU laminate substrate, again exclusively global vias may be used to electrically contact the laminate insert package 100 to the SBU laminate substrate.
  • the concept of integrating the laminate insert package 100 into a layer stack substrate does not prohibit the use of heat-sinks
  • the laminate insert package 100 may occupy a layer very close to the surface of the layer stack substrate. If a common node is chosen then the common node may be connected to one surface (e.g., first or second substrate metal layer 202 , 204 ) and a heat-sink can be soldered or directly connected to that surface without the need for electrical isolation. Further, thermal planes of relatively heavy weight copper may also be used as part of the electronic device 300 for the purpose of heat-sinking.
  • FIGS. 4A-4J illustrate stages of a method of producing an embodiment of a laminate insert package 400 . It is to be noted that the method illustrated in FIGS. 4A-4J is, to some extent, similar to but somewhat more detailed than the process flow described in conjunction with FIGS. 1A-1D . Thus, it is to be understood that details in the embodiment described below may be applied to the process flow of the embodiment illustrated in FIGS. 1A-1D and vice versa.
  • a first metal layer or foil 401 is provided ( FIG. 4A ).
  • the first metal foil 401 corresponds to the first metal foil 101 of the aforementioned embodiment.
  • a first dielectric layer 410 is applied to the top surface 401 b of the first metal foil 401 .
  • the first dielectric layer 410 may be selectively printed on the top surface 401 b by using a screen, stencil or jet printing method, or a dispensing process.
  • the top surface 401 b of the first metal foil 401 remains exposed.
  • the open area(s) 410 a within the first dielectric layer 410 may then be filled with a bonding material such as e.g., a conducting adhesive, bonding with low temperature sintering material or solder ( FIG. 4C ).
  • a bonding material such as e.g., a conducting adhesive, bonding with low temperature sintering material or solder ( FIG. 4C ).
  • a conducting adhesive 411 is applied.
  • the conducting adhesive 411 may be applied in the same manner as the first dielectric layer 410 , e.g., as a liquid by using printing or dispensing techniques.
  • the conducting adhesive 411 may, for instance, be made of a metal particle filled epoxy. It is possible to use B stage epoxy materials or similar multi-stage curing system adhesives. By way of example, polyimides, bismaleimides etc. could be used as adhesives. Further, by way of example, silver may be used for the metal particles.
  • the metal particle filled epoxy may be dried after the printing and may be solid at room
  • an insulating spacer layer 403 corresponding to the first insulating layer 103 in the aforementioned embodiment is applied on the first dielectric layer 410 .
  • the insulating spacer layer 403 is made and applied by any of the techniques described before, and reference is made to the corresponding description to avoid reiteration.
  • a semiconductor chip 102 is placed on the conducting adhesive 411 .
  • a polymer such as a resin which is solid at room temperature (after drying) means that the resin will become sticky at increased temperatures. Modestly increasing the temperature to e.g., about 80° C. will allow processes such as hot-bonding to be used to fix the semiconductor chip 102 to the first metal foil 401 .
  • Hot-bonding involves either the first metal foil 401 or the semiconductor chip 102 to be heated up to make the resin of the conducting adhesive 411 tacky at the area where the semiconductor chip 102 is to be bonded. Once the semiconductor chip 102 has been placed and the assembly is cool again, then the resin of the conducting adhesive 411 solidifies and the assembly can easily be handled again.
  • the final layer structure illustrated in FIG. 4I may be built up layer by layer from the bottom of the structure to the top.
  • FIGS. 4F-4H exemplify, by way of example, an alternative process flow.
  • a second metal foil 404 corresponding to the second metal foil 104 of the aforementioned embodiment is provided.
  • a second structured dielectric layer 412 is applied to a second surface 404 b (corresponding to second surface 104 b of the second metal foil 104 in the aforementioned embodiment) of the second metal foil 404 .
  • the structured second dielectric layer 412 may be selectively applied e.g., by printing or dispensing processes or may be applied over the full area and then appropriately etched to establish open areas 412 a , 412 b by conventional technologies.
  • the open areas 412 a and 412 b may then be filled by a bonding material such as e.g., a conducting adhesive 411 in the same way as described before in conjunction with FIG. 4C .
  • the pattern of the second dielectric layer 412 may correspond to the position(s) of die metal contact(s) on the semiconductor chip 102 .
  • the open area 412 a may correspond to the gate contact
  • the open area 412 b may correspond to the source contact
  • the open area 410 a of the first dielectric layer 410 may correspond to the drain contact of the semiconductor chip 102 .
  • the two assemblies are brought together and laminated in a lamination press (not illustrated).
  • the die metal contacts on the top side of the semiconductor chip 102 are mechanically and in an electrically conductive manner fixed to the second metal foil 404 by the conducting adhesive 411 in the open areas 412 a , 412 b of the second dielectric layer 412 .
  • FIG. 4J illustrates a patterning of the first and second metal foils 401 , 404 .
  • openings 401 c and 404 c are formed in the first and second metal foils 401 , 404 by appropriate structuring techniques including e.g., photolithography and etching. Patterning may be configured to provide for conductor tracks, die pads or other structures connected or disconnected to the semiconductor chip(s) 102 . In one embodiment, it is possible to produce insulated structures which are electrically disconnected from all other structures generated from the respective first or second metal foil 401 , 404 .
  • FIGS. 4A-4I are arranged in an extended laminate panel.
  • FIGS. 5A-5E are perspective view showing stages of production of such laminate panel.
  • FIG. 5A corresponds to FIG. 4A and illustrates the first metal foil 401 of the laminate panel.
  • FIG. 5B corresponds to FIG. 4B and illustrates the structured first dielectric layer 401 of the laminate panel including an array of open areas 410 a.
  • FIG. 5C corresponds to FIG. 4C and illustrates the open areas 410 a filled with the conducting adhesive 411 .
  • FIG. 5D corresponds to FIG. 4D and illustrates the laminate panel once the insulating spacer layer 403 is applied.
  • FIG. 5E corresponds to FIG. 4E and illustrates the laminate panel after mounting the semiconductor chips 102 on the first metal foil 401 .
  • the processes relating to the second metal foil 404 are accomplished analogously to FIGS. 5A-5C on laminate panel level.
  • the two laminate panels are then brought together and laminated in a lamination press to generate a laminated panel containing an array of the insert laminate structures as illustrated in FIG. 4I .
  • the laminate panel contains an array of 9 insert laminate structures each including one semiconductor chip 102 .
  • FIG. 6 illustrates a plan view of the top side of a laminate insert package 500 according to one embodiment.
  • the laminate insert package 500 implements a synchronous buck configuration which may e.g., be used as part of a voltage regulator or switch mode power supply circuit.
  • a five phase synchronous buck configuration is displayed, which is composed of five identical structures arranged in the form of a linear array.
  • each structure includes three semiconductor chips, namely two power MOSFETs arranged in a half-bridge configuration and one phase IC which controls the duty cycle of the structure under consideration.
  • the plan view of FIG. 6 illustrates a structured top metal foil 504 which corresponds to the second metal foils 104 and 404 of the previous embodiments.
  • foil area 504 a may represent the phase output node
  • foil areas 504 b may represent the input/output terminals of the phase IC
  • foil area 504 d may be connected to the gate contact of one of the MOSFETs.
  • many different designs of the pattern of the top metal foil 504 of the laminate insert package 500 are available.
  • FIG. 7 illustrates a structured bottom metal foil 501 of the laminate insert package 500 .
  • An isolated area 501 a forms a die pad to be connected to e.g., the drain contact of a first of the power MOSFETs.
  • the insular, isolated area 501 b may be electrically connected to the gate contact of the second power MOSFET.
  • FIGS. 6 and 7 further demonstrate where through-vias may be implemented to connect the first and second structured metal foils 501 , 504 to substrate metal foils after insertion and lamination of the laminate insert package 500 into a (e.g., customer's) layer stack substrate.
  • the intended positions of the vias are depicted by dots which are confined to openings 501 c and 504 c of the bottom and top metal foils 501 and 504 , respectively, which correspond to openings 401 c and 404 c of the respective metal foil 401 , 404 as illustrated in FIG. 4J . Note that the intended positions of all global vias penetrating the laminate insert package 500 may connect only to one of the metal foils 501 , 504 and not to the other.
  • FIG. 8 is a partial plan view of the laminate insert package 500 showing the interior of the package at multiple partial section lines I-I to IV-IV.
  • the configuration of the laminate insert package 500 corresponds to the buildup of the laminate insert package 400 .
  • the patterned top metal foil 504 can be seen.
  • This foil 504 is placed on a top dielectric layer 512 , which corresponds to the second dielectric layer 412 of the laminate insert package 400 .
  • the top metal foil 504 is cut down to the surface of the top dielectric layer 512 .
  • conducting adhesive 411 can be seen to fill an opening 512 a of the top dielectric layer 512 corresponding to opening 412 a of the laminate insert package 400 .
  • the top dielectric layer 512 is cut down to the surface of an insulating spacer layer 503 corresponding to the insulating spacer layer 403 of the laminate insert package 400 .
  • Semiconductor chips 102 showing die metal contacts 520 become apparent.
  • the insulating spacer layer 503 as well as the semiconductor chips 102 are cut down to the surface of a bottom dielectric layer 510 .
  • the bottom dielectric layer 510 corresponds to the first dielectric layer 410 of the laminate insert package 400 .
  • conducting adhesive 411 can be seen to fill open areas 510 a (corresponding to open areas 410 a ) of the bottom dielectric layer 510 .
  • the bottom dielectric layer 510 is cut down to the surface of the structured bottom metal foil 501 .
  • Lands of conducting adhesive 411 may be seen which are applied to areas where semiconductor chips (not illustrated in FIG. 9 ) are placed.
  • the thicknesses of the various insulating and conducting layers may cover a wide range.
  • the first or bottom metal foils 101 , 401 , 501 may have a thickness in the range between 30 to 80 ⁇ m
  • the first or bottom dielectric layer 410 , 510 may have a thickness of about 10 to 20 ⁇ m
  • the first insulating or spacer layer 103 , 403 , 503 may have the same thickness as the semiconductor chip 102 (e.g., tens to hundreds of micrometers)
  • the second or top dielectric layer 412 , 512 may have a thickness of about 10 to 20 ⁇ m
  • the second or top metal foil 104 , 404 , 504 may have a thickness in the same range as the first or bottom metal foil 101 , 401 , 501 .
  • FIG. 9 is a plan view showing the laminate insert package 500 of FIGS. 6 , 7 and 8 integrated into a layer stack substrate 600 which has not yet been finished. More specifically, FIG. 8 illustrates an embedding insulating layer 605 of the layer stack substrate 600 which is configured to accommodate the laminate insert package 500 (synchronous buck circuit) 500 illustrated in FIGS. 6 , 7 and 8 .
  • the embedding insulating layer 605 corresponds to embedding insulating layer 205 of the layer stack substrate 200 illustrated in FIG. 2 , and reference is made to the previous description to avoid reiteration.
  • the embedding insulating layer 605 may be used for other connectivity in the rest of its area.
  • a metal layer 606 attached to the surface of the embedding insulating layer 605 may have been structured into a desired electrical conductor pattern.
  • the patterned metal layer 606 that can be seen on the top of the embedding insulating layer 605 will, after lamination of the layer stack substrate 600 , form an internal substrate metal layer.
  • a top substrate insulating layer corresponding to the second substrate insulating layer 203 and a top substrate metal layer corresponding to the second substrate metal layer 204 of the layer stack substrate 200 are not yet applied to the semi-finished layer stack substrate 600 illustrated in FIG. 9 , and thus are not depicted in FIG. 9 .
  • These layers and possibly further insulating and conducting layers are added before the layer stack substrate forming the electronic device is completed.
  • embedding insulating layer 605 which accommodates the laminate insert package 500 may form part of a variety of different types of layer stack substrates such as e.g., double-sided or multi-layer PCB, SBU laminate structures, etc.
  • the electronic device (or circuit) which in this example is e.g., a part of a voltage regulator or switch mode power supply circuit, may be realized on the basis of a variety of different layer stack substrates.
  • the embedding insulating layer 605 itself may realize different structures in the various layer stack substrates, e.g., a core layer of a PCB (which is typically equipped with double-sided structured metal foils) or a prepreg layer of a PCB.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
US12/538,470 2009-08-10 2009-08-10 Embedded laminated device Active 2030-09-27 US8319334B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/538,470 US8319334B2 (en) 2009-08-10 2009-08-10 Embedded laminated device
DE102010036915.2A DE102010036915B4 (de) 2009-08-10 2010-08-09 Elektronikbauelement mit eingebetteter Halbleiterkomponente und Verfahren zur Herstellung desselben
US13/618,280 US8759156B2 (en) 2009-08-10 2012-09-14 Method of producing laminated device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/538,470 US8319334B2 (en) 2009-08-10 2009-08-10 Embedded laminated device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/618,280 Division US8759156B2 (en) 2009-08-10 2012-09-14 Method of producing laminated device

Publications (2)

Publication Number Publication Date
US20110031611A1 US20110031611A1 (en) 2011-02-10
US8319334B2 true US8319334B2 (en) 2012-11-27

Family

ID=43495619

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/538,470 Active 2030-09-27 US8319334B2 (en) 2009-08-10 2009-08-10 Embedded laminated device
US13/618,280 Active US8759156B2 (en) 2009-08-10 2012-09-14 Method of producing laminated device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/618,280 Active US8759156B2 (en) 2009-08-10 2012-09-14 Method of producing laminated device

Country Status (2)

Country Link
US (2) US8319334B2 (de)
DE (1) DE102010036915B4 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130011972A1 (en) * 2009-08-10 2013-01-10 Infineon Technologies Ag Method of producing laminated device
DE102015106151A1 (de) * 2015-04-22 2016-10-27 Infineon Technologies Ag Leiterplatte mit eingebettetem Leistungshalbleiterchip
US20170325327A1 (en) * 2016-04-07 2017-11-09 Massachusetts Institute Of Technology Printed circuit board for high power components
US20180308799A1 (en) * 2014-10-03 2018-10-25 Mc10, Inc. Flexible electronic circuits with embedded integrated circuit die and methods of making and using the same

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011006356A1 (de) * 2011-03-29 2012-10-04 Continental Automotive Gmbh Schaltungsträger mit eingebetteter Schaltungsplatine
US9576887B2 (en) 2012-10-18 2017-02-21 Infineon Technologies Americas Corp. Semiconductor package including conductive carrier coupled power switches
US9559047B2 (en) * 2012-10-18 2017-01-31 Infineon Technologies Austria Ag Passive component as thermal capacitance and heat sink
US9312231B2 (en) * 2013-10-31 2016-04-12 Freescale Semiconductor, Inc. Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process
KR20150079189A (ko) * 2013-12-31 2015-07-08 삼성전기주식회사 전자소자 내장 기판
US10064287B2 (en) * 2014-11-05 2018-08-28 Infineon Technologies Austria Ag System and method of providing a semiconductor carrier and redistribution structure
US10192846B2 (en) 2014-11-05 2019-01-29 Infineon Technologies Austria Ag Method of inserting an electronic component into a slot in a circuit board
US10553557B2 (en) 2014-11-05 2020-02-04 Infineon Technologies Austria Ag Electronic component, system and method
US10679965B2 (en) * 2015-02-04 2020-06-09 Zowie Technology Corporation Semiconductor package structure with preferred heat dissipating efficacy without formation of short circuit
DE102015113503A1 (de) * 2015-08-14 2017-02-16 Schweizer Electronic Ag Elektronisches Schaltelement und modular aufgebauter Stromrichter
US10206286B2 (en) * 2017-06-26 2019-02-12 Infineon Technologies Austria Ag Embedding into printed circuit board with drilling
DE102018104972B4 (de) * 2018-03-05 2022-06-23 Schweizer Electronic Ag Leiterplattenelement mit integriertem elektronischen Schaltelement, Stromrichter und Verfahren zum Herstellen eines Leiterplattenelements
WO2023213394A1 (en) * 2022-05-04 2023-11-09 Huawei Digital Power Technologies Co., Ltd. Multi-layer printed circuit board and method for its production

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0528001A1 (de) 1991-02-28 1993-02-24 Gen Electric Zusammenbauverfahren vom batch-typ fuer chippackungen.
US5426263A (en) * 1993-12-23 1995-06-20 Motorola, Inc. Electronic assembly having a double-sided leadless component
US20040188827A1 (en) * 2003-01-07 2004-09-30 Tomoko Akashi Semiconductor device and method of assembling the same
US20060060954A1 (en) 2003-04-11 2006-03-23 Georg Meyer-Berg Multichip module including a plurality of semiconductor chips, and printed circuit board including a plurality of components
US20070108585A1 (en) * 2005-11-10 2007-05-17 Mark Pavier Semiconductor package including a semiconductor die having redistributed pads
US20070132091A1 (en) 2005-12-09 2007-06-14 Chung-Lin Wu Thermal enhanced upper and dual heat sink exposed molded leadless package
DE102006005420A1 (de) 2006-02-03 2007-09-06 Infineon Technologies Ag Stapelbares Halbleiterbauteil und Verfahren zur Herstellung desselben
WO2007119877A1 (en) 2006-04-13 2007-10-25 Panasonic Corporation Circuit module and power line communication apparatus
US20070262430A1 (en) 2006-05-09 2007-11-15 Oki Electric Industry Co., Ltd. Electric component, method of producing the same, substrate with built-in electric component, and method of producing the same
US7473988B2 (en) 2005-09-01 2009-01-06 Ngk Spark Plug Co., Ltd Wiring board construction including embedded ceramic capacitors(s)
US20090041994A1 (en) 2005-07-04 2009-02-12 Ulrich Ockenfuss Multilayer Printed Circuit Board Structure Comprising an Integrated Electrical Component, and Production Method Therefor
DE102008035911A1 (de) 2007-08-10 2009-04-16 Infineon Technologies Ag Verfahren zum Herstellen eines integrierten Schaltungsmoduls
DE102008062498A1 (de) 2007-12-21 2009-07-23 Infineon Technologies Ag Elektronikbauelement und Verfahren
DE102009040557A1 (de) 2008-09-30 2010-05-27 Infineon Technologies Ag Bauelement mit zwei Montageoberflächen

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8319334B2 (en) 2009-08-10 2012-11-27 Infineon Technologies Ag Embedded laminated device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0528001A1 (de) 1991-02-28 1993-02-24 Gen Electric Zusammenbauverfahren vom batch-typ fuer chippackungen.
US5426263A (en) * 1993-12-23 1995-06-20 Motorola, Inc. Electronic assembly having a double-sided leadless component
US20040188827A1 (en) * 2003-01-07 2004-09-30 Tomoko Akashi Semiconductor device and method of assembling the same
US20060060954A1 (en) 2003-04-11 2006-03-23 Georg Meyer-Berg Multichip module including a plurality of semiconductor chips, and printed circuit board including a plurality of components
US20090041994A1 (en) 2005-07-04 2009-02-12 Ulrich Ockenfuss Multilayer Printed Circuit Board Structure Comprising an Integrated Electrical Component, and Production Method Therefor
US7473988B2 (en) 2005-09-01 2009-01-06 Ngk Spark Plug Co., Ltd Wiring board construction including embedded ceramic capacitors(s)
US20070108585A1 (en) * 2005-11-10 2007-05-17 Mark Pavier Semiconductor package including a semiconductor die having redistributed pads
US20070132091A1 (en) 2005-12-09 2007-06-14 Chung-Lin Wu Thermal enhanced upper and dual heat sink exposed molded leadless package
DE102006005420A1 (de) 2006-02-03 2007-09-06 Infineon Technologies Ag Stapelbares Halbleiterbauteil und Verfahren zur Herstellung desselben
US20080123302A1 (en) 2006-04-13 2008-05-29 Matsushita Electric Industrial Co., Ltd. Circuit module and power line communication apparatus
WO2007119877A1 (en) 2006-04-13 2007-10-25 Panasonic Corporation Circuit module and power line communication apparatus
US20070262430A1 (en) 2006-05-09 2007-11-15 Oki Electric Industry Co., Ltd. Electric component, method of producing the same, substrate with built-in electric component, and method of producing the same
DE102008035911A1 (de) 2007-08-10 2009-04-16 Infineon Technologies Ag Verfahren zum Herstellen eines integrierten Schaltungsmoduls
DE102008062498A1 (de) 2007-12-21 2009-07-23 Infineon Technologies Ag Elektronikbauelement und Verfahren
DE102009040557A1 (de) 2008-09-30 2010-05-27 Infineon Technologies Ag Bauelement mit zwei Montageoberflächen

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"Embedded Die Technology, Next Generation Packaging for Discrete Semiconductors", Wil Peels, et al., NXP Semiconductors pp. 5 (Oct. 8, 2008).

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130011972A1 (en) * 2009-08-10 2013-01-10 Infineon Technologies Ag Method of producing laminated device
US8759156B2 (en) * 2009-08-10 2014-06-24 Infineon Technologies Ag Method of producing laminated device
US20180308799A1 (en) * 2014-10-03 2018-10-25 Mc10, Inc. Flexible electronic circuits with embedded integrated circuit die and methods of making and using the same
DE102015106151A1 (de) * 2015-04-22 2016-10-27 Infineon Technologies Ag Leiterplatte mit eingebettetem Leistungshalbleiterchip
US10062671B2 (en) 2015-04-22 2018-08-28 Infineon Technologies Ag Circuit board embedding a power semiconductor chip
DE102015106151B4 (de) 2015-04-22 2019-07-11 Infineon Technologies Ag Leiterplatte mit eingebettetem Leistungshalbleiterchip
US20170325327A1 (en) * 2016-04-07 2017-11-09 Massachusetts Institute Of Technology Printed circuit board for high power components

Also Published As

Publication number Publication date
DE102010036915A1 (de) 2011-02-24
US20110031611A1 (en) 2011-02-10
DE102010036915B4 (de) 2014-10-23
US20130011972A1 (en) 2013-01-10
US8759156B2 (en) 2014-06-24

Similar Documents

Publication Publication Date Title
US8319334B2 (en) Embedded laminated device
US8664043B2 (en) Method of manufacturing a laminate electronic device including separating a carrier into a plurality of parts
US8698298B2 (en) Laminate electronic device
US9681558B2 (en) Module with integrated power electronic circuitry and logic circuitry
US10186477B2 (en) Power overlay structure and method of making same
KR102332362B1 (ko) 초박형 임베디드 반도체 소자 패키지 및 그 제조 방법
US20170263539A1 (en) Power overlay structure and method of making same
KR102295990B1 (ko) 임베딩된 반도체 디바이스 패키지 및 그 제조 방법
US9070568B2 (en) Chip package with embedded passive component
US9190389B2 (en) Chip package with passives
US11309277B2 (en) Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate
JP2013243345A (ja) 超薄埋設ダイモジュール及びその製造方法
US10332832B2 (en) Method of manufacturing an electronics package using device-last or device-almost last placement
JP2006521686A (ja) 基板における電気的な構成素子から成る装置および該装置を製造する方法
TW201725946A (zh) 零件內建基板及零件內建基板的製造方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: INFINEON TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STANDING, MARTIN;REEL/FRAME:023072/0955

Effective date: 20090807

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12