US8060727B2 - Microprogrammed processor having mutiple processor cores using time-shared access to a microprogram control store - Google Patents

Microprogrammed processor having mutiple processor cores using time-shared access to a microprogram control store Download PDF

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US8060727B2
US8060727B2 US12/143,075 US14307508A US8060727B2 US 8060727 B2 US8060727 B2 US 8060727B2 US 14307508 A US14307508 A US 14307508A US 8060727 B2 US8060727 B2 US 8060727B2
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processor
processor cores
microprogrammed
control store
microprogram
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Stefan Blixt
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IMSYS AB
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Conemtech AB
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

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  • the invention generally relates to a microprogrammed processor, a computer system comprising such a processor as well as a method of operating a microprogrammed processor.
  • a processor executes a program.
  • a program includes instructions, which are stored as a sequence of bytes in a memory.
  • An instruction also called a machine instruction or macroinstruction, can (in the general case) consist of one or several bytes, and contains an opcode field defining its basic function, e.g. an arithmetic operation or a conditional jump in the execution sequence (instead of continuing to the next instruction).
  • the instruction may contain other fields that may specify one or more operands.
  • the program sequence of instructions in the memory
  • a processor may be built as an integrated circuit, which is then called a microprocessor.
  • peripherals can contain electromechanics (e.g. a printer or hard disk), but some can be purely electronic. They all have digital control electronics for interfacing with the processor, and usually also for their internal control.
  • a processor core is a digital device that can perform different sets of actions for each cycle of a high-frequency clock signal.
  • the processor core typically includes two main parts, or units. One is the execution unit, where data can be taken in (from memory or peripherals), operated on, temporarily stored in registers, and/or output (to memory or peripherals).
  • the other part is the control unit, which, for every cycle of the clock, controls the actions of the execution unit and itself, based on the state reached in the previous cycle.
  • control signals created by the control unit can be generated by digital gates that sense the contents of the instruction register, the sequence counter (assuming the processor has multi-cycle instructions), and other registers and flip-flops that define the machine state in the current clock cycle.
  • microinstructions also referred to as microinstructions. These can be thought of as words consisting of bits or bit fields, each representing control signals as defined by their positions in the word, and each word specifying the respective signal levels to be produced during the current clock cycle.
  • the technique is similar to that used in jacquard looms, player pianos, and pegged drum controllers for old washing machines or music boxes (also used in clock chiming mechanisms from the 14th century).
  • Each microinstruction corresponds to a line of holes in the paper roll for a player piano, and all the lines of holes on the paper roll together correspond to a micro program stored in a control store, or micro program memory.
  • This special (wide and fast) memory internal to the control unit of the processor core, outputs a microinstruction for every clock cycle.
  • the microinstruction sequence can contain jumps, i.e. control does not always pass from one microinstruction to the next one in the stored sequence.
  • the processor core has the control logic needed to execute the microinstructions, e.g. to generate the direct control signals to select sources of data, select operation of the arithmetic unit, select destinations for data, increment/decrement counters, and select or calculate the next microprogram address.
  • This level usually treats the instructions of the program as data, which it, under microprogram control, brings into the execution unit and operates on.
  • the execution unit then also comprises a resource for calculating the next microprogram address.
  • the microcode In the beginning of the execution of a program instruction, the microcode normally analyzes the operation code of the instruction and creates a microprogram address to the start of the execution microcode sequence for that opcode. It then computes the next microprogram address using a counter for stepping ahead in the sequence and typically a multiplexor to select other alternatives, i.e. doing jumps in the microprogram.
  • microinstruction register which stores the microinstruction, i.e. the output from the control store.
  • the microprogram is normally contained in a special microprogram memory, referred to as the control store, in the control unit of the processor core (and not in the main memory where the application program is stored).
  • the microprogram controls the details of the processor core as it controls the execution hardware to first fetch a machine instruction from the application program in the main memory and then execute this instruction by performing arithmetic/logic or other operations and determining the next program address, as specified by the microprogram.
  • microprogrammed processors represent a significant advance in processor technology, especially by allowing higher complexity of operation and thereby increased overall flexibility and efficiency, there is still a general demand, especially in embedded systems, for processors that are even more efficient, e.g. with lower cost and lower power consumption, through higher program density, more efficient use of hardware resources, and/or higher flexibility for different kinds of special operations.
  • a basic idea of the present invention is to provide a novel microprogrammed processor by combining two or more processor cores in such a way that the processor cores can share the special microprogram memory resource that is located deep inside the processor architecture.
  • the novel microprogrammed processor basically comprises at least two processor cores, and a common internal microprogram control store including microcode instructions for controlling at least the internal standard operation of the multiple processor cores, and suitable means for providing time-shared access to the microprogram control store by the processor cores.
  • execution units of the multiple processor cores and the common microprogram control store are provided on the same integrated circuit (IC) chip, effectively providing a truly unique microprogrammed multi-core microprocessor using a common/shared microprogram control store.
  • IC integrated circuit
  • FIG. 1 is a schematic diagram illustrating the basic schematics of a novel processor architecture according to an exemplary embodiment of the invention.
  • FIG. 2 is a schematic diagram illustrating a computer system based on a microprogrammed multi-core processor using a shared control store according to a preferred exemplary embodiment of the invention.
  • FIG. 3 is a schematic diagram illustrating an example of how the microprogram control store is switched between two processor cores.
  • FIG. 4 is a schematic diagram illustrating a computer system based on a microprogrammed multi-core processor using a shared control store according to a preferred exemplary embodiment of the invention.
  • FIG. 5 is a schematic diagram illustrating a particular implementation example of a computer system of the present invention in the specific form of a microcontroller.
  • FIG. 6 is a schematic flow diagram illustrating a method of operating a microprogrammed processor according to an exemplary embodiment of the invention.
  • the invention relates to a microprogrammed processor 100 , preferably also built as a microprocessor, having two or more processor cores (P 1 , P 2 ) 10 - 1 , 10 - 2 .
  • Each of the cores has an execution unit (i.e. resources or sets of resources such as arithmetic/logic units and associated registers) and a microprogram-controlled control unit, but instead of having their own microprogram memories the control units of the cores time-share a common microprogram memory 20 , also referred to as the control store.
  • the control store may for example be a RAM core or ROM core or a programmable ROM core such as flash memory, or any combination of these (two or more memory cores, each covering a part of the address range), comprising microinstructions for the control of the execution units.
  • the execution units and memory cores are preferably all on the same integrated circuit chip to provide a microprogrammed multi-core processor in microprocessor implementation.
  • Microprogramming i.e. the use of an internal control store with microinstructions controlling the internal operation of a processor, can be useful in embedded systems having their software based on “virtual machines” and/or using demanding algorithms that do not execute efficiently on common standard processors, i.e. simple microcontrollers, RISC (Reduced Instruction Set Computer) processors, or DSP (Digital Signal Processor) processors.
  • Microprogramming is used in traditional CISC (Complex Instruction Set Computer) processors, but those normally have a limited traditional instruction set, “frozen” for further development due to the backwards software compatibility requirements, and these microprograms are normally small and stored in ROM.
  • the instruction sets of CISC machines are usually old and not well suited for modern compilers.
  • microprogramming can be used for other instruction sets, such as the “byte code” of the Java Virtual Machine. This was designed to fit a compiler. Other virtual machines have also been defined, and such “virtualization” is of increasing importance.
  • Microprogramming can also be used for increasing the efficiency (increasing speed and/or reducing power consumption) of the execution of important algorithms, such as cryptography, graphics, audio and video processing, radio baseband processing, data compression/decompression, and Java garbage collection.
  • important algorithms such as cryptography, graphics, audio and video processing, radio baseband processing, data compression/decompression, and Java garbage collection.
  • a microcode-programmed (i.e. a microprogrammed) processor is a processor in which the general standard operation of the processor is controlled by sequences of microcode words in the internal micro program memory (i.e. the control store).
  • the internal micro program memory i.e. the control store.
  • microprocessor which simply means that the processor is built as an integrated circuit.
  • a microcode-programmed processor may also be built as an integrated circuit, but a microprocessor is not by definition equipped with a micro program for controlling its internal operation.
  • processors with execution units optimized for signal processing, for graphics, or for Java, but these optimizations are different for the different purposes and difficult to combine in an economic design.
  • the use of microprogramming can make possible a processor design with sufficient performance on all these different types of processing, using relatively simple general-purpose execution units without adding special optimization hardware.
  • Such a design will need a larger control store than that of a typical CISC.
  • the execution unit can often be simpler, because of the high speed of modern IC technology, the characteristics of performance requirement for embedded systems as compared to computers (“good enough” instead of “as fast as possible”), and the increased “intelligence” offered by sophisticated microprogrammed control.
  • the execution unit(s) of a processor core may be built from combinatorial logic gates, flip-flops, and perhaps a register set in some kind of RAM core.
  • the operation of the unit is controlled by a microprogram in a similar (but often larger) on-chip memory, the microprogram memory (i.e. control store), which e.g. can be of read/write type (RAM) or read-only (ROM) or a combination of both.
  • the microprogram memory i.e. control store
  • RAM read/write type
  • ROM read-only
  • the longest path delays through the combinatorial logic are about twice as long as the minimum cycle time of the internal memory cores.
  • the microinstruction cycle is divided in two halves and the logic can do one read plus one write access, in sequence, in the internal memory cores during one microinstruction cycle.
  • the microprogram memory is a relatively expensive resource.
  • a basic idea of the invention is to combine two (or more) processor cores, exemplified by P 1 and P 2 in FIG. 1 , in such a way that the execution units of the cores can share this resource.
  • FIG. 2 is a schematic diagram illustrating a computer system based on a microprogrammed multi-core processor using a shared control store according to a preferred exemplary embodiment of the invention.
  • the computer system 200 basically comprises a microprogrammed processor 100 , and input/output (I/O) unit 110 and a main memory 120 .
  • the microprogrammed processor 100 includes a number, N, of processor cores 10 - 1 , 10 - 2 , . . . , 10 -N, also denoted P 1 to PN, an internal common microprogram memory 20 and a time-shared access control unit 30 for generating suitable control signals for controlling access to the microprogram memory 20 .
  • the number, N, of processor cores is generally an integer equal to or greater than 2.
  • the common internal microprogram memory 20 i.e. the control store, includes microcode instructions (arranged as one or more micro programs) for controlling at least the internal standard operation of the processor cores.
  • the time-shared access control unit 30 is configured for providing time-shared access to the microprogram control store 20 by all or a subset of the processor cores.
  • each of the processor cores has at least one internal execution unit for executing microcode instructions from the common microprogram control store, and the execution units thus effectively share the common microprogram control store.
  • the clocks for the two or more processor cores are generated such that their microinstruction cycles are out of phase.
  • each one of them preferably starts its microinstruction cycle when the other core is halfway through its cycle.
  • the clock frequency is then generally equal to (or not much longer than) twice the minimum allowable cycle time for the memory cores used in the microprogram memory, and this memory is accessed at twice the microprogram frequency. There is usually no need for writing in the microprogram memory during normal operation; only one access is needed per microinstruction.
  • the first line shows an example of how the microprogram memory is switched between two processor cores P 1 and P 2 .
  • the two lines below show the microinstruction execution in P 1 and P 2 at the same time. Normally, one of the processor cores reads a micro instruction, which is then executed while the other processor core reads its next micro instruction.
  • the time-sharing of the control store is done on a regular basis, there is normally no competition, no request/acknowledge signaling, no arbitration.
  • the execution units will normally not need to wait for each other and they could be used for completely independent tasks.
  • microprogram memory i.e. control store
  • microcode instruction from the internal microprogram memory (i.e. control store)
  • Each core reads a microcode instruction from the microprogram memory and then executes the microcode instruction. While one processor core executes a microcode instruction, another processor core may access the microprogram memory and read another microcode instruction.
  • the separate processor cores may thus execute completely different microprogram tasks, even different microprograms, independently of each other. It should be emphasized that this is not about sharing a primary memory between processors, but rather a special way of sharing the control store resource of the control unit of a micro-programmed processor having multiple cores.
  • one of the cores/execution units is, in a preferred exemplary embodiment, stopped/put on hold and its control store cycle time slots used for writing in the control store, using the other core/execution unit.
  • the reading from the control store takes one clock cycle.
  • the address is applied at the beginning of the cycle and the corresponding microinstruction word is loaded into the above-mentioned register, the microinstruction register, at the end of the same cycle.
  • the execution of the microinstruction requires at least two clock cycles, during which time the contents of the microinstruction register is unchanged and available to the execution unit, which it directly controls: the control signals inside the execution unit are derived from the microinstruction bits and the phase, i.e. a signal indicating whether the cycle is the first or the second execution cycle.
  • the execution may require additional cycles, but the execution unit must then store parts of the microinstruction or derived signals, since the microinstruction register will be loaded with the next microinstruction. Furthermore, in this case the execution unit must be able to handle overlapping microinstructions—the third phase must be executed simultaneously with the first phase of the next microinstruction.
  • FIG. 4 illustrates an example of a preferred implementation of the invention.
  • the computer system includes two (or more) processor cores 10 - 1 , 10 - 2 (P 1 and P 2 ), a common control store 20 shared by P 1 and P 2 , flip-flop circuitry 30 (FF) and an associated inverter 32 , an address multiplexor 40 , and I/O units 110 as well as main memory 120 for the processor cores, and an optional common channel unit 130 .
  • each processor core 10 has its own micro instruction register 14 , and naturally also its own execution unit(s) 12 .
  • each processor core 10 is connected to its own dedicated I/O unit(s) 110 and main memory 120 . Double-lines generally indicate parallel signals.
  • P 1 and P 2 are not necessarily identical, although a compatible design can provide more benefit, if it means that they can share significant portions of the microprogram. If they have different types of work, e.g. P 1 is mostly free and can respond quickly to external events by executing short but time-critical sequences, while P 2 executes the big and complex but less time-critical work, perhaps a Java Virtual Machine, requiring a lengthy “garbage collection” routine that must not be disturbed, then P 1 may have just a small main memory and all the I/O interfaces, while P 2 has a big main memory containing most of the program code and data set.
  • P 1 may have just a small main memory and all the I/O interfaces
  • P 2 has a big main memory containing most of the program code and data set.
  • the parts are able to exchange data.
  • an optional “Channel” block has been included.
  • This channel is an I/O unit for both P 1 and P 2 . If the execution units of P 1 and P 2 contain DMA (direct memory access) logic, then the Channel can be very simple. It may have a register for data from P 1 to P 2 . It will generate a “request” signal to P 1 when the register is empty and an “available” signal to P 2 when it has data. Transfer in the other direction would be similar, using another register.
  • a similar simple mechanism can be used with programmed I/O over general purpose I/O (GPIO) ports if fast transfer is not needed.
  • GPIO general purpose I/O
  • Such a simple mechanism may also be used, for auxiliary control signaling, together with (in addition to) the DMA transfer alternatives described here.
  • the Channel needs to have more storage. This could be in the form of a shared random access memory, or a FIFO buffer in each direction.
  • the execution units have multi-channel DMA units with buffer memories, and DMA transfer can use an 8-bit I/O extension bus.
  • Programmed I/O input/output directly controlled by the microcode and thus not using DMA
  • P 1 can use programmed I/O to write or read data to/from the main memory of P 2 through one of P 2 's DMA channels
  • P 2 can write or read data to/from the main memory of P 1 through one of P 1 's DMA channels.
  • P 1 can use programmed I/O to write or read data to/from the main memory of P 2 through one of P 2 's DMA channels, and P 2 can write or read data to/from the main memory of P 1 through one of P 1 's DMA channels.
  • P 1 can use programmed I/O to write or read data to/from the main memory of P 2 through one of P 2 's DMA channels
  • P 2 can write or read data to/from the main memory of P 1 through one of P 1 's DMA channels.
  • FIG. 5 is a schematic diagram illustrating a particular implementation example of a computer system of the present invention in the specific form of a microcontroller.
  • the processor 100 is also built as an integrated circuit (IC), and the I/O units and main memory 120 are preferably added on the same IC chip to form a microcontroller system 200 .
  • the microprogrammed multi-core processor 100 may then be referred to as the overall processor core of the microcontroller 200 .
  • the execution units 12 of the processor cores 10 may share portions of a microprogram in the control store 20 , while further being used for executing different microprogram tasks independently of each other.
  • the control store 20 may include a shared microprogram or part thereof, especially for standard processor control operation, while also containing parts dedicated for other microprogram tasks.
  • FIG. 6 is a schematic flow diagram illustrating a method of operating a microprogrammed processor according to an exemplary embodiment of the invention.
  • a common microprogram control store is provided, including microcode instructions for controlling at least the internal standard operation of the processor cores.
  • access to the common microprogram control store by the processor cores is provided on time-shared basis to enable the cores to execute microcode instructions independently of each other.
  • clock signals or equivalent control signals are generated for the processor cores such that the microinstruction cycles of the processor cores are executed out of phase.

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