US7436701B2 - Single poly EPROM device with double control gates to prevent unintentionally charging/discharging - Google Patents

Single poly EPROM device with double control gates to prevent unintentionally charging/discharging Download PDF

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US7436701B2
US7436701B2 US11/314,587 US31458705A US7436701B2 US 7436701 B2 US7436701 B2 US 7436701B2 US 31458705 A US31458705 A US 31458705A US 7436701 B2 US7436701 B2 US 7436701B2
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gate
floating gate
single poly
poly eprom
control
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US20060133151A1 (en
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Ralph Oberhuber
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Texas Instruments Inc
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Texas Instruments Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • EPROM electronically programmable read-only memory.
  • an EPROM comprises a memory, which retains information, even if the power supply to the memory is switched off.
  • the EPROM device commonly comprises a field effect transistor having a source, a drain and a conduction channel between the source and drain. Additionally, the field effect transistor has a gate floating above channel. The floating gate is electrically isolated. Information is stored by injecting charges on the floating gate. Due to its isolation, the charges remain on the floating gate, even if the power supply is switched off. The charges on the floating gate effect the conductance channel between the source and the drain of the field effect transistor. The information may be retrieved from the memory device by measuring the current flowing between the source and the drain.
  • FIG. 1 A top view of a more advanced EPROM device, called a Single Poly EPROM device, is shown in FIG. 1 .
  • the Single Poly EPROM device of FIG. 1 comprises a floating gate 10 , a control gate 12 , a source 16 and a drain 18 .
  • Source 16 , drain 18 and floating gate 10 form a field effect transistor, wherein the floating gate 10 represents the gate of the field effect transistor.
  • the channel between source 16 and drain 18 is covered by a part of the floating gate 10 in FIG. 1 .
  • a back gate contact 14 b , a drain contact 14 D and a source contact 14 S are connected to a back gate 10 , the source 18 and the drain 16 , respectively.
  • control gate 12 is not formed by a conductive layer on top of the floating gate 10 , but by a doped semiconductor region underlying part of the floating gate 10 .
  • the floating gate 10 is made out of a poly-silicon layer on top of both the channel of the field effect transistor and the control gate 12 .
  • Two control gate contacts 14 C are connected to the control gate 12 (although a simple control gate is sufficient for functionality).
  • FIG. 2 shows a schematic cross section of the Single Poly EPROM device of FIG. 1 .
  • the floating gate 10 is situated above both the control gate 12 and the channel between source 16 and drain 18 .
  • a back gate 20 shown in FIG. 2 has the same purpose as in standard MOS transistors.
  • Reference sign C 1 depicts the capacitance between the floating gate 10 and the control gate 12 of the Single Poly EPROM device shown in FIG. 2 .
  • Single Poly EPROM devices can be programmed either through hot carrier injection or Fowler-Nordheim tunneling.
  • a thin gate oxide is provided as isolator between the floating gate 10 and the channel region. The channel region can be used for tunneling between the floating gate 10 and source 16 /drain 18 .
  • FIG. 3 illustrates the configuration of a conventional memory array consisting of Single Poly EPROM devices 32 and select transistors 30 .
  • One Single Poly EPROM device 32 connected to a selected transistor 30 forms a memory cell in the array.
  • the memory cells are grouped in columns Coll, Colt and rows ROW 1 , ROW 2 .
  • the select transistor 30 is a high voltage transistor, which is connected to the Single Poly EPROM device in order to protect the floating gate 10 against the high programming voltage. Otherwise, a high voltage applied to the drain 18 of the Single Poly EPROM device 32 during erasing would also appear at the drain 18 of the other unselected cells in the same memory column COL 1 , COL 2 . Consequently, the memory cell must consist of two transistors 30 and 32 as shown in FIG. 3 .
  • This select transistor 30 is needed to prevent programming if the transistor is not selected. If each Single Poly EPROM cell has to be programmable individually, then each Single Poly EPROM cell has to contain one select transistor 30 . Therefore, the total area of the array is significantly increased by the high voltage select transistors 30 .
  • the Single Poly EPROM device according to the invention does not need a dedicated select transistor for protecting its drain. Therefore, less area is needed in a memory array comprising the Single Poly EPROM devices according to the invention.
  • the Single poly EPROM device comprises a floating gate, a control gate, a source and a drain.
  • the control gate is positioned laterally of a channel between the source and the drain.
  • the floating gate is positioned above both the channel and the control gate.
  • An additional gate is provided above the floating gate.
  • a control is connected to the additional gate for controlling a voltage at the floating gate in order to prevent that the floating gate is unintentionally charged or discharged.
  • the floating gate voltage may be influenced by the voltage at the additional gate. Consequently, the voltage drop between the floating gate and the source or drain of the Single Poly EPROM device may be controlled in such a way, that the floating gate is not unintentionally charged or discharged. Therefore, the Single Poly EPROM device does not need a select transistor.
  • the control comprises a tri-state buffer having a buffer output connected to the additional gate.
  • the tri-state buffer comprises a buffer input and a select input for selectively passing the buffer input to the buffer output.
  • the tri-state buffer works as a buffer when a select signal is applied so that the input signal is transferred to the buffer output. Otherwise, the tri-state buffer output is floating.
  • Plural Single Poly EPROM devices may be connected to a single tri-state buffer output in order to prevent unintentional programming or erasing.
  • the programming of a Single Poly EPROM device is carried out by disconnecting the buffer output from the buffer input of the tri-state buffer, and applying a programming voltage to the control gate so that the floating gate is charged or discharged.
  • the drain terminal is connected to ground.
  • the buffer output and consequently the additional gate are floating. In this state, the voltage drop between the control gate and the floating gate is equal to the programming voltage multiplied by a coupling ratio.
  • the additional gate has virtually no effect on the coupling ratio.
  • the Single Poly EPROM device is programmed by the Fowler-Nordheim tunneling effect. This effect allows electrons to pass through the insulator between the floating gate and the channel, although their energy is too low to surmount the energy barrier.
  • the Single Poly EPROM device may be erased by applying the programming voltage to the drain and connecting the control gate to ground.
  • Unintentionally programming or erasing of the Single Poly EPROM device according to the invention may be prevented by passing the buffer input to the buffer output of the tri-state buffer and applying a predetermined voltage to the buffer input.
  • the buffer input may be connected to ground potential. Consequently, the voltage drop between the control gate and the additional gate is equal to the programming voltage.
  • the floating gate is connected in series to the additional gate and the control gate. The voltage at the floating gate lies between ground voltage and the programming voltage. The voltage drop between the drain and the floating gate is too small to allow Fowler-Nordheim tunneling.
  • the Single Poly EPROM devices according to the present invention are used as memory cells in a semiconductor memory.
  • Plural rows of Single Poly EPROM devices may be provided in the semiconductor memory device.
  • the additional gates of each Single Poly EPROM device situated in one row may all be connected in parallel to the buffer output of a single tri-state buffer. Therefore, each Single Poly EPROM device in a row may be protected from unintentional programming or erasing by appropriately controlling the tri-state buffer connected to the Single Poly EPROM devices in one row.
  • a significant area reduction can be achieved in this way, since only one tri-state buffer for each row is required in contrast to the conventional architecture, where one high voltage select transistor is required for each memory cell.
  • FIG. 1 shows a schematic top view of a conventional Single Poly EPROM device.
  • FIG. 2 shows a schematic cross section of the Single Poly EPROM device shown in FIG. 1 .
  • FIG. 3 shows illustrates schematically the configuration of a conventional semiconductor memory comprising conventional Single Poly EPROM devices.
  • FIG. 4 shows a schematic top view of a Single Poly EPROM device according to the embodiment of the present invention.
  • FIG. 5 shows a schematic cross section of the Single Poly EPROM device according to the embodiment shown in FIG. 4 .
  • FIG. 6 illustrates schematically the configuration of a semiconductor memory comprising plural rows of Single Poly EPROM devices according to the embodiment of the present invention.
  • the Single Poly EPROM device comprises an additional gate 40 , a floating gate 10 and a control gate 12 .
  • a section of the floating gate 10 is positioned between the additional gate 40 and the control gate 12 .
  • this section of the floating gate 10 is sandwiched between the control gate 12 and the additional gate 40 .
  • Both the additional gate 40 and the control gate 12 have contacts, namely an additional gate contact 14 A and a drain contact 14 C, whereas the floating gate 10 is completely isolated.
  • the Single Poly EPROM device of FIG. 4 comprises a source 16 and a drain 18 .
  • a channel between source 16 and drain 18 is covered by a section of the floating gate 10 . Therefore, the floating gate 10 controls the conductivity of the channel.
  • the floating gate 10 , the drain 18 and the source 16 comprise a field effect transistor.
  • the field effect transistor is a metal-oxide semiconductor FET having an N-channel (enhancement MOSFET).
  • both the drain 18 and the source 16 are n-doped.
  • the channel between source 16 and drain 18 is p-doped.
  • a silicon dioxide layer insulates the floating gate 10 from the n-channel.
  • the floating gate 10 is made out of poly-silicon.
  • the additional gate 40 is either made out of a second poly-silicon layer or a TiN-layer (although any conducting layer can be used). Silicon dioxide layers isolate the additional gate 40 from the floating gate 10 and the control gate 12 from the floating gate 10 .
  • the source 16 , the drain 18 and the control gate 12 comprise n-doped areas within a p-doped bulk area 15 .
  • a back gate 20 is connected to the bulk area 15 .
  • the purpose of a back gate 20 is the same as in conventional integrated MOSFET devices.
  • FIG. 5 shows schematically a cross section of the Single Poly EPROM device shown in FIG. 4 .
  • This cross section is taken approximately in the plane indicated by the reference sign h in FIG. 4 .
  • the control gate 12 is positioned laterally to the drain 18 . Both areas are n-doped.
  • the floating gate 10 is made out of poly-silicon and is positioned above both the drain 18 and the control gate 12 shown in FIG. 5 .
  • the floating gate 10 is electrically isolated from the control gate 12 .
  • Reference sign C 1 depicts a capacitance between the control gate 12 and the floating gate 10 .
  • the additional gate 40 is positioned above the floating gate 10 .
  • Reference numeral C 2 depicts the capacitance between the additional gate 40 and the floating gate 10 .
  • the capacitances CI and C 2 are connected in series to each other.
  • the voltage at the floating gate 10 is determined by the voltage drop between the additional gate 40 and the control gate 12 as well as the capacitances C 1 and C 2 shown in FIG. 5 .
  • the size of the capacitances C 1 and C 2 is determined by the geometry of the gates 40 , 10 and 12 as well as the insulating layers between these gates.
  • the additional gate 40 is connected to the output of a tri-state buffer 60 .
  • the tri-state buffer 60 may be controlled to pass its buffer input 64 to its buffer output 62 by appropriately selecting the select input 68 equal to “0”.
  • the buffer input 64 is connected to ground potential GND and a programming voltage VPP is applied to the control gate 12 .
  • VPP programming voltage
  • the voltage drop between control gate 12 and additional gate 40 is equal to the programming voltage VPP. If the capacitances C 1 and C 2 are equal, then the voltage of the floating gate 10 will be ⁇ 1 ⁇ 2*VPP. No programming will occur, because the voltage between the drain 18 and the floating gate 10 is too small to allow Fowler-Nordheim tunneling.
  • the buffer output is made to be floating by appropriately selecting the select input 68 equal to “1”. Consequently, the additional gate 40 is floating.
  • the drain 18 is connected to ground potential GND.
  • the voltage drop between control gate 12 and floating gate is equal to the programming voltage VPP multiplied by a coupling ratio. Fowler-Nordheim occurs and the Single Poly EPROM device is programmed. An erasure of the Single Poly EPROM device is carried out by applying the programming voltage to the ground 18 and applying ground potential to the control gate.
  • FIG. 6 illustrates schematically an array of Single Poly EPROM devices 66 according to the embodiment of the present invention.
  • Each of the Single Poly EPROM devices 66 has a control gate 12 and an additional gate 40 .
  • the particular layout of each of the Single Poly EPROM devices 66 is depicted in FIGS. 4 and 5 .
  • the Single Poly EPROM devices 66 are aligned in rows ROW 1 , ROW 2 and columns COL 1 and COL 2 .
  • the drains 18 of each Single Poly EPROM device 66 are connected to a bit line BL 1 , BL 2 .
  • the sources 16 of each Single Poly EPROM device 66 in a single column COL 1 , COL 2 are connected to each other.
  • tri-state buffers 60 are shown in FIG. 6 .
  • the additional gates 40 of the Single Poly EPROM devices 66 in one row ROW 1 , ROW 2 are connected to the output 62 of a single tri-state buffer 60 .
  • Each tri-state buffer 60 also comprises a buffer input 64 and a select input 68 .
  • the state of the tri-state buffer 60 is determined by a select signal fed to the select input 68 . If the select signal is equal to zero, then the tri-state buffer 60 transfers the select signal to the buffer output 62 . If the select signal is equal to 1, then the buffer 62 output is floating.
  • the voltage at the additional gate 40 of the Single Poly EPROM devices 66 in a single row ROW 1 , ROW 2 may be controlled by one tri-state buffer 60 . If programming or erasing of one of the Single Poly EPROM devices 66 is to be carried out, then the tri-state buffer 60 in the corresponding row ROW 1 , ROW 2 is controlled in such a way, that the buffer output 62 is floating. However, the remaining buffer outputs 62 are used to control the voltage of the additional gate 40 .
  • the voltage applied to the drain 18 of the Single Poly EPROM device 66 for programming or erasing may not charge or discharge the floating gates 10 of the remaining Single Poly EPROM devices 66 . No select transistors as in the conventional memory array is necessary for protecting the drains 18 of the Single Poly EPROM devices 66 in the memory array. Consequently, the area of the memory array may be considerably reduced.

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US11/314,587 2004-12-22 2005-12-21 Single poly EPROM device with double control gates to prevent unintentionally charging/discharging Active 2026-10-09 US7436701B2 (en)

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DE102004061921.2 2004-12-22
DE102004061921A DE102004061921B4 (de) 2004-12-22 2004-12-22 Halbleiterspeichervorrichtung umfassend mehrere Single-Poly-EPROM-Vorrichtungen

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9355726B2 (en) 2014-04-29 2016-05-31 SK Hynix Inc. EPROM cell array, method of operating the same, and memory device including the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US20110233643A1 (en) * 2010-03-23 2011-09-29 Chingis Technology Corporation PMOS Flash Cell Using Bottom Poly Control Gate

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5790455A (en) 1997-01-02 1998-08-04 John Caywood Low voltage single supply CMOS electrically erasable read-only memory
US5798548A (en) * 1995-05-18 1998-08-25 Sanyo Electric Co., Ltd. Semiconductor device having multiple control gates
US20010025980A1 (en) 1997-07-03 2001-10-04 Roberta Bottini Process for producing a semiconductor memory device comprising mass-storage memory cells and shielded memory cells for storing reserved information
US6433609B1 (en) * 2001-11-19 2002-08-13 International Business Machines Corporation Double-gate low power SOI active clamp network for single power supply and multiple power supply applications
US6535430B2 (en) * 2000-02-16 2003-03-18 Halo, Inc. Wordline decoder for flash memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798548A (en) * 1995-05-18 1998-08-25 Sanyo Electric Co., Ltd. Semiconductor device having multiple control gates
US5790455A (en) 1997-01-02 1998-08-04 John Caywood Low voltage single supply CMOS electrically erasable read-only memory
US20010025980A1 (en) 1997-07-03 2001-10-04 Roberta Bottini Process for producing a semiconductor memory device comprising mass-storage memory cells and shielded memory cells for storing reserved information
US6535430B2 (en) * 2000-02-16 2003-03-18 Halo, Inc. Wordline decoder for flash memory
US6433609B1 (en) * 2001-11-19 2002-08-13 International Business Machines Corporation Double-gate low power SOI active clamp network for single power supply and multiple power supply applications

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9355726B2 (en) 2014-04-29 2016-05-31 SK Hynix Inc. EPROM cell array, method of operating the same, and memory device including the same
TWI618065B (zh) * 2014-04-29 2018-03-11 愛思開海力士有限公司 電性可程式化唯讀記憶體單元陣列、操作其之方法以及包含其之記憶體裝置

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US20060133151A1 (en) 2006-06-22
DE102004061921B4 (de) 2011-03-10

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