US7277542B2 - Stream cipher encryption application accelerator and methods thereof - Google Patents

Stream cipher encryption application accelerator and methods thereof Download PDF

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US7277542B2
US7277542B2 US09/916,557 US91655701A US7277542B2 US 7277542 B2 US7277542 B2 US 7277542B2 US 91655701 A US91655701 A US 91655701A US 7277542 B2 US7277542 B2 US 7277542B2
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accelerator
data
memory
state memory
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US20020037079A1 (en
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Donald E. Duval
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Avago Technologies International Sales Pte Ltd
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Broadcom Corp
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Priority to DE60117230T priority patent/DE60117230T2/de
Priority to EP01308059A priority patent/EP1191739B1/de
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Priority to US11/905,468 priority patent/US7903813B2/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/722—Modular multiplication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
    • H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49936—Normalisation mentioned as feature only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/56—Financial cryptography, e.g. electronic payment or e-cash
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2463/00—Additional details relating to network architectures or network communication protocols for network security covered by H04L63/00
    • H04L2463/102—Additional details relating to network architectures or network communication protocols for network security covered by H04L63/00 applying security measure for e-commerce

Definitions

  • the present invention relates to a deployed cryptographic application in a distributed computing environment. More specifically, a stream cipher encryption algorithm accelerator and methods of use thereof is described.
  • RC4 is a trademark of RSA Security Inc of Redwood City, Calif.
  • RC4TM is a secure, variable key-size stream cipher with byte-oriented operations.
  • the RC4TM algorithm is based on the use of a random permutation having a period that is overwhelmingly likely to be greater than 10 100 . Typically, eight to sixteen machine operations are required per output byte.
  • RC4TM uses a variable length key from 1 to 256 bytes to initialize a 256-byte state table.
  • the state table is used for subsequent generation of pseudo-random bytes and then to generate a pseudo-random stream which is XORed with the plaintext to give the ciphertext.
  • Each element in the state table is swapped at least once.
  • RC4TM was proprietary and details of the algorithm were only available after signing a nondisclosure agreement.
  • someone anonymously posted source code (referred to as “Alleged RC4”, or more commonly referred to as ARCFOUR) to a user group mailing list.
  • ARCFOUR quickly spread to various Usenet newsgroups and, ultimately, via the Internet to ftp sites around the world. Readers with legal copies of RC4 confirmed compatibility between ARCFOUR and RC4TM owned by RSA Data Security, Inc. which tried unsuccessfully to claim that ARCFOUR was a trade secret even though it was public. Consequently, ARCFOUR has become the defacto standard for online encryption and has become one of the most popular encryption algorithms in the browser market.
  • the conventional system 100 includes a CPU 102 coupled to a first memory array 104 used to store a secret key(s) and a second memory array 106 used to store an incrementing pattern by way of an interface 108 .
  • the CPU 102 is also connected to a state array unit 110 and a data storage device 112 , such as a register, memory device, and so on, used to store a message 114 to be, in this example, encrypted using the ARCFOUR algorithm.
  • a process 200 as shown by the flowchart illustrated in FIG. 2 is used.
  • the CPU 102 performs a mixing operation by, at 202 , storing an incrementing pattern in the second memory array 106 and a secret key (or keys) in the first memory array 104 .
  • the CPU 102 performs a shifting operation based upon the key values stored in the first memory array 104 and at 206 updates the state array 110 thereby completing the mixing operation.
  • the CPU 102 performs a ciphering operation at 208 on each byte of the message 112 until such time as the encrypted message is ready to be transmitted to a receiver. It should be noted that a received encrypted message is decrypted in a substantially similar manner.
  • an efficient encryption accelerator and methods of use thereof that off loads most, if not all, of the encryption/decryption operations from a system CPU.
  • the efficient encryption accelerator is most appropriate for use in a secure e-commerce transaction carried out over an unsecure network of distributed computing devices, such as the Internet.
  • An efficient encryption system and encryption accelerator are disclosed.
  • the encryption system and encryption accelerator is most appropriate for use in executing a secure e-commerce transaction carried out over an unsecure network of distributed computing devices, such as the Internet.
  • a system for encrypting and decrypting data formed of a number of bytes using an encryption algorithm includes a system bus and an encryption accelerator arranged to execute the encryption algorithm coupled to the system bus.
  • an encryption accelerator produces an initial incrementing state memory pattern totally in hardware whereas the shuffling operation is performed by transferring the secret key data in bytes into the accelerator via an external interface. It should be noted that the shuffling operation is performed on the fly as the key data transfer takes place. After the state memory shuffling operation has been completed, the data that is to be encrypted (or decrypted) is transferred to the accelerator through the external interface. For each byte of date the accelerator produces a byte from the state memory which is exclusive-OR'd with the byte of data. The state memory is then shuffled further through a data dependent swapping operation.
  • the accelerator uses the ARCFOUR encryption algorithm and is capable of operating in a number of modes.
  • One such mode is arranged to accommodate an interruption of the processing of a first data stream to process a second, orthogonal data stream. After completion of the processing of the second data stream, the first data stream processing is restarted where it originally left off.
  • FIG. 1 illustrates a conventional CPU based encryption/decryption system.
  • FIG. 2 shows a flowchart detailing a process for encrypting a message using an ARCFOUR encryption process.
  • FIG. 3 shows a system having an encryption accelerator coupled to a central processing unit in accordance with an embodiment of the invention.
  • FIG. 4 shows a particular implementation of the encryption accelerator shown in FIG. 3 .
  • FIG. 5 shows a particular implementation of the encryption accelerator in accordance with an embodiment of the invention that includes a state machine coupled to the state memory and an input interface.
  • FIG. 6 shows a flowchart detailing a process for implementing the ARCFOUR algorithm by the accelerator in accordance with an embodiment of the invention.
  • FIG. 7 shows a flowchart detailing a process for implementing the ciphering operation of the process shown in FIG. 6 .
  • FIG. 8 illustrates a typical, general-purpose computer system suitable for implementing the present invention.
  • the inventive encryption accelerator implements the ARCFOUR algorithm by requiring that a 256 byte state memory be initialized with an incrementing pattern (i.e., location 0 contains the value 0, location 1 contains the value 1, and so on).
  • a key consisting of one to 256 bytes where each byte is 8 bits, is then used to move the state memory values to new locations in a shuffling operation.
  • the values in the state memory at the end of this operation consist of the numbers 0 through 255, but the locations of those values are only known if the key is known.
  • this inventive accelerator produces the initial incrementing state memory pattern totally in hardware whereas the shuffling operation is performed by transferring the key data, modulo key length in bytes into the accelerator via an external interface. It should be noted that the shuffling operation is performed on the fly as the key data transfer takes place.
  • the data that is to be encrypted (or decrypted) is transferred to the accelerator through the external interface.
  • the accelerator produces a byte from the state memory that is exclusive-OR'd with the byte of data to produce the encrypted byte of data.
  • the state memory is then shuffled further through a data dependent swapping operation.
  • the inventive encryption accelerator is capable of accommodating multiple streams of data by, for example, operating in multiple modes. These operation modes include an Initial Mode and a Continuation Mode.
  • Initial Mode When the accelerator is operating in the Initial Mode, the operations described above are performed sequentially, whereas in the Continuation mode, the state memory is loaded with the contents of the state memory that were saved when an earlier stream of data was interrupted. In either mode, when a Last Transfer flag is not set, the contents of the state memory are saved externally to the accelerator.
  • the invention will now be described in terms of an encryption/decryption accelerator system that can be implemented in a number of ways, such as for example, as a stand alone integrated circuit, as embedded software, or as a subsystem included in, for example, a server computer used in a variety of Internet and Internet related activities. It should be noted, however, that the invention is not limited to the described embodiments and can be used in any system where high speed encryption is desired.
  • FIG. 3 shows a system 300 having an encryption accelerator 302 coupled to a central processing unit 304 in accordance with an embodiment of the invention.
  • the encryption accelerator 302 is coupled to the CPU 304 by way of an I/O bus 306 that is, in turn, coupled to a system bus 308 .
  • a system memory 312 Also coupled to the system bus 308 by way of a memory bus 310 is a system memory 312 arranged, in this implementation, to store a secret key (or keys) corresponding to a particular message (or messages) to be encrypted (or decrypted).
  • a buffer or other such storage device can be used to intermittently store the message to be encrypted at a point that is in temporal proximity to the accelerator 302 thereby improving system 300 performance.
  • a storage device can include a FIFO type buffer or buffers used to store, for example, the message to be encrypted or the encrypted message prior to being transmitted to an I/O port 314 coupled to external circuitry.
  • the inventive encryption accelerator 302 implements the ARCFOUR algorithm by requiring that a state memory 316 be initialized with an incrementing pattern (i.e., location 0 contains the value 0, location 1 contains the value 1, and so on) .
  • the state memory 316 is 256 bytes in size.
  • a secret key array 318 that is stored in the system memory 312 is used to move state memory values to new locations in the state memory 316 .
  • the secret key array 318 consists of 256 bytes, where each byte is 8 bits. The secret key array 318 is produced by repeating the secret key until 256 bytes are filled.
  • the values in the state memory 316 at the end of the shuffling operation consist of the numbers 0 through 255, but the locations of those values in the state memory 316 are only known if the secret key array 318 is known.
  • this inventive accelerator 302 produces the initial incrementing state memory pattern totally in hardware whereas the shuffling operation is performed by transferring the secret key array 318 and an associated message data length (in bytes) into the accelerator 302 via the system bus 308 and any intervening external interfaces thereby preserving valuable CPU resources. It should be noted that the shuffling operation in the state memory 316 is performed “on the fly” as transfer of the secret key array 318 takes place.
  • the data that is to be encrypted is transferred to the accelerator 302 through the system bus 308 .
  • the accelerator 302 produces a byte from the state memory 316 which is exclusive-OR'd with the corresponding byte of data to be encrypted.
  • the state memory 316 is then shuffled further through a data dependent swapping operation.
  • the encryption accelerator 302 is capable of operating in multiple modes that include an Initial Mode and a Continuation Mode.
  • Initial Mode When the accelerator is operation in the Initial Mode, the operations described above are performed sequentially.
  • the state memory 316 when in the Continuation mode, the state memory 316 is reloaded with the contents of the state memory 316 that were saved to external memory (such as the system memory 312 , if so desired) when a Last Transfer flag is not set when an earlier stream of data was interrupted.
  • FIG. 5 shows a particular implementation of the encryption accelerator 302 in accordance with an embodiment of the invention that includes a state machine 502 coupled to the state memory 316 and an input interface 504 .
  • the accelerator 302 also includes an index I counter 506 and an index J counter 508 each coupled to the state machine 502 and a combinational logic block 509 .
  • a combinational logic block 510 is coupled to the state memory 316 and the state machine 502 as well as an output interface 512 .
  • the combinational logic block 510 is configured to operate as an exclusive OR logic block.
  • an input FIFO 514 and an output FIFO 516 each coupled to the state machine 502 and the system bus 308 are provided to latch the data to be encrypted (on the input side) and the encrypted data (on the output side).
  • the state machine 502 directs the shuffling operation in the state memory 316 by causing the secret key array 318 to be retrieved from the system memory 312 and directing the counters 506 and 508 to increment the indices (i,j) accordingly. In this way, the shuffling operations are completely performed by the accelerator 302 thereby preserving valuable CPU resources.
  • the state machine 502 determines that when data to be encrypted is stored in the input FIFO 514 , that on a byte wise basis, the data to be encrypted is passed by way of the input interface to the combination logic block where, in this example, it is exclusive OR'd with the contents of the state memory 316 .
  • the result of this exclusive OR'ing operation represents an encrypted byte which is then passed to the output FIFO 516 .
  • the state machine 502 determines if there are additional bytes to be encrypted and if so determined, directs the accelerator 302 to act accordingly.
  • the state machine 502 when in continuation mode, if a second data stream is to be processed, the state machine 502 directs that the contents of the state memory 316 be stored externally (if the last transfer flag is not set) until such time as the second data stream has been completely processed by the accelerator 302 . At this point, the state machine 502 directs that the stored values of the state memory 316 corresponding to the last state of the processing of the first data stream be restored to the state memory 316 and then restarts processing of the interrupted first data stream.
  • FIG. 6 shows a flowchart detailing a process 600 for implementing the ARCFOUR algorithm by the accelerator 302 in accordance with an embodiment of the invention.
  • the process 600 begins at 602 where the state machine is initialized. Next, at 603 , an incrementing pattern is stored in the state memory. Next at 604 , the index variables i and j are initialized.
  • the state machine directs a shuffling operation, according to the ARCFOUR (or RC4) stream cipher, that includes, at 608 , adding the contents of the i th element of the state memory to the variable j and the nth element of the secret key array. The variable j is then set to the sum calculated in step 608 modulo 256 .
  • the i th and j th elements of the state memory are swapped.
  • the i th index variable is incremented, and at 614 a determination is made whether or not the incremented index variable i is greater than the maximum allowable value. If the incremented index variable i is not greater than the max value, then the shuffling operation 606 continues, otherwise, the index variables i and j are initialized at 616 thereby completing the key setup portion of the ARCFOUR algorithm.
  • a ciphering portion of ARCFOUR algorithm is performed at 618 on a data stream to be encypted to form an encrypted data stream at 620 .
  • FIG. 7 shows a flowchart detailing a process 700 for implementing the ciphering operation 618 , according to the ARCFOUR (or RC4) stream cipher, of the process 600 shown in FIG. 6 .
  • the process 700 begins at 702 by receiving a byte of the data to be encrypted and at 704 by incrementing the index variable i by one.
  • the variable i is then set to the incremented value determined in step 704 modulo 256 .
  • the variable j is then set to the sum of j and the i th element of the state memory modulo 256 .
  • the contents of the i th element of the state memory is added to the j th element of the state memory while at 708 the i th and j th elements of the state memory are swapped.
  • the i th and the j th elements of the state memory are added together to form a new value n.
  • the variable n is then set to the value n determined in step 709 modulo 256 .
  • an encrypted output byte is formed by combining the nth element of the state memory with the data byte to be encrypted using a bit by bit exclusive OR operation.
  • a determination is made whether or not there are additional bytes to be encrypted. If there are additional bytes, then control is passed back to 702 , otherwise processing is stopped.
  • FIG. 8 illustrates a typical, general-purpose computer system 800 suitable for implementing the present invention.
  • the computer system 800 includes at least one processor (CPU) 802 that is coupled to memory devices including primary storage devices 806 (typically a read only memory, or ROM) and primary storage devices 804 (typically a random access memory, or RAM).
  • primary storage devices 806 typically a read only memory, or ROM
  • primary storage devices 804 typically a random access memory, or RAM
  • Computer system 800 or, more specifically, CPUs 802 , may be arranged to support a virtual machine, as will be appreciated by those skilled in the art.
  • ROM acts to transfer data and instructions uni-directionally to the CPUs 802
  • RAM is used typically to transfer data and instructions in a bi-directional manner.
  • CPUs 802 may generally include any number of processors.
  • Both primary storage devices 804 , 806 may include any suitable computer-readable media.
  • a secondary storage medium 808 which is typically a mass memory device, is also coupled bi-directionally to CPUs 802 and provides additional data storage capacity.
  • the mass memory device 808 is a computer-readable medium that may be used to store programs including computer code, data, and the like.
  • mass memory device 808 is a storage medium such as a hard disk or a tape which generally slower than primary storage devices 804 , 806 .
  • Mass memory storage device 808 may take the form of a magnetic or paper tape reader or some other well-known device. It will be appreciated that the information retained within the mass memory device 808 , may, in appropriate cases, be incorporated in standard fashion as part of RAM 806 as virtual memory.
  • a specific primary storage device 804 such as a CD-ROM may also pass data uni-directionally to the CPUs 802 .
  • CPUs 802 are also coupled to one or more input/output devices 810 that may include, but are not limited to, devices such as video monitors, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, or other well-known input devices such as, of course, other computers.
  • CPUs 802 optionally may be coupled to a computer or telecommunications network, e.g., an internet network or an intranet network, using a network connection as shown generally at 812 . With such a network connection, it is contemplated that the CPUs 802 might receive information from the network, or might output information to the network in the course of performing the above-described method steps.
  • Such information which is often represented as a sequence of instructions to be executed using CPUs 802 , may be received from and outputted to the network, for example, in the form of a computer data signal embodied in a carrier wave.
  • the above-described devices and materials will be familiar to those of skill in the computer hardware and software arts.

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US09/916,557 US7277542B2 (en) 2000-09-25 2001-07-26 Stream cipher encryption application accelerator and methods thereof
DE60117230T DE60117230T2 (de) 2000-09-25 2001-09-21 Stromverschlüsselungsanwendungsbeschleuniger und zugehöriges Verfahren
EP01308059A EP1191739B1 (de) 2000-09-25 2001-09-21 Stromverschlüsselungsanwendungsbeschleuniger und zugehöriges Verfahren
US11/905,468 US7903813B2 (en) 2000-09-25 2007-10-01 Stream cipher encryption application accelerator and methods thereof

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