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US7259434B2 - Highly reliable amorphous high-k gate oxide ZrO2 - Google Patents

Highly reliable amorphous high-k gate oxide ZrO2 Download PDF

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US7259434B2
US7259434B2 US10931356 US93135604A US7259434B2 US 7259434 B2 US7259434 B2 US 7259434B2 US 10931356 US10931356 US 10931356 US 93135604 A US93135604 A US 93135604A US 7259434 B2 US7259434 B2 US 7259434B2
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oxide
gate
layer
region
surface
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Kie Y. Ahn
Leonard Forbes
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Micron Technology Inc
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Micron Technology Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/1052Memory structures and multistep manufacturing processes therefor not provided for in groups H01L27/1055 - H01L27/112
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31683Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures

Abstract

A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset in a range of approximately 5.16 eV to 7.8 eV. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Description

CROSS REFERENCE TO RELATED APPLICATION

This application is a Divisional of U.S. application Ser. No. 09/945,535 filed on Aug. 30, 2001, which application is herein incorporated by reference.

FIELD OF THE INVENTION

The invention relates to semiconductor devices and device fabrication. Specifically, the invention relates to gate oxide layers of transistor devices and their method of fabrication.

BACKGROUND OF THE INVENTION

In the semiconductor device industry, particularly in the fabrication of transistors, there is continuous pressure to reduce the size of devices such as transistors. The ultimate goal is to fabricate increasingly smaller and more reliable integrated circuits (ICs) for use in products such as processor chips, mobile telephones, or memory devices such as DRAMs. The smaller devices are frequently powered by batteries, where there is also pressure to reduce the size of the batteries, and to extend the time between battery charges. This forces the industry to not only design smaller transistors, but to design them to operate reliably with lower power supplies.

A common configuration of a transistor is shown in FIG. 1. While the following discussion uses FIG. 1 to illustrate a transistor from the prior art, one skilled in the art will recognize that the present invention could be incorporated into the transistor shown in FIG. 1 to form a novel transistor according to the invention. The transistor 100 is fabricated in a substrate 110 that is typically silicon, but could be fabricated from other semiconductor materials as well. The transistor 100 has a first source/drain region 120 and a second source/drain region 130. A body region 132 is located between the first source/drain region and the second source/drain region, the body region 132 defining a channel of the transistor with a channel length 134. A gate dielectric, or gate oxide 140 is located on the body region 132 with a gate 150 located over the gate oxide. Although the gate dielectric can be formed from materials other than oxides, the gate dielectric is typically an oxide, and is commonly referred to as a gate oxide. The gate may be fabricated from polycrystalline silicon (polysilicon) or other conducting materials such as metal may be used.

In fabricating transistors to be smaller in size and reliably operating on lower power supplies, one important design criteria is the gate oxide 140. A gate oxide 140, when operating in a transistor, has both a physical gate oxide thickness and an equivalent oxide thickness (EOT). The equivalent oxide thickness quantifies the electrical properties, such as capacitance, of a gate oxide 140 in terms of a representative physical thickness. EOT is defined as the thickness of a theoretical SiO2 layer that describes the actual electrical operating characteristics of the gate oxide 140 in the transistor 100. For example, in traditional SiO2 gate oxides, a physical oxide thickness may be 5.0 nm, but due to undesirable electrical effects such as gate depletion, the EOT may be 6.0 nm. A gate oxide other than SiO2 may also be described electrically in terms of an EOT. In this case, the theoretical oxide referred to in the EOT number is an equivalent SiO2 oxide layer. For example, SiO2 has a dielectric constant of approximately 4. An alternate oxide with a dielectric constant of 20 and a physical thickness of 100 nm would have an EOT of approximately 20 nm (100*(4/20)), which represents a theoretical SiO2 gate oxide.

Lower transistor operating voltages and smaller transistors require thinner equivalent oxide thicknesses (EOTs). A problem with the increasing pressure of smaller transistors and lower operating voltages is that gate oxides fabricated from SiO2 are at their limit with regards to physical thickness and EOT. Attempts to fabricate SiO2 gate oxides thinner than today's physical thicknesses show that these gate oxides no longer have acceptable electrical properties. As a result, the EOT of a SiO2 gate oxide 140 can no longer be reduced by merely reducing the physical gate oxide thickness.

Attempts to solve this problem have led to interest in gate oxides made from oxide materials other than SiO2. Certain alternate oxides have a higher dielectric constant (k), which allows the physical thickness of a gate oxide 140 to be the same as existing SiO2 limits or thicker, but provides an EOT that is thinner than current SiO2 limits.

A problem that arises in forming an alternate oxide layer on the body region of a transistor is the process in which the alternate oxide is formed on the body region. Recent studies show that the surface roughness of the body region has a large effect on the electrical properties of the gate oxide, and the resulting operating characteristics of the transistor. The leakage current through a physical 1.0 nm gate oxide increases by a factor of 10 for every 0.1 increase in the root-mean-square (RMS) roughness. In forming an alternate oxide layer on the body region of a transistor, a thin layer of the alternate material to be oxidized (typically a metal) must first be deposited on the body region. Current processes for depositing a metal or other alternate layer on the body region of a transistor are unacceptable due to their effect on the surface roughness of the body region.

FIG. 2 a shows a surface 210 of a body region 200 of a transistor. The surface 210 in the Figure has a high degree of smoothness, with a surface variation 220. FIG. 2 b shows the body region 200 during a conventional sputtering deposition process stage. During sputtering, particles 230 of the material to be deposited bombard the surface 210 at a high energy. When a particle 230 hits the surface 210, some particles adhere as shown by particle 235, and other particles cause damage as shown by pit 240. High energy impacts can throw off body region particles 215 to create the pits 240. A resulting layer 250 as deposited by sputtering is shown in FIG. 2 c. The deposited layer/body region interface 255 is shown following a rough contour created by the sputtering damage. The surface of the deposited layer 260 also shows a rough contour due to the rough interface 255.

In a typical process of forming an alternate material gate oxide, the deposited layer 250 is oxidized to convert the layer 250 to an oxide material. Existing oxidation processes do not, however, repair the surface damage created by existing deposition methods such as sputtering. As described above, surface roughness has a large influence on the electrical properties of the gate oxide and the resulting transistor.

What is needed is an alternate material gate oxide that is more reliable at existing EOTs than current gate oxides. What is also needed is an alternate material gate oxide with an EOT thinner than conventional SiO2. What is also needed is an alternative material gate oxide with a smooth interface between the gate oxide and the body region. Because existing methods of deposition are not capable of providing a smooth interface with an alternate material gate oxide, what is further needed is a method of forming an alternate material gate oxide that maintains a smooth interface.

Additionally, at higher process temperatures, any of several materials used to fabricate the transistor, such as silicon, can react with other materials such as metals or oxygen to form unwanted suicides or oxides. What is needed is a lower temperature process of forming gate oxides that prevents the formation of unwanted byproduct materials.

SUMMARY OF THE INVENTION

A method of forming a gate oxide on a surface such as a transistor body region is shown where a metal layer is deposited by thermal evaporation on the body region, the metal being chosen from a group consisting of the group IVB elements of the periodic table. The metal layer is then oxidized to convert the metal layer to a gate oxide. In one embodiment, the metal layer includes zirconium (Zr). One embodiment of the invention uses an electron beam source to evaporate the metal layer onto the body region of the transistor. The oxidation process in one embodiment utilizes a krypton(Kr)/oxygen (O2) mixed plasma process.

In addition to the novel process of forming a gate oxide layer, a transistor formed by the novel process exhibits novel features that may only be formed by the novel process. Thermal evaporation deposition of a metal layer onto a body region of a transistor preserves an original smooth surface roughness of the body region in contrast to other prior deposition methods that increase surface roughness. The resulting transistor fabricated with the process of this invention will exhibit a gate oxide/body region interface with a surface roughness variation as low as 0.6 nm.

These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a common configuration of a transistor.

FIG. 2 a shows a smooth surface of a body region of a transistor.

FIG. 2 b shows a deposition process according to the prior art.

FIG. 2 c shows a deposited film on a body region according to the prior art.

FIG. 3 a shows a deposition process according to the invention.

FIG. 3 b shows a magnified view of a deposited film on a body region from FIG. 3 a.

FIG. 4 a shows a deposited film on a body region according to the invention.

FIG. 4 b shows a partially oxidized film on a body region according to the invention.

FIG. 4 c shows a completely oxidized film on a body region according to the invention.

FIG. 5 shows a perspective view of a personal computer.

FIG. 6 shows a schematic view of a central processing unit.

FIG. 7 shows a schematic view of a DRAM memory device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors.

The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

FIG. 3 a shows an electron beam evaporation technique to deposit a material on a surface such as a body region of a transistor. In FIG. 3 a, a substrate 310 is placed inside a deposition chamber 300. The substrate in this embodiment is masked by a first masking structure 312 and a second masking structure 314. In this embodiment, the unmasked region 316 includes a body region of a transistor, however one skilled in the art will recognize that other semiconductor device structures may utilize this process. Also located within the deposition chamber 300 is an electron beam source 330, and a target material 334. Although in this embodiment, an electron beam evaporation technique is used, it will be apparent to one skilled in the art that other thermal evaporation techniques can be used without departing from the scope of the invention. During the evaporation process, the electron beam source 330 generates an electron beam 332. The electron beam hits the target material 334 and heats a portion of the target material enough to cause the surface of the target material to evaporate. The evaporated material 336 is then distributed throughout the chamber 300, and the material 336 deposits on surfaces that it contacts, such as the exposed body region 316. The depositing material builds up to form a layer 320 of material that is chemically the same as the target material 334.

In one embodiment of the invention, the deposited material layer 320 includes a pure metal layer chosen from the alkaline earth metals in group IVB of the periodic table. In one embodiment of the invention, the deposited material layer 320 includes zirconium (Zr). In one embodiment of the invention, the target material is a 99.9999% pure slug of zirconium. The choice of material is based on the properties of the oxide formed. Considerations included the thermodynamic stability of the oxide with silicon, the diffusion coefficient of the oxide at high processing temperatures such as 1000° K., the lattice match of the oxide with silicon, the dielectric constant of the oxide, and the conduction band offset of the oxide. In one embodiment, the conduction band offset of the metal oxide formed is in a range of approximately 5.16 eV to 7.8 eV. In one embodiment, the deposited material layer 320 is substantially amorphous. A lower presence of grain boundaries in the substantially amorphous material layer 320 reduces the leakage current through the final gate oxide. Although the amorphous form is preferred, the material chosen for oxidation, such as zirconium is also acceptable in its crystalline form.

A thermal evaporation process such as the electron beam evaporation technique described above does not cause the surface damage that is inherent in other deposition techniques such as the sputtering technique shown in FIG. 2 b. This allows a very thin layer of material to be deposited on a body region of a transistor, while maintaining a smooth interface. A thermal evaporation process such as the electron beam evaporation technique described above also allows low processing temperatures that inhibit the formation of unwanted byproducts such as suicides and oxides. In one embodiment, the thermal evaporation is performed with a substrate temperature between approximately 150 and 200° C.

FIG. 3 b shows a magnified view of the body region 316 and the deposited layer 320 from FIG. 3 a. The interface 340 is shown with a roughness variation 346. The deposited layer surface 348 is also shown with a similar surface roughness. One possible surface variation 346 would be an atomic layer variation. In atomic smoothness, the greatest difference in surface features is between a first atomic layer as indicated by layer 342 and a second atomic layer 344. The thermal evaporation deposition technique described above preserves atomic smoothness such as is shown in FIG. 3 b, however other acceptable levels of surface roughness greater than atomic smoothness will also be preserved by the thermal evaporation technique.

FIGS. 4 a4 c show a low temperature oxidation process that is used in one embodiment to convert the deposited layer 320 into a gate oxide. A deposited material layer 410 is shown in FIG. 4 a on a substrate surface 400. The layer 410 forms an interface 420 with the substrate surface 400, and the layer 410 has an outer surface 430. The layer 410 in this embodiment is deposited over a body region of a transistor, however the layer may be deposited on any surface within the scope of the invention.

In FIG. 4 b, the layer 410 is in the process of being oxidized. In one embodiment, the oxidation process includes a krypton/oxygen mixed plasma oxidation process. The mixed plasma process generates atomic oxygen or oxygen radicals in contrast to molecular oxygen or O2 used in conventional thermal oxidation. The atomic oxygen is introduced to the layer from all exposed directions as indicated by arrows 440, creating an oxide portion 450. The atomic oxygen continues to react with the layer and creates an oxidation interface 422. As the reaction progresses, atomic oxygen diffuses through the oxide portion 450 and reacts at the oxidation interface 422 until the layer is completely converted to an oxide of the deposited material layer. FIG. 4 c shows the resulting oxide layer 450 which spans a physical thickness 452 from the outer surface 430 to the interface 420.

In one embodiment, the processing variables for the mixed plasma oxidation include a low ion bombardment energy of less than 7 eV, a high plasma density above 1012/cm3 and a low electron temperature below 1.3 eV. In one embodiment, the substrate temperature is approximately 400° C. In one embodiment, a mixed gas of 3% oxygen with the balance being krypton at a pressure of 1 Torr is used. In one embodiment, a microwave power density of 5 W/cm2 is used. In one embodiment, the oxidation process provides a growth rate of 1.5 nm/min.

The low temperature mixed plasma oxidation process described above allows the deposited layer to be oxidized at a low temperature, which inhibits the formation of unwanted byproducts such as silicides and oxides. The mixed plasma process in one embodiment is performed at approximately 400° C. in contrast to prior thermal oxidation processes that are performed at approximately 1000° C. The mixed plasma oxidation process has also been shown to provide improved thickness variation on silicon (111) surfaces in addition to (100) surfaces. Although the low temperature mixed plasma process above describes the formation of alternate material oxides, one skilled in the art will recognize that the process can also be used to form SiO2 oxide structures.

Metals chosen from group IVB of the periodic table form oxides that are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. Zirconium is one example of a metal selected from group IVB that forms a thermodynamically stable gate oxide. In particular, zirconium forms an oxide comprised of ZrO2. Zirconium oxide ZrO2 exhibits a dielectric constant of approximately 25, which allows for a thinner EOT than conventional SiO2. In addition to the stable thermodynamic properties inherent in the oxides chosen, the novel process used to form the oxide layer is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures.

A transistor made using the novel gate oxide process described above will possess several novel features. By creating an oxide material with a higher dielectric constant (k) and controlling surface roughness during formation, a gate oxide can be formed with an EOT thinner than 2 nm. A thicker gate oxide that is more uniform, and easier to process can also be formed with the alternate material oxide of the present invention, the alternate material gate oxide possessing an EOT equivalent to the current limits of SiO2 gate oxides. The smooth surface of the body region is preserved during processing, and a resulting transistor will have a smooth interface between the body region and the gate oxide with a surface roughness on the order of 0.6 nm.

Transistors created by the methods described above may be implemented into memory devices and information handling devices as shown in FIGS. 5–7 and described below. While specific types of memory devices and computing devices are shown below, it will be recognized by one skilled in the art that several types of memory devices and information handling devices could utilize the invention.

A personal computer, as shown in FIGS. 5 and 6, include a monitor 500, keyboard input 502 and a central processing unit 504. The processor unit typically includes microprocessor 606, memory bus circuit 608 having a plurality of memory slots 612(a–n), and other peripheral circuitry 610. Peripheral circuitry 610 permits various peripheral devices 624 to interface processor-memory bus 620 over input/output (I/O) bus 622. The personal computer shown in FIGS. 5 and 6 also includes at least one transistor having a gate oxide according to the teachings of the present invention.

Microprocessor 606 produces control and address signals to control the exchange of data between memory bus circuit 608 and microprocessor 606 and between memory bus circuit 608 and peripheral circuitry 610. This exchange of data is accomplished over high speed memory bus 620 and over high speed I/O bus 622.

Coupled to memory bus 620 are a plurality of memory slots 612(a–n) which receive memory devices well known to those skilled in the art. For example, single in-line memory modules (SIMMs) and dual in-line memory modules (DIMMs) may be used in the implementation of the present invention.

These memory devices can be produced in a variety of designs which provide different methods of reading from and writing to the dynamic memory cells of memory slots 612. One such method is the page mode operation. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell arrays and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed. Page mode DRAMs require access steps which limit the communication speed of memory circuit 608. A typical communication speed for a DRAM device using page mode is approximately 33 MHZ.

An alternate type of device is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. This memory can increase some communication speeds by allowing shorter access signals without reducing the time in which memory output data is available on memory bus 620. Other alternative types of devices include SDRAM, DDR SDRAM, SLDRAM and Direct RDRAM as well as others such as SRAM or Flash memories.

FIG. 7 is a block diagram of an illustrative DRAM device 700 compatible with memory slots 612(a–n). The description of DRAM 700 has been simplified for purposes of illustrating a DRAM memory device and is not intended to be a complete description of all the features of a DRAM. Those skilled in the art will recognize that a wide variety of memory devices may be used in the implementation of the present invention. The example of a DRAM memory device shown in FIG. 7 includes at least one transistor having a gate oxide according to the teachings of the present invention.

Control, address and data information provided over memory bus 620 is further represented by individual inputs to DRAM 700, as shown in FIG. 7. These individual representations are illustrated by data lines 702, address lines 704 and various discrete lines directed to control logic 706.

As is well known in the art, DRAM 700 includes memory array 710 which in turn comprises rows and columns of addressable memory cells. Each memory cell in a row is coupled to a common wordline. Additionally, each memory cell in a column is coupled to a common bitline. Each cell in memory array 710 includes a storage capacitor and an access transistor as is conventional in the art.

DRAM 700 interfaces with, for example, microprocessor 606 through address lines 704 and data lines 702. Alternatively, DRAM 700 may interface with a DRAM controller, a micro-controller, a chip set or other electronic system. Microprocessor 606 also provides a number of control signals to DRAM 700, including but not limited to, row and column address strobe signals RAS and CAS, write enable signal WE, an output enable signal OE and other conventional control signals.

Row address buffer 712 and row decoder 714 receive and decode row addresses from row address signals provided on address lines 704 by microprocessor 606. Each unique row address corresponds to a row of cells in memory array 710. Row decoder 714 includes a wordline driver, an address decoder tree, and circuitry which translates a given row address received from row address buffers 712 and selectively activates the appropriate wordline of memory array 710 via the wordline drivers.

Column address buffer 716 and column decoder 718 receive and decode column address signals provided on address lines 704. Column decoder 718 also determines when a column is defective and the address of a replacement column. Column decoder 718 is coupled to sense amplifiers 720. Sense amplifiers 720 are coupled to complementary pairs of bitlines of memory array 710.

Sense amplifiers 720 are coupled to data-in buffer 722 and data-out buffer 724. Data-in buffers 722 and data-out buffers 724 are coupled to data lines 702. During a write operation, data lines 702 provide data to data-in buffer 722. Sense amplifier 720 receives data from data-in buffer 722 and stores the data in memory array 710 as a charge on a capacitor of a cell at an address specified on address lines 704.

During a read operation, DRAM 700 transfers data to microprocessor 606 from memory array 710. Complementary bitlines for the accessed cell are equilibrated during a precharge operation to a reference voltage provided by an equilibration circuit and a reference voltage supply. The charge stored in the accessed cell is then shared with the associated bitlines. A sense amplifier of sense amplifiers 720 detects and amplifies a difference in voltage between the complementary bitlines. The sense amplifier passes the amplified voltage to data-out buffer 724.

Control logic 706 is used to control the many available functions of DRAM 700. In addition, various control circuits and signals not detailed herein initiate and synchronize DRAM 700 operation as known to those skilled in the art. As stated above, the description of DRAM 700 has been simplified for purposes of illustrating the present invention and is not intended to be a complete description of all the features of a DRAM. Those skilled in the art will recognize that a wide variety of memory devices, including but not limited to, SDRAMs, SLDRAMs, RDRAMs and other DRAMs and SRAMs, VRAMs and EEPROMs, may be used in the implementation of the present invention. The DRAM implementation described herein is illustrative only and not intended to be exclusive or limiting.

CONCLUSION

Thus has been shown a gate oxide and method of fabricating a gate oxide that produce a more reliable and thinner equivalent oxide thickness. Gate oxides formed from elements in group IVB of the periodic table are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. Zirconium oxide in particular has been shown to provide excellent electrical and thermodynamic properties. In addition to the stable thermodynamic properties inherent in the gate oxide of the invention, the process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures.

Transistors and higher level ICs or devices have been shown utilizing the novel gate oxide and process of formation. The higher dielectric constant (k) oxide materials shown in one embodiment are formed with an EOT thinner than 2 nm, e.g. thinner than possible with conventional SiO2 gate oxides. A thicker gate oxide that is more uniform, and easier to process has also been shown with at EOT equivalent to the current limits of SiO2 gate oxides. In one embodiment of the present invention, the novel gate oxide provides a conduction band offset in a range of approximately 5.16 eV to 7.8 eV.

A novel process of forming a gate oxide has been shown where the surface smoothness of the body region is preserved during processing, and the resulting transistor has a smooth interface between the body region and the gate oxide with a surface roughness on the order of 0.6 nm. This solves the prior art problem of poor electrical properties such as high leakage current, created by unacceptable surface roughness.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (28)

1. A transistor, comprising:
a first and second source/drain region;
a body region located between the first and second source/drain regions;
a substantially amorphous zirconium oxide dielectric layer directly coupled to the semiconductor surface portion of the body region having a surface roughness of approximately 0.6 nm; and
a gate coupled to the zirconium oxide dielectric layer.
2. The transistor of claim 1, wherein the zirconium oxide dielectric layer includes ZrO2.
3. The transistor of claim 1, wherein the surface portion of the body region is oriented in the (100) crystalline plane.
4. The transistor of claim 1, wherein the surface portion of the body region is oriented in the (111) crystalline plane.
5. The transistor of claim 1, wherein the zirconium oxide dielectric layer is substantially pure zirconium and oxygen to greater than 99.999%.
6. A memory array, comprising:
a number of access transistors, comprising:
a first and second source/drain region;
a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm;
a substantially amorphous zirconium oxide dielectric layer directly coupled to the semiconductor surface portion of the body region;
a gate coupled to the zirconium oxide dielectric layer;
a number of wordlines coupled to a number of the gates of the number of access transistors;
a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and
a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
7. The memory array of claim 6, wherein the zirconium oxide dielectric layer includes ZrO2.
8. The memory array of claim 6, wherein the zirconium oxide dielectric layer exhibits a dielectric constant (k) of approximately 25.
9. The memory array of claim 6, wherein the zirconium oxide dielectric layer is substantially pure zirconium and oxygen to greater than 99.999%.
10. An information handling device, comprising:
a processor;
a memory array, comprising:
a number of access transistors, comprising:
a first and second source/drain region;
a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm;
a substantially amorphous zirconium oxide dielectric layer directly coupled to the semiconductor surface portion of the body region;
a gate coupled to the zirconium oxide dielectric layer;
a number of wordlines coupled to a number of the gates of the number of access transistors;
a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and
a system bus coupling the processor to the memory device.
11. The information handling device of claim 10, wherein the zirconium oxide dielectric layer includes ZrO2.
12. The information handling device of claim 10, wherein the zirconium oxide dielectric layer exhibits a dielectric constant (k) of approximately 25.
13. The information handling device of claim 10, wherein the zirconium oxide dielectric layer is substantially pure zirconium and oxygen to greater than 99.999%.
14. A transistor, comprising:
a first and second source/drain region;
a body region located between the first and second source/drain regions;
a substantially amorphous group IVB oxide dielectric layer having a surface roughness of approximately 0.6 nm directly coupled to the semiconductor surface portion of the body region, wherein the oxide dielectric layer has a conduction band offset in a range of approximately 5.16eV to 7.8 eV; and
a gate coupled to the group IVB oxide dielectric layer.
15. The transistor of claim 14, wherein the dielectric layer includes ZrO2.
16. The transistor of claim 14, wherein the surface portion of the body region is oriented in the (100) crystalline plane.
17. The transistor of claim 14, wherein the surface portion of the body region is oriented in the (111) crystalline plane.
18. The transistor of claim 14, wherein the dielectric layer is substantially a pure group 1VB metal and oxygen to greater than 99.999%.
19. A transistor, comprising:
a semiconductor substrate having a first impurity type and a surface having a roughness of less than 0.6nm;
at least two diffused regions having a second impurity type;
a conductive gate disposed between the at least two diffused regions and separated from the semiconductor substrate by a non-crystalline dielectric layer; and
the dielectric layer having a dielectric constant greater than 10, and a thickness greater than 5.0 nm in direct contact with the semiconductor substrate.
20. The transistor of claim 19 wherein the dielectric layer comprises an oxidized metal selected from the periodic table group IVB.
21. The transistor of claim 20 wherein the oxidized metal comprises zirconium (Zr) oxide.
22. The transistor of claim 21 wherein the zirconium oxide comprises zirconium dioxide (ZrO2).
23. The transistor of claim 22 wherein the dielectric layer comprises substantially pure zirconium and oxygen to greater than 99.999%.
24. The transistor of claim 23 wherein the zirconium dioxide exhibits a dielectric constant (k) of approximately 25.
25. The transistor of claim 23 wherein the zirconium dioxide exhibits a conduction band offset in a range of approximately 5.16 eV to 7.8 eV.
26. The transistor of claim 19 wherein the dielectric layer exhibits electrical properties approximately equal to an equivalent silicon dioxide layer thickness of less than 2.0nm.
27. The transistor of claim 19 wherein the semiconductor substrate surface is oriented in the (100) crystalline plane.
28. The transistor of claim 19 wherein the semiconductor substrate surface is oriented in the (111) crystalline plane.
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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060115993A1 (en) * 2002-09-10 2006-06-01 Samsung Electronics Co., Ltd. Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices
US20090174010A1 (en) * 2008-01-03 2009-07-09 International Business Machines Corporation Sram device structure including same band gap transistors having gate stacks with high-k dielectrics and same work function
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7682913B1 (en) 2009-01-26 2010-03-23 International Business Machines Corporation Process for making a MCSFET
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7719065B2 (en) 2004-08-26 2010-05-18 Micron Technology, Inc. Ruthenium layer for a dielectric layer containing a lanthanide oxide
US7727905B2 (en) 2004-08-02 2010-06-01 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US20100258881A1 (en) * 2009-04-14 2010-10-14 International Business Machines Corporation Dual metal and dual dielectric integration for metal high-k fets
US7867919B2 (en) 2004-08-31 2011-01-11 Micron Technology, Inc. Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer
US7923381B2 (en) 2002-12-04 2011-04-12 Micron Technology, Inc. Methods of forming electronic devices containing Zr-Sn-Ti-O films
US8084808B2 (en) 2005-04-28 2011-12-27 Micron Technology, Inc. Zirconium silicon oxide films
US8154066B2 (en) 2004-08-31 2012-04-10 Micron Technology, Inc. Titanium aluminum oxide films
US8278225B2 (en) 2005-01-05 2012-10-02 Micron Technology, Inc. Hafnium tantalum oxide dielectrics
US8445952B2 (en) 2002-12-04 2013-05-21 Micron Technology, Inc. Zr-Sn-Ti-O films
US8652957B2 (en) 2001-08-30 2014-02-18 Micron Technology, Inc. High-K gate dielectric oxide
US9741918B2 (en) 2013-10-07 2017-08-22 Hypres, Inc. Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6852167B2 (en) * 2001-03-01 2005-02-08 Micron Technology, Inc. Methods, systems, and apparatus for uniform chemical-vapor depositions
US7476925B2 (en) * 2001-08-30 2009-01-13 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators
US7068544B2 (en) * 2001-08-30 2006-06-27 Micron Technology, Inc. Flash memory with low tunnel barrier interpoly insulators
US6900122B2 (en) * 2001-12-20 2005-05-31 Micron Technology, Inc. Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics
US7160577B2 (en) 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7045430B2 (en) * 2002-05-02 2006-05-16 Micron Technology Inc. Atomic layer-deposited LaAlO3 films for gate dielectrics
US7135421B2 (en) * 2002-06-05 2006-11-14 Micron Technology, Inc. Atomic layer-deposited hafnium aluminum oxide
US7205218B2 (en) * 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US7221586B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide nanolaminates
US6921702B2 (en) * 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US6884739B2 (en) * 2002-08-15 2005-04-26 Micron Technology Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
US6790791B2 (en) * 2002-08-15 2004-09-14 Micron Technology, Inc. Lanthanide doped TiOx dielectric films
US7199023B2 (en) * 2002-08-28 2007-04-03 Micron Technology, Inc. Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
US7084078B2 (en) * 2002-08-29 2006-08-01 Micron Technology, Inc. Atomic layer deposited lanthanide doped TiOx dielectric films
US7192892B2 (en) * 2003-03-04 2007-03-20 Micron Technology, Inc. Atomic layer deposited dielectric layers
US7135369B2 (en) * 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US7183186B2 (en) * 2003-04-22 2007-02-27 Micro Technology, Inc. Atomic layer deposited ZrTiO4 films
US7192824B2 (en) * 2003-06-24 2007-03-20 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectric layers
US7049192B2 (en) * 2003-06-24 2006-05-23 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectrics
US7384727B2 (en) * 2003-06-26 2008-06-10 Micron Technology, Inc. Semiconductor processing patterning methods
US7115532B2 (en) * 2003-09-05 2006-10-03 Micron Technolgoy, Inc. Methods of forming patterned photoresist layers over semiconductor substrates
US6969677B2 (en) 2003-10-20 2005-11-29 Micron Technology, Inc. Methods of forming conductive metal silicides by reaction of metal with silicon
US7026243B2 (en) * 2003-10-20 2006-04-11 Micron Technology, Inc. Methods of forming conductive material silicides by reaction of metal with silicon
US7030448B2 (en) * 2004-01-12 2006-04-18 Applied Intellectual Properties Co., Ltd. Mask ROM and the method of forming the same and the scheme of reading the device
US7153769B2 (en) * 2004-04-08 2006-12-26 Micron Technology, Inc. Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal with silicon
US7119031B2 (en) * 2004-06-28 2006-10-10 Micron Technology, Inc. Methods of forming patterned photoresist layers over semiconductor substrates
US7241705B2 (en) * 2004-09-01 2007-07-10 Micron Technology, Inc. Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
US7235501B2 (en) * 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
US20060125030A1 (en) * 2004-12-13 2006-06-15 Micron Technology, Inc. Hybrid ALD-CVD of PrxOy/ZrO2 films as gate dielectrics
US7508648B2 (en) * 2005-02-08 2009-03-24 Micron Technology, Inc. Atomic layer deposition of Dy doped HfO2 films as gate dielectrics
US7374964B2 (en) * 2005-02-10 2008-05-20 Micron Technology, Inc. Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics
US7399666B2 (en) * 2005-02-15 2008-07-15 Micron Technology, Inc. Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectrics
US7498247B2 (en) 2005-02-23 2009-03-03 Micron Technology, Inc. Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics
US7365027B2 (en) * 2005-03-29 2008-04-29 Micron Technology, Inc. ALD of amorphous lanthanide doped TiOx films
US7572695B2 (en) * 2005-05-27 2009-08-11 Micron Technology, Inc. Hafnium titanium oxide films
US7510983B2 (en) * 2005-06-14 2009-03-31 Micron Technology, Inc. Iridium/zirconium oxide structure
US20070045752A1 (en) * 2005-08-31 2007-03-01 Leonard Forbes Self aligned metal gates on high-K dielectrics
US7195999B2 (en) * 2005-07-07 2007-03-27 Micron Technology, Inc. Metal-substituted transistor gates
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7393736B2 (en) * 2005-08-29 2008-07-01 Micron Technology, Inc. Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics
US20070049023A1 (en) * 2005-08-29 2007-03-01 Micron Technology, Inc. Zirconium-doped gadolinium oxide films
US7544596B2 (en) 2005-08-30 2009-06-09 Micron Technology, Inc. Atomic layer deposition of GdScO3 films as gate dielectrics
US7410910B2 (en) * 2005-08-31 2008-08-12 Micron Technology, Inc. Lanthanum aluminum oxynitride dielectric films
US8071476B2 (en) 2005-08-31 2011-12-06 Micron Technology, Inc. Cobalt titanium oxide dielectric films
US7972974B2 (en) 2006-01-10 2011-07-05 Micron Technology, Inc. Gallium lanthanide oxide films
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7582161B2 (en) * 2006-04-07 2009-09-01 Micron Technology, Inc. Atomic layer deposited titanium-doped indium oxide films
US7727908B2 (en) * 2006-08-03 2010-06-01 Micron Technology, Inc. Deposition of ZrA1ON films
US7985995B2 (en) * 2006-08-03 2011-07-26 Micron Technology, Inc. Zr-substituted BaTiO3 films
US7749879B2 (en) * 2006-08-03 2010-07-06 Micron Technology, Inc. ALD of silicon films on germanium
US7582549B2 (en) * 2006-08-25 2009-09-01 Micron Technology, Inc. Atomic layer deposited barium strontium titanium oxide films
US7605030B2 (en) 2006-08-31 2009-10-20 Micron Technology, Inc. Hafnium tantalum oxynitride high-k dielectric and metal gates
US7759747B2 (en) 2006-08-31 2010-07-20 Micron Technology, Inc. Tantalum aluminum oxynitride high-κ dielectric
US7563730B2 (en) 2006-08-31 2009-07-21 Micron Technology, Inc. Hafnium lanthanide oxynitride films
US7776765B2 (en) * 2006-08-31 2010-08-17 Micron Technology, Inc. Tantalum silicon oxynitride high-k dielectrics and metal gates
US7544604B2 (en) * 2006-08-31 2009-06-09 Micron Technology, Inc. Tantalum lanthanide oxynitride films
US7432548B2 (en) * 2006-08-31 2008-10-07 Micron Technology, Inc. Silicon lanthanide oxynitride films
US20080057659A1 (en) * 2006-08-31 2008-03-06 Micron Technology, Inc. Hafnium aluminium oxynitride high-K dielectric and metal gates
US20080087890A1 (en) * 2006-10-16 2008-04-17 Micron Technology, Inc. Methods to form dielectric structures in semiconductor devices and resulting devices
US8367506B2 (en) * 2007-06-04 2013-02-05 Micron Technology, Inc. High-k dielectrics with gold nano-particles
JPWO2013073671A1 (en) * 2011-11-17 2015-04-02 国立大学法人東北大学 Semiconductor device and manufacturing method thereof
KR20140032716A (en) 2012-09-07 2014-03-17 삼성전자주식회사 Semiconductor device and method for fabricating thereof
WO2015142295A1 (en) 2014-03-20 2015-09-24 Institut "Jozef Stefan" Method for synthesis of tetragonal zirconia thin films suitable for catalytic devices

Citations (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3381114A (en) 1963-12-28 1968-04-30 Nippon Electric Co Device for manufacturing epitaxial crystals
US4058430A (en) 1974-11-29 1977-11-15 Tuomo Suntola Method for producing compound thin films
US4215156A (en) 1977-08-26 1980-07-29 International Business Machines Corporation Method for fabricating tantalum semiconductor contacts
US4333808A (en) 1979-10-30 1982-06-08 International Business Machines Corporation Method for manufacture of ultra-thin film capacitor
US4394673A (en) 1980-09-29 1983-07-19 International Business Machines Corporation Rare earth silicide Schottky barriers
US4399424A (en) 1980-10-07 1983-08-16 Itt Industries, Inc. Gas sensor
US4413022A (en) 1979-02-28 1983-11-01 Canon Kabushiki Kaisha Method for performing growth of compound thin films
US4590042A (en) 1984-12-24 1986-05-20 Tegal Corporation Plasma reactor having slotted manifold
US4647947A (en) 1982-03-15 1987-03-03 Tokyo Shibaura Denki Kabushiki Kaisha Optical protuberant bubble recording medium
US4725877A (en) 1986-04-11 1988-02-16 American Telephone And Telegraph Company, At&T Bell Laboratories Metallized semiconductor device including an interface layer
US4767641A (en) 1986-03-04 1988-08-30 Leybold-Heraeus Gmbh Plasma treatment apparatus
US4920071A (en) 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
US4993358A (en) 1989-07-28 1991-02-19 Watkins-Johnson Company Chemical vapor deposition reactor and method of operation
US5006192A (en) 1988-06-28 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Apparatus for producing semiconductor devices
US5049516A (en) 1987-12-02 1991-09-17 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor memory device
US5055319A (en) 1990-04-02 1991-10-08 The Regents Of The University Of California Controlled high rate deposition of metal oxide films
US5080928A (en) 1990-10-05 1992-01-14 Gte Laboratories Incorporated Method for making moisture insensitive zinc sulfide based luminescent materials
US5198029A (en) 1989-08-01 1993-03-30 Gte Products Corporation Apparatus for coating small solids
US5302461A (en) 1992-06-05 1994-04-12 Hewlett-Packard Company Dielectric films for use in magnetoresistive transducers
US5426603A (en) 1993-01-25 1995-06-20 Hitachi, Ltd. Dynamic RAM and information processing system using the same
US5562952A (en) 1993-11-11 1996-10-08 Nissin Electric Co., Ltd. Plasma-CVD method and apparatus
US5572052A (en) 1992-07-24 1996-11-05 Mitsubishi Denki Kabushiki Kaisha Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer
US5595606A (en) 1995-04-20 1997-01-21 Tokyo Electron Limited Shower head and film forming apparatus using the same
US5621681A (en) 1995-03-22 1997-04-15 Samsung Electronics Co., Ltd. Device and manufacturing method for a ferroelectric memory
US5625233A (en) 1995-01-13 1997-04-29 Ibm Corporation Thin film multi-layer oxygen diffusion barrier consisting of refractory metal, refractory metal aluminide, and aluminum oxide
US5646583A (en) 1996-01-04 1997-07-08 Rockwell International Corporation Acoustic isolator having a high impedance layer of hafnium oxide
US5674563A (en) 1993-09-14 1997-10-07 Nissan Motor Co., Ltd. Method for ferroelectric thin film production
US5698022A (en) 1996-08-14 1997-12-16 Advanced Technology Materials, Inc. Lanthanide/phosphorus precursor compositions for MOCVD of lanthanide/phosphorus oxide films
US5735960A (en) 1996-04-02 1998-04-07 Micron Technology, Inc. Apparatus and method to increase gas residence time in a reactor
US5751021A (en) 1995-04-24 1998-05-12 Sharp Kk Semiconductor light-emitting device
US5789030A (en) 1996-03-18 1998-08-04 Micron Technology, Inc. Method for depositing doped amorphous or polycrystalline silicon on a substrate
US5795808A (en) 1995-11-13 1998-08-18 Hyundai Electronics Industries C., Ltd. Method for forming shallow junction for semiconductor device
US5801105A (en) 1995-08-04 1998-09-01 Tdk Corporation Multilayer thin film, substrate for electronic device, electronic device, and preparation of multilayer oxide thin film
US5810923A (en) 1994-08-17 1998-09-22 Tdk Corporation Method for forming oxide thin film and the treatment of silicon substrate
US5822256A (en) 1994-09-06 1998-10-13 Intel Corporation Method and circuitry for usage of partially functional nonvolatile memory
US5827571A (en) 1994-06-08 1998-10-27 Hyundai Electronics Industries Co., Ltd. Hot-wall CVD method for forming a ferroelectric film
US5840897A (en) 1990-07-06 1998-11-24 Advanced Technology Materials, Inc. Metal complex source reagents for chemical vapor deposition
US5912797A (en) 1997-09-24 1999-06-15 Lucent Technologies Inc. Dielectric materials of amorphous compositions and devices employing same
US5916365A (en) 1996-08-16 1999-06-29 Sherman; Arthur Sequential chemical vapor deposition
US5923056A (en) 1996-10-10 1999-07-13 Lucent Technologies Inc. Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials
US5950925A (en) 1996-10-11 1999-09-14 Ebara Corporation Reactant gas ejector head
US5972847A (en) 1998-01-28 1999-10-26 Lockheed Martin Energy Method for making high-critical-current-density YBa2 Cu3 O7 superconducting layers on metallic substrates
US5981350A (en) 1998-05-29 1999-11-09 Micron Technology, Inc. Method for forming high capacitance memory cells
US6010969A (en) 1996-10-02 2000-01-04 Micron Technology, Inc. Method of depositing films on semiconductor devices by using carboxylate complexes
US6013553A (en) 1997-07-24 2000-01-11 Texas Instruments Incorporated Zirconium and/or hafnium oxynitride gate dielectric
US6020024A (en) 1997-08-04 2000-02-01 Motorola, Inc. Method for forming high dielectric constant metal oxides
US6025225A (en) 1998-01-22 2000-02-15 Micron Technology, Inc. Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same
US6025627A (en) 1998-05-29 2000-02-15 Micron Technology, Inc. Alternate method and structure for improved floating gate tunneling devices
US6027961A (en) 1998-06-30 2000-02-22 Motorola, Inc. CMOS semiconductor devices and method of formation
US6040243A (en) 1999-09-20 2000-03-21 Chartered Semiconductor Manufacturing Ltd. Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion
US6057271A (en) 1989-12-22 2000-05-02 Sumitomo Electric Industries, Ltd. Method of making a superconducting microwave component by off-axis sputtering
US6059885A (en) 1996-12-19 2000-05-09 Toshiba Ceramics Co., Ltd. Vapor deposition apparatus and method for forming thin film
US6090636A (en) 1998-02-26 2000-07-18 Micron Technology, Inc. Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same
US6093944A (en) 1998-06-04 2000-07-25 Lucent Technologies Inc. Dielectric materials of amorphous compositions of TI-O2 doped with rare earth elements and devices employing same
US6110529A (en) 1990-07-06 2000-08-29 Advanced Tech Materials Method of forming metal films on a substrate by chemical vapor deposition
US6115401A (en) 1996-02-13 2000-09-05 Corning Oca Corporation External cavity semiconductor laser with monolithic prism assembly
US6120531A (en) 1987-05-20 2000-09-19 Micron, Technology Physiotherapy fiber, shoes, fabric, and clothes utilizing electromagnetic energy
US6134175A (en) 1998-08-04 2000-10-17 Micron Technology, Inc. Memory address decode array with vertical transistors
US6150188A (en) 1998-02-26 2000-11-21 Micron Technology Inc. Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same
US6161500A (en) 1997-09-30 2000-12-19 Tokyo Electron Limited Apparatus and method for preventing the premature mixture of reactant gases in CVD and PECVD reactions
US6171900B1 (en) 1999-04-15 2001-01-09 Taiwan Semiconductor Manufacturing Company CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET
US6187484B1 (en) 1999-08-31 2001-02-13 Micron Technology, Inc. Irradiation mask
US6191448B1 (en) 1997-07-08 2001-02-20 Micron Technology, Inc. Memory cell with vertical transistor and buried word and body lines
US6198168B1 (en) 1998-01-20 2001-03-06 Micron Technologies, Inc. Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same
US6203726B1 (en) 1997-03-04 2001-03-20 Symyx Technologies, Inc. Phosphor Materials
US6203613B1 (en) 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US6206972B1 (en) 1999-07-08 2001-03-27 Genus, Inc. Method and apparatus for providing uniform gas delivery to substrates in CVD and PECVD processes
US6207589B1 (en) 1999-07-19 2001-03-27 Sharp Laboratories Of America, Inc. Method of forming a doped metal oxide dielectric film
US6211035B1 (en) 1998-09-09 2001-04-03 Texas Instruments Incorporated Integrated circuit and method
US6225168B1 (en) 1998-06-04 2001-05-01 Advanced Micro Devices, Inc. Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof
US6225237B1 (en) 1998-09-01 2001-05-01 Micron Technology, Inc. Method for forming metal-containing films using metal complexes with chelating O- and/or N-donor ligands
US6232847B1 (en) 1997-04-28 2001-05-15 Rockwell Science Center, Llc Trimmable singleband and tunable multiband integrated oscillator using micro-electromechanical system (MEMS) technology
US6273951B1 (en) 1999-06-16 2001-08-14 Micron Technology, Inc. Precursor mixtures for use in preparing layers on substrates
US6281144B1 (en) 1997-09-26 2001-08-28 Novellus Systems, Inc. Exclusion of polymer film from semiconductor wafer edge and backside during film (CVD) deposition
US6297539B1 (en) 1999-07-19 2001-10-02 Sharp Laboratories Of America, Inc. Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same
US6297516B1 (en) 1997-11-24 2001-10-02 The Trustees Of Princeton University Method for deposition and patterning of organic thin film
US6296943B1 (en) 1994-03-05 2001-10-02 Nissan Chemical Industries, Ltd. Method for producing composite sol, coating composition, and optical element
US6300203B1 (en) 2000-10-05 2001-10-09 Advanced Micro Devices, Inc. Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors
US6303481B2 (en) 1999-12-29 2001-10-16 Hyundai Electronics Industries Co., Ltd. Method for forming a gate insulating film for semiconductor devices
US6302964B1 (en) 1998-06-16 2001-10-16 Applied Materials, Inc. One-piece dual gas faceplate for a showerhead in a semiconductor wafer processing system
US6317357B1 (en) 1998-02-24 2001-11-13 Micron Technology, Inc. Vertical bipolar read access for low voltage memory cell
US6348386B1 (en) 2001-04-16 2002-02-19 Motorola, Inc. Method for making a hafnium-based insulating film
US6365470B1 (en) 2000-08-24 2002-04-02 Secretary Of Agency Of Industrial Science And Technology Method for manufacturing self-matching transistor
US6368941B1 (en) 2000-11-08 2002-04-09 United Microelectronics Corp. Fabrication of a shallow trench isolation by plasma oxidation
US6368518B1 (en) 1999-08-25 2002-04-09 Micron Technology, Inc. Methods for removing rhodium- and iridium-containing films
US6381168B2 (en) 1998-04-14 2002-04-30 Micron Technology, Inc. Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
US6380579B1 (en) 1999-04-12 2002-04-30 Samsung Electronics Co., Ltd. Capacitor of semiconductor device
US6387712B1 (en) 1996-06-26 2002-05-14 Tdk Corporation Process for preparing ferroelectric thin films
US6391769B1 (en) 1998-08-19 2002-05-21 Samsung Electronics Co., Ltd. Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby
US6399979B1 (en) 1997-07-08 2002-06-04 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
US6404027B1 (en) 2000-02-07 2002-06-11 Agere Systems Guardian Corp. High dielectric constant gate oxides for silicon-based devices

Family Cites Families (250)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2501563A (en) 1946-02-20 1950-03-21 Libbey Owens Ford Glass Co Method of forming strongly adherent metallic compound films by glow discharge
GB8423324D0 (en) * 1984-09-14 1984-10-17 Philips Electronic Associated Processing video signals
EP0540993A1 (en) 1991-11-06 1993-05-12 Ramtron International Corporation Structure and fabrication of high transconductance MOS field effect transistor using a buffer layer/ferroelectric/buffer layer stack as the gate dielectric
DE69221283D1 (en) 1992-01-08 1997-09-04 Nippon Oil Co Ltd A process for preparing polysilanes
JPH07263751A (en) 1994-03-24 1995-10-13 Sharp Corp Ii-vi compound semiconductor device and manufacture of it
US5478653A (en) 1994-04-04 1995-12-26 Guenzer; Charles S. Bismuth titanate as a template layer for growth of crystallographically oriented silicon
US5814584A (en) 1995-06-30 1998-09-29 The United States Of America As Represented By The Secretary Of The Army Compound in the series A2 MeSbO6 for use as substrates barrier-dielectric layers and passivating layers in high critical temperature superconducting devices
US5745334A (en) 1996-03-25 1998-04-28 International Business Machines Corporation Capacitor formed within printed circuit board
US5765214A (en) 1996-04-22 1998-06-09 Cypress Semiconductor Corporation Memory access method and apparatus and multi-plane memory device with prefetch
US5877860A (en) 1996-05-13 1999-03-02 Boxer Cross, Inc. System and method for measuring the microroughness of a surface of a substrate
US6173379B1 (en) 1996-05-14 2001-01-09 Intel Corporation Memory device for a microprocessor register file having a power management scheme and method for copying information between memory sub-cells in a single clock cycle
US6313035B1 (en) 1996-05-31 2001-11-06 Micron Technology, Inc. Chemical vapor deposition using organometallic precursors
US5777923A (en) 1996-06-17 1998-07-07 Aplus Integrated Circuits, Inc. Flash memory read/write controller
US6020247A (en) 1996-08-05 2000-02-01 Texas Instruments Incorporated Method for thin film deposition on single-crystal semiconductor substrates
US5926730A (en) 1997-02-19 1999-07-20 Micron Technology, Inc. Conductor layer nitridation
DE19709002A1 (en) 1997-03-05 1998-09-24 Siemens Ag Bridged doped zone manufacturing method e.g. for DMOS transistor
US6075691A (en) 1997-03-06 2000-06-13 Lucent Technologies Inc. Thin film capacitors and process for making them
US6699745B1 (en) 1997-03-27 2004-03-02 Texas Instruments Incorporated Capacitor and memory structure and method
US6309595B1 (en) * 1997-04-30 2001-10-30 The Altalgroup, Inc Titanium crystal and titanium
US6034015A (en) 1997-05-14 2000-03-07 Georgia Tech Research Corporation Ceramic compositions for microwave wireless communication
US6072209A (en) 1997-07-08 2000-06-06 Micro Technology, Inc. Four F2 folded bit line DRAM cell structure having buried bit and word lines
US6191470B1 (en) 1997-07-08 2001-02-20 Micron Technology, Inc. Semiconductor-on-insulator memory cell with buried word and body lines
US6066869A (en) 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
KR100269328B1 (en) 1997-12-31 2000-10-16 윤종용 Method for forming conductive layer using atomic layer deposition process
US5991225A (en) 1998-02-27 1999-11-23 Micron Technology, Inc. Programmable memory address decode array with vertical transistors
US6124729A (en) 1998-02-27 2000-09-26 Micron Technology, Inc. Field programmable logic arrays with vertical transistors
US6287673B1 (en) 1998-03-03 2001-09-11 Acktar Ltd. Method for producing high surface area foil electrodes
FR2779751B1 (en) 1998-06-10 2003-11-14 Saint Gobain Isover Substrate has photocatalytic coating
US6208164B1 (en) 1998-08-04 2001-03-27 Micron Technology, Inc. Programmable logic array with vertical transistors
US6093623A (en) 1998-08-04 2000-07-25 Micron Technology, Inc. Methods for making silicon-on-insulator structures
US5999454A (en) 1998-08-19 1999-12-07 Lucent Technologies, Inc. Sense amplifier for flash memory
US6352777B1 (en) 1998-08-19 2002-03-05 The Trustees Of Princeton University Organic photosensitive optoelectronic devices with transparent electrodes
WO2000019500A1 (en) 1998-09-25 2000-04-06 Asahi Kasei Kabushiki Kaisha Semiconductor substrate and its production method, semiconductor device comprising the same and its production method
DE19844085C1 (en) * 1998-09-25 2000-03-16 Siemens Ag Combustion engine control method
DE69940335D1 (en) 1998-09-28 2009-03-12 Nec Electronics Corp Apparatus and method for non-destructive testing of a semiconductor device
WO2000026973A1 (en) 1998-11-02 2000-05-11 Presstek, Inc. Transparent conductive oxides for plastic flat panel displays
US6433993B1 (en) 1998-11-23 2002-08-13 Microcoating Technologies, Inc. Formation of thin film capacitors
US6207522B1 (en) * 1998-11-23 2001-03-27 Microcoating Technologies Formation of thin film capacitors
JP2000208508A (en) 1999-01-13 2000-07-28 Texas Instr Inc <Ti> Vacuum deposition of high-dielectric material made of silicate
US6383861B1 (en) 1999-02-18 2002-05-07 Micron Technology, Inc. Method of fabricating a dual gate dielectric
US6200893B1 (en) 1999-03-11 2001-03-13 Genus, Inc Radical-assisted sequential CVD
US6445023B1 (en) 1999-03-16 2002-09-03 Micron Technology, Inc. Mixed metal nitride and boride barrier layers
US6498362B1 (en) 1999-08-26 2002-12-24 Micron Technology, Inc. Weak ferroelectric transistor
US6653209B1 (en) 1999-09-30 2003-11-25 Canon Kabushiki Kaisha Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device
US6270835B1 (en) 1999-10-07 2001-08-07 Microcoating Technologies, Inc. Formation of this film capacitors
FI117942B (en) 1999-10-14 2007-04-30 Asm Int The method of growing oksidiohutkalvojen
FI118158B (en) 1999-10-15 2007-07-31 Asm Int Process for the modification of precursor chemicals in an ALD litigation
KR100304714B1 (en) 1999-10-20 2001-11-02 윤종용 Method for fabricating metal layer of semiconductor device using metal-halide gas
KR100350575B1 (en) 1999-11-05 2002-08-28 주식회사 하이닉스반도체 Silicon on insulator having source-body-substrate contact and method for fabricating the same
JP4397491B2 (en) 1999-11-30 2010-01-13 財団法人国際科学振興財団 Semiconductor device and method for forming silicon having (111) face orientation on the surface
US6780704B1 (en) 1999-12-03 2004-08-24 Asm International Nv Conformal thin films over textured capacitor electrodes
US20010053082A1 (en) 1999-12-22 2001-12-20 Makarand H. Chipalkatti Electroluminescent vehicle lamp
US6429120B1 (en) 2000-01-18 2002-08-06 Micron Technology, Inc. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
FI20000099A0 (en) 2000-01-18 2000-01-18 Asm Microchemistry Ltd The method of growing metal thin films
US6437425B1 (en) 2000-01-18 2002-08-20 Agere Systems Guardian Corp Semiconductor devices which utilize low K dielectrics
WO2001054200A1 (en) 2000-01-19 2001-07-26 North Carolina State University Lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors and methods of fabricating same
US6527866B1 (en) 2000-02-09 2003-03-04 Conductus, Inc. Apparatus and method for deposition of thin films
US6392257B1 (en) 2000-02-10 2002-05-21 Motorola Inc. Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
US6407435B1 (en) 2000-02-11 2002-06-18 Sharp Laboratories Of America, Inc. Multilayer dielectric stack and method
DE10010821A1 (en) 2000-02-29 2001-09-13 Infineon Technologies Ag Increasing capacity in a storage trench comprises depositing a first silicon oxide layer in the trench, depositing a silicon layer over the first layer to sufficiently
WO2001064600A1 (en) 2000-03-01 2001-09-07 The Penn State Research Foundation Method for fabrication of lead based perovskite materials
US6444039B1 (en) 2000-03-07 2002-09-03 Simplus Systems Corporation Three-dimensional showerhead apparatus
US6537613B1 (en) 2000-04-10 2003-03-25 Air Products And Chemicals, Inc. Process for metal metalloid oxides and nitrides with compositional gradients
FI117979B (en) 2000-04-14 2007-05-15 Asm Int Process for the preparation of oksidiohutkalvojen
US6482740B2 (en) 2000-05-15 2002-11-19 Asm Microchemistry Oy Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH
US6432779B1 (en) 2000-05-18 2002-08-13 Motorola, Inc. Selective removal of a metal oxide dielectric
US6794281B2 (en) 2002-05-20 2004-09-21 Freescale Semiconductor, Inc. Dual metal gate transistors for CMOS process
US6444592B1 (en) 2000-06-20 2002-09-03 International Business Machines Corporation Interfacial oxidation process for high-k gate dielectric process integration
JP4145509B2 (en) 2000-06-27 2008-09-03 三星電子株式会社Samsung Electronics Co.,Ltd. Method of manufacturing an integrated circuit device including an insulating film
EP1301941A2 (en) 2000-07-20 2003-04-16 North Carolina State University High dielectric constant metal silicates formed by controlled metal-surface reactions
DE10039327A1 (en) 2000-08-03 2002-02-14 Ihp Gmbh Electronic component and manufacturing processes for electronic component
US7112503B1 (en) 2000-08-31 2006-09-26 Micron Technology, Inc. Enhanced surface area capacitor fabrication methods
US6518634B1 (en) 2000-09-01 2003-02-11 Motorola, Inc. Strontium nitride or strontium oxynitride gate dielectric
US6602338B2 (en) 2000-09-18 2003-08-05 National Science Council Titanium dioxide film co-doped with yttrium and erbium and method for producing the same
EP1743949B1 (en) 2000-10-02 2012-02-15 JX Nippon Mining & Metals Corporation High-purity zirconium or hafnium metal for sputter targets and thin film applications
US6465334B1 (en) 2000-10-05 2002-10-15 Advanced Micro Devices, Inc. Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors
US6660660B2 (en) 2000-10-10 2003-12-09 Asm International, Nv. Methods for making a dielectric stack in an integrated circuit
US6395650B1 (en) 2000-10-23 2002-05-28 International Business Machines Corporation Methods for forming metal oxide layers with enhanced purity
JP3681632B2 (en) 2000-11-06 2005-08-10 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
US6613695B2 (en) 2000-11-24 2003-09-02 Asm America, Inc. Surface preparation prior to deposition
KR100385947B1 (en) 2000-12-06 2003-06-02 삼성전자주식회사 Method of forming thin film by atomic layer deposition
JP2002198525A (en) 2000-12-27 2002-07-12 Toshiba Corp Semiconductor device and its manufacturing method
US6524867B2 (en) 2000-12-28 2003-02-25 Micron Technology, Inc. Method for forming platinum-rhodium stack as an oxygen barrier
KR20020056260A (en) 2000-12-29 2002-07-10 박종섭 Method for forming metal gate of semiconductor devoie
US20020089023A1 (en) 2001-01-05 2002-07-11 Motorola, Inc. Low leakage current metal oxide-nitrides and method of fabricating same
KR100385952B1 (en) 2001-01-19 2003-06-02 삼성전자주식회사 A semiconductor capacitor having tantalum oxide as dielctric film and formation method thereof
US7087482B2 (en) 2001-01-19 2006-08-08 Samsung Electronics Co., Ltd. Method of forming material using atomic layer deposition and method of forming capacitor of semiconductor device using the same
US6713846B1 (en) 2001-01-26 2004-03-30 Aviza Technology, Inc. Multilayer high κ dielectric films
US6528374B2 (en) 2001-02-05 2003-03-04 International Business Machines Corporation Method for forming dielectric stack without interfacial layer
US6495436B2 (en) 2001-02-09 2002-12-17 Micron Technology, Inc. Formation of metal oxide gate dielectric
US6518610B2 (en) 2001-02-20 2003-02-11 Micron Technology, Inc. Rhodium-rich oxygen barriers
KR100384558B1 (en) 2001-02-22 2003-05-22 삼성전자주식회사 Method for forming dielectric layer and capacitor using thereof
US6586792B2 (en) 2001-03-15 2003-07-01 Micron Technology, Inc. Structures, methods, and systems for ferroelectric memory transistors
US6454912B1 (en) 2001-03-15 2002-09-24 Micron Technology, Inc. Method and apparatus for the fabrication of ferroelectric films
US20050145959A1 (en) 2001-03-15 2005-07-07 Leonard Forbes Technique to mitigate short channel effects with vertical gate transistor with different gate materials
WO2002090614A1 (en) 2001-03-20 2002-11-14 Mattson Technology, Inc. Method for depositing a coating having a relatively high dielectric constant onto a substrate
US6541280B2 (en) 2001-03-20 2003-04-01 Motorola, Inc. High K dielectric film
US6441417B1 (en) 2001-03-28 2002-08-27 Sharp Laboratories Of America, Inc. Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same
JP3792589B2 (en) 2001-03-29 2006-07-05 富士通株式会社 A method of manufacturing a semiconductor device
US6448192B1 (en) 2001-04-16 2002-09-10 Motorola, Inc. Method for forming a high dielectric constant material
EP1251530A3 (en) 2001-04-16 2004-12-29 Shipley Company, L.L.C. Dielectric laminate for a capacitor
US6514828B2 (en) 2001-04-20 2003-02-04 Micron Technology, Inc. Method of fabricating a highly reliable gate oxide
US6465853B1 (en) 2001-05-08 2002-10-15 Motorola, Inc. Method for making semiconductor device
US6759081B2 (en) 2001-05-11 2004-07-06 Asm International, N.V. Method of depositing thin films for magnetic heads
US7037574B2 (en) 2001-05-23 2006-05-02 Veeco Instruments, Inc. Atomic layer deposition for fabricating thin films
US7037862B2 (en) 2001-06-13 2006-05-02 Micron Technology, Inc. Dielectric layer forming method and devices formed therewith
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6420279B1 (en) 2001-06-28 2002-07-16 Sharp Laboratories Of America, Inc. Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate
US20030008243A1 (en) 2001-07-09 2003-01-09 Micron Technology, Inc. Copper electroless deposition technology for ULSI metalization
US6534420B2 (en) 2001-07-18 2003-03-18 Micron Technology, Inc. Methods for forming dielectric materials and methods for forming semiconductor devices
US6919266B2 (en) 2001-07-24 2005-07-19 Micron Technology, Inc. Copper technology for ULSI metallization
US20030032270A1 (en) 2001-08-10 2003-02-13 John Snyder Fabrication method for a device for regulating flow of electric current with high dielectric constant gate insulating layer and source/drain forming schottky contact or schottky-like region with substrate
US7129128B2 (en) 2001-08-29 2006-10-31 Micron Technology, Inc. Method of improved high K dielectric-polysilicon interface for CMOS devices
US6461914B1 (en) 2001-08-29 2002-10-08 Motorola, Inc. Process for making a MIM capacitor
US7135734B2 (en) 2001-08-30 2006-11-14 Micron Technology, Inc. Graded composition metal oxide tunnel barrier interpoly insulators
US6730575B2 (en) 2001-08-30 2004-05-04 Micron Technology, Inc. Methods of forming perovskite-type material and capacitor dielectric having perovskite-type crystalline structure
US8026161B2 (en) * 2001-08-30 2011-09-27 Micron Technology, Inc. Highly reliable amorphous high-K gate oxide ZrO2
US7068544B2 (en) 2001-08-30 2006-06-27 Micron Technology, Inc. Flash memory with low tunnel barrier interpoly insulators
US7476925B2 (en) 2001-08-30 2009-01-13 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators
US7042043B2 (en) 2001-08-30 2006-05-09 Micron Technology, Inc. Programmable array logic or memory devices with asymmetrical tunnel barriers
US6778441B2 (en) 2001-08-30 2004-08-17 Micron Technology, Inc. Integrated circuit memory device and method
US6573199B2 (en) 2001-08-30 2003-06-03 Micron Technology, Inc. Methods of treating dielectric materials with oxygen, and methods of forming capacitor constructions
US7132711B2 (en) 2001-08-30 2006-11-07 Micron Technology, Inc. Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
US6754108B2 (en) 2001-08-30 2004-06-22 Micron Technology, Inc. DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US6844203B2 (en) 2001-08-30 2005-01-18 Micron Technology, Inc. Gate oxides, and methods of forming
US6806145B2 (en) 2001-08-31 2004-10-19 Asm International, N.V. Low temperature method of forming a gate stack with a high k layer deposited over an interfacial oxide layer
US20030059535A1 (en) 2001-09-25 2003-03-27 Lee Luo Cycling deposition of low temperature films in a cold wall single wafer process chamber
US7541005B2 (en) 2001-09-26 2009-06-02 Siemens Energy Inc. Catalytic thermal barrier coatings
US6605549B2 (en) 2001-09-29 2003-08-12 Intel Corporation Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics
US6720259B2 (en) * 2001-10-02 2004-04-13 Genus, Inc. Passivation method for improved uniformity and repeatability for atomic layer deposition and chemical vapor deposition
US6451662B1 (en) 2001-10-04 2002-09-17 International Business Machines Corporation Method of forming low-leakage on-chip capacitor
US7524528B2 (en) 2001-10-05 2009-04-28 Cabot Corporation Precursor compositions and methods for the deposition of passive electrical components on a substrate
US6498063B1 (en) 2001-10-12 2002-12-24 Micron Technology, Inc. Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth
US6559014B1 (en) 2001-10-15 2003-05-06 Advanced Micro Devices, Inc. Preparation of composite high-K / standard-K dielectrics for semiconductor devices
US6683011B2 (en) 2001-11-14 2004-01-27 Regents Of The University Of Minnesota Process for forming hafnium oxide films
US6593610B2 (en) 2001-12-13 2003-07-15 Micron Technology, Inc. Memory cell arrays
US6953730B2 (en) 2001-12-20 2005-10-11 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
US6900122B2 (en) 2001-12-20 2005-05-31 Micron Technology, Inc. Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics
US6696332B2 (en) 2001-12-26 2004-02-24 Texas Instruments Incorporated Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing
US6674138B1 (en) 2001-12-31 2004-01-06 Advanced Micro Devices, Inc. Use of high-k dielectric materials in modified ONO structure for semiconductor devices
FR2834387B1 (en) 2001-12-31 2004-02-27 Memscap electronic component incorporating integrated circuit and a micro-capacitor
US6821873B2 (en) 2002-01-10 2004-11-23 Texas Instruments Incorporated Anneal sequence for high-κ film property optimization
US6767795B2 (en) 2002-01-17 2004-07-27 Micron Technology, Inc. Highly reliable amorphous high-k gate dielectric ZrOXNY
US6645882B1 (en) 2002-01-17 2003-11-11 Advanced Micro Devices, Inc. Preparation of composite high-K/standard-K dielectrics for semiconductor devices
US6620670B2 (en) 2002-01-18 2003-09-16 Applied Materials, Inc. Process conditions and precursors for atomic layer deposition (ALD) of AL2O3
US20030141560A1 (en) 2002-01-25 2003-07-31 Shi-Chung Sun Incorporating TCS-SiN barrier layer in dual gate CMOS devices
US6989565B1 (en) 2002-04-15 2006-01-24 Lsi Logic Corporation Memory device having an electron trapping layer in a high-K dielectric gate stack
US6893984B2 (en) 2002-02-20 2005-05-17 Micron Technology Inc. Evaporated LaA1O3 films for gate dielectrics
US6900481B2 (en) 2002-02-21 2005-05-31 Intel Corporation Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors
US6586349B1 (en) 2002-02-21 2003-07-01 Advanced Micro Devices, Inc. Integrated process for fabrication of graded composite dielectric material layers for semiconductor devices
US6451641B1 (en) 2002-02-27 2002-09-17 Advanced Micro Devices, Inc. Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material
US6972267B2 (en) 2002-03-04 2005-12-06 Applied Materials, Inc. Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor
US6900106B2 (en) 2002-03-06 2005-05-31 Micron Technology, Inc. Methods of forming capacitor constructions
US6642573B1 (en) 2002-03-13 2003-11-04 Advanced Micro Devices, Inc. Use of high-K dielectric material in modified ONO structure for semiconductor devices
US6812100B2 (en) 2002-03-13 2004-11-02 Micron Technology, Inc. Evaporation of Y-Si-O films for medium-k dielectrics
JP4090347B2 (en) 2002-03-18 2008-05-28 株式会社日立国際電気 Manufacturing method and a substrate processing apparatus of a semiconductor device
JP3937892B2 (en) 2002-04-01 2007-06-27 日本電気株式会社 Method of manufacturing a thin film forming method and a semiconductor device
US6750066B1 (en) 2002-04-08 2004-06-15 Advanced Micro Devices, Inc. Precision high-K intergate dielectric layer
US20030235961A1 (en) 2002-04-17 2003-12-25 Applied Materials, Inc. Cyclical sequential deposition of multicomponent films
US7045430B2 (en) 2002-05-02 2006-05-16 Micron Technology Inc. Atomic layer-deposited LaAlO3 films for gate dielectrics
US7160577B2 (en) 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7589029B2 (en) 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US6784101B1 (en) 2002-05-16 2004-08-31 Advanced Micro Devices Inc Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
US6709926B2 (en) 2002-05-31 2004-03-23 International Business Machines Corporation High performance logic and high density embedded dram with borderless contact and antispacer
US7205218B2 (en) 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US7135421B2 (en) 2002-06-05 2006-11-14 Micron Technology, Inc. Atomic layer-deposited hafnium aluminum oxide
US7067439B2 (en) 2002-06-14 2006-06-27 Applied Materials, Inc. ALD metal oxide deposition process using direct oxidation
US6524901B1 (en) 2002-06-20 2003-02-25 Micron Technology, Inc. Method for forming a notched damascene planar poly/metal gate
US6617639B1 (en) 2002-06-21 2003-09-09 Advanced Micro Devices, Inc. Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling
US6888739B2 (en) 2002-06-21 2005-05-03 Micron Technology Inc. Nanocrystal write once read only memory for archival storage
US6804136B2 (en) 2002-06-21 2004-10-12 Micron Technology, Inc. Write once read only memory employing charge trapping in insulators
US7847344B2 (en) 2002-07-08 2010-12-07 Micron Technology, Inc. Memory utilizing oxide-nitride nanolaminates
US6828632B2 (en) 2002-07-18 2004-12-07 Micron Technology, Inc. Stable PD-SOI devices and methods
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US6790791B2 (en) 2002-08-15 2004-09-14 Micron Technology, Inc. Lanthanide doped TiOx dielectric films
US6884739B2 (en) 2002-08-15 2005-04-26 Micron Technology Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
KR100450681B1 (en) 2002-08-16 2004-10-02 삼성전자주식회사 Capacitor of semiconductor memory device and manufacturing method thereof
US6960538B2 (en) 2002-08-21 2005-11-01 Micron Technology, Inc. Composite dielectric forming methods and composite dielectrics
US20040036129A1 (en) 2002-08-22 2004-02-26 Micron Technology, Inc. Atomic layer deposition of CMOS gates with variable work functions
US6967154B2 (en) 2002-08-26 2005-11-22 Micron Technology, Inc. Enhanced atomic layer deposition
US6972599B2 (en) 2002-08-27 2005-12-06 Micron Technology Inc. Pseudo CMOS dynamic logic with delayed clocks
US7199023B2 (en) 2002-08-28 2007-04-03 Micron Technology, Inc. Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
US7084078B2 (en) 2002-08-29 2006-08-01 Micron Technology, Inc. Atomic layer deposited lanthanide doped TiOx dielectric films
US6760257B2 (en) 2002-08-29 2004-07-06 Macronix International Co., Ltd. Programming a flash memory cell
US7122415B2 (en) 2002-09-12 2006-10-17 Promos Technologies, Inc. Atomic layer deposition of interpoly oxides in a non-volatile memory device
US20040065255A1 (en) 2002-10-02 2004-04-08 Applied Materials, Inc. Cyclical layer deposition system
US6770536B2 (en) 2002-10-03 2004-08-03 Agere Systems Inc. Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate
US6686212B1 (en) 2002-10-31 2004-02-03 Sharp Laboratories Of America, Inc. Method to deposit a stacked high-κ gate dielectric for CMOS applications
JP2004158487A (en) 2002-11-01 2004-06-03 Matsushita Electric Ind Co Ltd Method of manufacturing semiconductor device
US20040099889A1 (en) 2002-11-27 2004-05-27 Agere Systems, Inc. Process for fabricating a semiconductor device having an insulating layer formed over a semiconductor substrate
US7101813B2 (en) 2002-12-04 2006-09-05 Micron Technology Inc. Atomic layer deposited Zr-Sn-Ti-O films
US6958302B2 (en) 2002-12-04 2005-10-25 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films using TiI4
JP4290421B2 (en) 2002-12-27 2009-07-08 Necエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US6762114B1 (en) 2002-12-31 2004-07-13 Texas Instruments Incorporated Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness
US6750126B1 (en) 2003-01-08 2004-06-15 Texas Instruments Incorporated Methods for sputter deposition of high-k dielectric films
US20040144980A1 (en) 2003-01-27 2004-07-29 Ahn Kie Y. Atomic layer deposition of metal oxynitride layers as gate dielectrics and semiconductor device structures utilizing metal oxynitride layers
US6884685B2 (en) 2003-02-14 2005-04-26 Freescale Semiconductors, Inc. Radical oxidation and/or nitridation during metal oxide layer deposition process
US20040168627A1 (en) 2003-02-27 2004-09-02 Sharp Laboratories Of America, Inc. Atomic layer deposition of oxide film
US6930059B2 (en) 2003-02-27 2005-08-16 Sharp Laboratories Of America, Inc. Method for depositing a nanolaminate film by atomic layer deposition
US7192892B2 (en) 2003-03-04 2007-03-20 Micron Technology, Inc. Atomic layer deposited dielectric layers
US6794315B1 (en) 2003-03-06 2004-09-21 Board Of Trustees Of The University Of Illinois Ultrathin oxide films on semiconductors
US7019351B2 (en) 2003-03-12 2006-03-28 Micron Technology, Inc. Transistor devices, and methods of forming transistor devices and circuit devices
US7135369B2 (en) 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US20040198069A1 (en) 2003-04-04 2004-10-07 Applied Materials, Inc. Method for hafnium nitride deposition
US7442415B2 (en) 2003-04-11 2008-10-28 Sharp Laboratories Of America, Inc. Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films
US7183186B2 (en) 2003-04-22 2007-02-27 Micro Technology, Inc. Atomic layer deposited ZrTiO4 films
KR100546324B1 (en) 2003-04-22 2006-01-26 삼성전자주식회사 Methods of forming metal oxide thin film and lanthanum oxide layer by ALD and method of forming high dielectric constant layer for semiconductor device
KR100885910B1 (en) 2003-04-30 2009-02-26 삼성전자주식회사 Nonvolatile semiconductor memory device having gate stack comprising OHAOxide-Hafnium oxide-Aluminium oxide film and method for manufacturing the same
US6740605B1 (en) 2003-05-05 2004-05-25 Advanced Micro Devices, Inc. Process for reducing hydrogen contamination in dielectric materials in memory devices
US6970053B2 (en) 2003-05-22 2005-11-29 Micron Technology, Inc. Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection
KR100555543B1 (en) 2003-06-24 2006-03-03 삼성전자주식회사 Method for forming high dielectric layer by atomic layer deposition and method for manufacturing capacitor having the layer
US7049192B2 (en) 2003-06-24 2006-05-23 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectrics
US7192824B2 (en) 2003-06-24 2007-03-20 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectric layers
US6785120B1 (en) * 2003-07-03 2004-08-31 Micron Technology, Inc. Methods of forming hafnium-containing materials, methods of forming hafnium oxide, and capacitor constructions comprising hafnium oxide
US7071066B2 (en) 2003-09-15 2006-07-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for forming high-k gates
US6989573B2 (en) 2003-10-10 2006-01-24 Micron Technology, Inc. Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics
US7157769B2 (en) 2003-12-18 2007-01-02 Micron Technology, Inc. Flash memory having a high-permittivity tunnel dielectric
US7154779B2 (en) 2004-01-21 2006-12-26 Sandisk Corporation Non-volatile memory cell using high-k material inter-gate programming
US8323754B2 (en) 2004-05-21 2012-12-04 Applied Materials, Inc. Stabilization of high-k dielectric materials
US20060019033A1 (en) * 2004-05-21 2006-01-26 Applied Materials, Inc. Plasma treatment of hafnium-containing materials
US7279413B2 (en) 2004-06-16 2007-10-09 International Business Machines Corporation High-temperature stable gate structure with metallic electrode
US7138681B2 (en) 2004-07-27 2006-11-21 Micron Technology, Inc. High density stepped, non-planar nitride read only memory
US7601649B2 (en) 2004-08-02 2009-10-13 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7151294B2 (en) 2004-08-03 2006-12-19 Micron Technology, Inc. High density stepped, non-planar flash memory
US7164168B2 (en) 2004-08-03 2007-01-16 Micron Technology, Inc. Non-planar flash memory having shielding between floating gates
US7129548B2 (en) * 2004-08-11 2006-10-31 International Business Machines Corporation MOSFET structure with multiple self-aligned silicide contacts
US7081421B2 (en) 2004-08-26 2006-07-25 Micron Technology, Inc. Lanthanide oxide dielectric layer
US7494939B2 (en) 2004-08-31 2009-02-24 Micron Technology, Inc. Methods for forming a lanthanum-metal oxide dielectric layer
US7588988B2 (en) 2004-08-31 2009-09-15 Micron Technology, Inc. Method of forming apparatus having oxide films formed using atomic layer deposition
US7138680B2 (en) 2004-09-14 2006-11-21 Infineon Technologies Ag Memory device with floating gate stack
US20060080682A1 (en) 2004-10-12 2006-04-13 Picsel Research Ltd. Run time dynamic linking
US7235501B2 (en) 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
US20060125030A1 (en) 2004-12-13 2006-06-15 Micron Technology, Inc. Hybrid ALD-CVD of PrxOy/ZrO2 films as gate dielectrics
US7560395B2 (en) 2005-01-05 2009-07-14 Micron Technology, Inc. Atomic layer deposited hafnium tantalum oxide dielectrics
US7508648B2 (en) 2005-02-08 2009-03-24 Micron Technology, Inc. Atomic layer deposition of Dy doped HfO2 films as gate dielectrics
US7399666B2 (en) 2005-02-15 2008-07-15 Micron Technology, Inc. Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectrics
US7498247B2 (en) 2005-02-23 2009-03-03 Micron Technology, Inc. Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7365027B2 (en) 2005-03-29 2008-04-29 Micron Technology, Inc. ALD of amorphous lanthanide doped TiOx films
US7390756B2 (en) 2005-04-28 2008-06-24 Micron Technology, Inc. Atomic layer deposited zirconium silicon oxide films
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US20060267113A1 (en) 2005-05-27 2006-11-30 Tobin Philip J Semiconductor device structure and method therefor
US7606816B2 (en) * 2005-06-03 2009-10-20 Yahoo! Inc. Record boundary identification and extraction through pattern mining
US7510983B2 (en) 2005-06-14 2009-03-31 Micron Technology, Inc. Iridium/zirconium oxide structure
US7195999B2 (en) * 2005-07-07 2007-03-27 Micron Technology, Inc. Metal-substituted transistor gates
US20070045752A1 (en) 2005-08-31 2007-03-01 Leonard Forbes Self aligned metal gates on high-K dielectrics
US20070049023A1 (en) 2005-08-29 2007-03-01 Micron Technology, Inc. Zirconium-doped gadolinium oxide films
US7521355B2 (en) 2005-12-08 2009-04-21 Micron Technology, Inc. Integrated circuit insulators and related methods
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7582161B2 (en) 2006-04-07 2009-09-01 Micron Technology, Inc. Atomic layer deposited titanium-doped indium oxide films

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3381114A (en) 1963-12-28 1968-04-30 Nippon Electric Co Device for manufacturing epitaxial crystals
US4058430A (en) 1974-11-29 1977-11-15 Tuomo Suntola Method for producing compound thin films
US4215156A (en) 1977-08-26 1980-07-29 International Business Machines Corporation Method for fabricating tantalum semiconductor contacts
US4413022A (en) 1979-02-28 1983-11-01 Canon Kabushiki Kaisha Method for performing growth of compound thin films
US4333808A (en) 1979-10-30 1982-06-08 International Business Machines Corporation Method for manufacture of ultra-thin film capacitor
US4394673A (en) 1980-09-29 1983-07-19 International Business Machines Corporation Rare earth silicide Schottky barriers
US4399424A (en) 1980-10-07 1983-08-16 Itt Industries, Inc. Gas sensor
US4647947A (en) 1982-03-15 1987-03-03 Tokyo Shibaura Denki Kabushiki Kaisha Optical protuberant bubble recording medium
US4590042A (en) 1984-12-24 1986-05-20 Tegal Corporation Plasma reactor having slotted manifold
US4920071A (en) 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
US4767641A (en) 1986-03-04 1988-08-30 Leybold-Heraeus Gmbh Plasma treatment apparatus
US4725877A (en) 1986-04-11 1988-02-16 American Telephone And Telegraph Company, At&T Bell Laboratories Metallized semiconductor device including an interface layer
US6120531A (en) 1987-05-20 2000-09-19 Micron, Technology Physiotherapy fiber, shoes, fabric, and clothes utilizing electromagnetic energy
US5049516A (en) 1987-12-02 1991-09-17 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor memory device
US5006192A (en) 1988-06-28 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Apparatus for producing semiconductor devices
US4993358A (en) 1989-07-28 1991-02-19 Watkins-Johnson Company Chemical vapor deposition reactor and method of operation
US5198029A (en) 1989-08-01 1993-03-30 Gte Products Corporation Apparatus for coating small solids
US6057271A (en) 1989-12-22 2000-05-02 Sumitomo Electric Industries, Ltd. Method of making a superconducting microwave component by off-axis sputtering
US5055319A (en) 1990-04-02 1991-10-08 The Regents Of The University Of California Controlled high rate deposition of metal oxide films
US5840897A (en) 1990-07-06 1998-11-24 Advanced Technology Materials, Inc. Metal complex source reagents for chemical vapor deposition
US6110529A (en) 1990-07-06 2000-08-29 Advanced Tech Materials Method of forming metal films on a substrate by chemical vapor deposition
US5080928A (en) 1990-10-05 1992-01-14 Gte Laboratories Incorporated Method for making moisture insensitive zinc sulfide based luminescent materials
US5302461A (en) 1992-06-05 1994-04-12 Hewlett-Packard Company Dielectric films for use in magnetoresistive transducers
US5572052A (en) 1992-07-24 1996-11-05 Mitsubishi Denki Kabushiki Kaisha Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer
US5426603A (en) 1993-01-25 1995-06-20 Hitachi, Ltd. Dynamic RAM and information processing system using the same
US5674563A (en) 1993-09-14 1997-10-07 Nissan Motor Co., Ltd. Method for ferroelectric thin film production
US5562952A (en) 1993-11-11 1996-10-08 Nissin Electric Co., Ltd. Plasma-CVD method and apparatus
US6296943B1 (en) 1994-03-05 2001-10-02 Nissan Chemical Industries, Ltd. Method for producing composite sol, coating composition, and optical element
US5827571A (en) 1994-06-08 1998-10-27 Hyundai Electronics Industries Co., Ltd. Hot-wall CVD method for forming a ferroelectric film
US5828080A (en) 1994-08-17 1998-10-27 Tdk Corporation Oxide thin film, electronic device substrate and electronic device
US5810923A (en) 1994-08-17 1998-09-22 Tdk Corporation Method for forming oxide thin film and the treatment of silicon substrate
US5822256A (en) 1994-09-06 1998-10-13 Intel Corporation Method and circuitry for usage of partially functional nonvolatile memory
US5625233A (en) 1995-01-13 1997-04-29 Ibm Corporation Thin film multi-layer oxygen diffusion barrier consisting of refractory metal, refractory metal aluminide, and aluminum oxide
US5744374A (en) 1995-03-22 1998-04-28 Samsung Electronics Co., Ltd. Device and manufacturing method for a ferroelectric memory
US5621681A (en) 1995-03-22 1997-04-15 Samsung Electronics Co., Ltd. Device and manufacturing method for a ferroelectric memory
US5595606A (en) 1995-04-20 1997-01-21 Tokyo Electron Limited Shower head and film forming apparatus using the same
US5751021A (en) 1995-04-24 1998-05-12 Sharp Kk Semiconductor light-emitting device
US5801105A (en) 1995-08-04 1998-09-01 Tdk Corporation Multilayer thin film, substrate for electronic device, electronic device, and preparation of multilayer oxide thin film
US5795808A (en) 1995-11-13 1998-08-18 Hyundai Electronics Industries C., Ltd. Method for forming shallow junction for semiconductor device
US5646583A (en) 1996-01-04 1997-07-08 Rockwell International Corporation Acoustic isolator having a high impedance layer of hafnium oxide
US6115401A (en) 1996-02-13 2000-09-05 Corning Oca Corporation External cavity semiconductor laser with monolithic prism assembly
US5789030A (en) 1996-03-18 1998-08-04 Micron Technology, Inc. Method for depositing doped amorphous or polycrystalline silicon on a substrate
US5735960A (en) 1996-04-02 1998-04-07 Micron Technology, Inc. Apparatus and method to increase gas residence time in a reactor
US6387712B1 (en) 1996-06-26 2002-05-14 Tdk Corporation Process for preparing ferroelectric thin films
US5698022A (en) 1996-08-14 1997-12-16 Advanced Technology Materials, Inc. Lanthanide/phosphorus precursor compositions for MOCVD of lanthanide/phosphorus oxide films
US5916365A (en) 1996-08-16 1999-06-29 Sherman; Arthur Sequential chemical vapor deposition
US6010969A (en) 1996-10-02 2000-01-04 Micron Technology, Inc. Method of depositing films on semiconductor devices by using carboxylate complexes
US6368398B2 (en) 1996-10-02 2002-04-09 Micron Technology, Inc. Method of depositing films by using carboxylate complexes
US6217645B1 (en) 1996-10-02 2001-04-17 Micron Technology, Inc Method of depositing films by using carboxylate complexes
US5923056A (en) 1996-10-10 1999-07-13 Lucent Technologies Inc. Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials
US5950925A (en) 1996-10-11 1999-09-14 Ebara Corporation Reactant gas ejector head
US6059885A (en) 1996-12-19 2000-05-09 Toshiba Ceramics Co., Ltd. Vapor deposition apparatus and method for forming thin film
US6203726B1 (en) 1997-03-04 2001-03-20 Symyx Technologies, Inc. Phosphor Materials
US6232847B1 (en) 1997-04-28 2001-05-15 Rockwell Science Center, Llc Trimmable singleband and tunable multiband integrated oscillator using micro-electromechanical system (MEMS) technology
US6399979B1 (en) 1997-07-08 2002-06-04 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
US6191448B1 (en) 1997-07-08 2001-02-20 Micron Technology, Inc. Memory cell with vertical transistor and buried word and body lines
US6020243A (en) 1997-07-24 2000-02-01 Texas Instruments Incorporated Zirconium and/or hafnium silicon-oxynitride gate dielectric
US6291866B1 (en) 1997-07-24 2001-09-18 Texas Instruments Incorporated Zirconium and/or hafnium oxynitride gate dielectric
US6013553A (en) 1997-07-24 2000-01-11 Texas Instruments Incorporated Zirconium and/or hafnium oxynitride gate dielectric
US6020024A (en) 1997-08-04 2000-02-01 Motorola, Inc. Method for forming high dielectric constant metal oxides
US5912797A (en) 1997-09-24 1999-06-15 Lucent Technologies Inc. Dielectric materials of amorphous compositions and devices employing same
US6281144B1 (en) 1997-09-26 2001-08-28 Novellus Systems, Inc. Exclusion of polymer film from semiconductor wafer edge and backside during film (CVD) deposition
US6161500A (en) 1997-09-30 2000-12-19 Tokyo Electron Limited Apparatus and method for preventing the premature mixture of reactant gases in CVD and PECVD reactions
US6297516B1 (en) 1997-11-24 2001-10-02 The Trustees Of Princeton University Method for deposition and patterning of organic thin film
US6198168B1 (en) 1998-01-20 2001-03-06 Micron Technologies, Inc. Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same
US6025225A (en) 1998-01-22 2000-02-15 Micron Technology, Inc. Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same
US5972847A (en) 1998-01-28 1999-10-26 Lockheed Martin Energy Method for making high-critical-current-density YBa2 Cu3 O7 superconducting layers on metallic substrates
US6317357B1 (en) 1998-02-24 2001-11-13 Micron Technology, Inc. Vertical bipolar read access for low voltage memory cell
US6150188A (en) 1998-02-26 2000-11-21 Micron Technology Inc. Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same
US6090636A (en) 1998-02-26 2000-07-18 Micron Technology, Inc. Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same
US6381168B2 (en) 1998-04-14 2002-04-30 Micron Technology, Inc. Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
US6294813B1 (en) 1998-05-29 2001-09-25 Micron Technology, Inc. Information handling system having improved floating gate tunneling devices
US6025627A (en) 1998-05-29 2000-02-15 Micron Technology, Inc. Alternate method and structure for improved floating gate tunneling devices
US6331465B1 (en) 1998-05-29 2001-12-18 Micron Technology, Inc. Alternate method and structure for improved floating gate tunneling devices using textured surface
US5981350A (en) 1998-05-29 1999-11-09 Micron Technology, Inc. Method for forming high capacitance memory cells
US6093944A (en) 1998-06-04 2000-07-25 Lucent Technologies Inc. Dielectric materials of amorphous compositions of TI-O2 doped with rare earth elements and devices employing same
US6225168B1 (en) 1998-06-04 2001-05-01 Advanced Micro Devices, Inc. Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof
US6302964B1 (en) 1998-06-16 2001-10-16 Applied Materials, Inc. One-piece dual gas faceplate for a showerhead in a semiconductor wafer processing system
US6027961A (en) 1998-06-30 2000-02-22 Motorola, Inc. CMOS semiconductor devices and method of formation
US6134175A (en) 1998-08-04 2000-10-17 Micron Technology, Inc. Memory address decode array with vertical transistors
US6391769B1 (en) 1998-08-19 2002-05-21 Samsung Electronics Co., Ltd. Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby
US6225237B1 (en) 1998-09-01 2001-05-01 Micron Technology, Inc. Method for forming metal-containing films using metal complexes with chelating O- and/or N-donor ligands
US6211035B1 (en) 1998-09-09 2001-04-03 Texas Instruments Incorporated Integrated circuit and method
US6380579B1 (en) 1999-04-12 2002-04-30 Samsung Electronics Co., Ltd. Capacitor of semiconductor device
US6171900B1 (en) 1999-04-15 2001-01-09 Taiwan Semiconductor Manufacturing Company CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET
US6273951B1 (en) 1999-06-16 2001-08-14 Micron Technology, Inc. Precursor mixtures for use in preparing layers on substrates
US6206972B1 (en) 1999-07-08 2001-03-27 Genus, Inc. Method and apparatus for providing uniform gas delivery to substrates in CVD and PECVD processes
US6207589B1 (en) 1999-07-19 2001-03-27 Sharp Laboratories Of America, Inc. Method of forming a doped metal oxide dielectric film
US6297539B1 (en) 1999-07-19 2001-10-02 Sharp Laboratories Of America, Inc. Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same
US6368518B1 (en) 1999-08-25 2002-04-09 Micron Technology, Inc. Methods for removing rhodium- and iridium-containing films
US6187484B1 (en) 1999-08-31 2001-02-13 Micron Technology, Inc. Irradiation mask
US6040243A (en) 1999-09-20 2000-03-21 Chartered Semiconductor Manufacturing Ltd. Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion
US6203613B1 (en) 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US6303481B2 (en) 1999-12-29 2001-10-16 Hyundai Electronics Industries Co., Ltd. Method for forming a gate insulating film for semiconductor devices
US6404027B1 (en) 2000-02-07 2002-06-11 Agere Systems Guardian Corp. High dielectric constant gate oxides for silicon-based devices
US6365470B1 (en) 2000-08-24 2002-04-02 Secretary Of Agency Of Industrial Science And Technology Method for manufacturing self-matching transistor
US6300203B1 (en) 2000-10-05 2001-10-09 Advanced Micro Devices, Inc. Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors
US6368941B1 (en) 2000-11-08 2002-04-09 United Microelectronics Corp. Fabrication of a shallow trench isolation by plasma oxidation
US6348386B1 (en) 2001-04-16 2002-02-19 Motorola, Inc. Method for making a hafnium-based insulating film

Non-Patent Citations (100)

* Cited by examiner, † Cited by third party
Title
"Improved Metallurgy for Wiring Very Large Scale Integrated Circuits", International Technology Disclosures, 4, Abstract, (1986), 1 page.
"Improved Metallurgy for Wiring Very Large Scale Integrated Circuits", International Technology Disclosures, vol. 4, No. 9, (1986), p. 2.
Aarik, Jaan , et al., "Atomic layer growth of epitaxial TiO<SUB>2 </SUB>thin films from TiCl<SUB>4 </SUB>and H<SUB>2</SUB>O on alpha -Al<SUB>2</SUB>O<SUB>3 </SUB>substrates", Journal of Crystal Growth, 242(1-2), (2002), 189-198.
Aarik, Jaan , et al., "Influence of Substrate temperature on atomic layer growth and properties of HfO<SUB>2 </SUB>thin films", Thin Solid Films, 340(1-2), (1999), 110-116.
Aarik, Jaan , et al., "Phase transformations in hafnium dioxide thin films grown by atomic layer deposition at high temperatures", Applied Surface Science, 173(1-2), (Mar. 2001), 15-21.
Aarik, Jaan , et al., "Texture Development in nanocrystalline hafnium dioxide thin films grown by atomic layer deposition", Journal of Crystal Growth, 220, (2000), 105-113.
Alen, Petra , "Atomic Layer deposition of Ta(Al)N(C) thin films using trimethylaluminum as a reducing agent", Journal of the Electrochemical Society, 148(10), (Oct. 2001),G566-G571.
Bendoraitis, J G., et al., "Optical energy gaps in the monoclinic oxides of hafnium and zirconium and their soild solutions", Journal of Physical Chemistry, 69(10), (1965), 3666-3667.
Braud, F., "Ultra Thin Diffusion Barriers for Cu Interconnections at the Gigabit Generation and Beyond", VMIC Conference Proceedings, (1996), 174-179.
Bright, A.A., et al., "Low-rate plasma oxidation of Si in a dilute oxygen/helium plasma for low-temperature gate quality Si/Sio2 interfaces", Applied Physics Letters, 58(6), (Feb. 1991), 619-621.
Bunshah, Rointan F., et al., "Deposition Technologies for Films and Coatings: Developments and Applications", Park Ridge, N.J., U.S.A. : Noyes Publications, (1982), 102-103.
Callegari, A. , et al., "Physical and electrical characterization of Hafnium oxide and Hafnium silicate sputtered films", Journal of Applied Physics, 90(12), (Dec. 15, 2001). 6466-75.
Cava, R J., "Improvement of the dielectric properties of Ta<SUB>2</SUB>O<SUB>5 </SUB>through substitution with Al<SUB>2</SUB>O<SUB>3</SUB>", Applied Physics Letters, 70(11), (Mar. 1997), 1396-8.
Chambers, J J., et al., "Physical and electrical characterization of ultrathin yttrium silicate insulators on silicon", Journal of Applied Physics, 90(2), (Jul. 15, 2001), 918-33.
Chang, Hyo S., et al., "Excellent thermal stability of Al2O3/ZrO2/Al2O3 stack structure of metal-oxide-semiconductor gate dielectrics application", Applied Physics Letters, 80(18), (May 6, 2002), 3385-7.
Chen, P. J., et al., "Thermal stability and scalability of Zr-aluminate-based high-k gate stacks", Symposium on VLSI Technology Digest, (2002), 192-3.
Cheng, Baohong , et al., "The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-100nm MOSFET's", IEEE Transactions on Electron Devices, 46(7), (Jul. 1999), 1537-1544.
Clark, P , "IMEC Highlights Hafnium, Metal Gates for High-k Integration", Semiconductor Business News, at Silicon Strategies.com, (Oct. 11, 2002), 2 pages.
Colombo, D. , et al., "Anhydrous Metal Nitrated as Volatile SIngle Source Precursors for the CVD of Metal Oxide Films", Communications, Department of EE, U of M, Mpls, MN, (Jul. 7, 1998), 3 pages.
Conley Jr., J F., et al., "Atomic Layer Deposition of Hafnium Oxide Using Anhydrous Hafnium Nitrate", Electrochemical and Solid State Letters, 5(5), (2002), C57-C59.
Copel, M. , "Structure and stability of ultrathin zirconium oxide layers on Si(001)", Applied Physics Letters, 76(4), (Jan. 200), 436-438.
Da Rosa, E B., et al., "Annealing of ZrAl<SUB>x</SUB>O<SUB>y </SUB>ultrathin films on Si in a vacuum or in O<SUB>2</SUB>", Journal of the Electrochemical Society, 148 (12), (Dec. 2001), G695-G703.
De Flaviis, Franco , et al., "Planar microwave integrated phase-shifter design with high purity ferroelectric material", IEEE Transactions on Microwave Theory & Techniques, 45(6), (Jun. 1997), 963-969.
Desu, S B., "Minimization of Fatigue in Ferroelectric Films", Physica Status Solidi A, 151(2), (1995),467-480.
Ding, "Copper Barrier, Seed Layer and Planarization Technologies", VMIC Conference Proceedings, (1997), 87-92.
Dusco, C , et al., "Deposition of tin oxide into porous silicon by atomic layer epitaxy", Journal of the Electrochemical Society, 143, (1996), 683-687.
El-Kareh, B , et al., "The evolution of DRAM cell technology", Solid State Technology, 40(5), (1997), 89-90, 92, 95-6, 98, 100-1.
Engelhardt, M. , "Modern Applications of Plasma Etching and Patterning in Silicon Process Technology", Contributions to Plasma Physics, 39(5), (1999), 473-478.
Forsgren, Katarina , "Atomic Layer Deposition of HfO2 using hafnium iodide", Conference held in Monterey, California, (May 2001), 1 page.
Forsgren, Katarina , "CVD and ALD of Group IV- and V-Oxides for Dielectric Applications", Comprehensive Summaries of Uppsala Dissertation from the Faculty of Science and Technology, 665, (2001).
Fukumoto, Hirofumi , et al., "Heteroepitaxial growth of Y2O3 films on silicon", Applied Physics Letters, 55(4), (Jul. 24, 1989), 360-361.
Fuyuki, Takashi , et al., "Electronic Properties of the Interface between Si and TiO2 Deposited at Very Low Temperatures", Japanese Journal of Applied Physics, 25(9), (Sep. 1986), 1288-1291.
Fuyuki, Takashi , et al., "Initial stage of ultra-thin SiO<SUB>2 </SUB>formation at low temperatures using activated oxygen", Applied Surface Science, 117-118, (Jun. 1997), 123-126.
Fuyuki, Takashi, et al., "Electronic Properties of the Interface between Si and TiO2 Deposited at Very Low Temperatures", Japanese Journal of Applied Physics, Part 1 (Regular Papers & Short Notes), 25(9), (Sep. 1986), 1288-1291.
Gartner, M , et al., "Spectroellipsometric characterization of lanthanide-doped TiO<SUB>2 </SUB>films obtained via the sol-gel technique", Thin Solid Films, 234(1-2), (1993), 561-565.
Geller, S. , et al., "Crystallographic Studies of Perovskite-like Compounds. II. rare earth Aluminates", Acta Cryst., 9, (May 1956), 1019-1025.
Giess, E. A., et al., "Lanthanide gallate perovskite-type substrates for epitaxial, high-T<SUB>c </SUB>superconducting Ba<SUB>2</SUB>YCu<SUB>3</SUB>O<SUB>7 </SUB>- delta / films", IBM Journal of Research and Development, 34(6), (Nov. 1990), 916-926.
Guillaumot, B , et al., "75 nm damascene metal gate and high-k integration for advanced CMOS devices", Technical Digest of International Electron Devices Meeting 2002, (2002), 355-358.
Guo, Xin , et al., "High quality ultra-thin (1.5 nm) TiO2-Si3N 4 gate dielectric for deep sub-micron CMOS technology", IEDM Technical Digest. International Electron Devices Meeting, (Dec. 5-8, 1999), 137-140.
Gusev, EP., et al., "Ultrathin High-K Dielectrics Grown by Atomic Layer Deposition: A Comparative Study of ZrO2, HfO2, Y2O3 and Al2O3", Electrochemical Society Proceedings Volume Sep. 2001, (2001), 189-195.
Gutowski, M J., "Thermodynamic stability of high-K dielectric metal oxides ZrO<SUB>2 </SUB>and HfO<SUB>2 </SUB>in contact with Si and SiO<SUB>2</SUB>", Applied Physics Letters, 80(11), (Mar. 18, 2002), 1897-1899.
Hirayama, Masaki , et al., "Low-Temperature Growth of High-Integrity Silicon Oxide Films by Oxygen Radical Generated in High Density Krypton Plasma", International Electron Devices Meeting 1999. Technical Digest, (1999), 249-252.
Hubbard, K. J., "Thermodynamic stability of binary oxides in contact with silicon", Journal of Materials Research, 11(11), (Nov. 1996), 2757-2776.
Hunt, C. E., et al., "Direct bonding of micromachined silicon wafers for laser diode heat exchanger applications", Journal of Micromechanics and Microengineering, 1(3), (Sep. 1991), 152-156.
Iddles, D M., et al., "Relationships between dopants, microstructure and the microwave dielectric properties of ZrO2-TiO2-SnO2 ceramics", Journal of Materials Science, 27(23), (Dec. 1992), 6303-6310.
Iijima, T. , "Microstructure and Electrical Properties of Amorphous W-Si-N Barrier Layer for Cu Interconnections", 1996 VMIC Conference, (1996), 168-173.
Jeon, Sanghun , et al., "Excellent electrical characteristics of lanthanide (Pr, Nd, Sm, Gd, and Dy) oxide and lanthanide-doped oxide for MOS gate dielectric applications", Electron Devices Meeting, 2001. IEDM Technical Digest. International, (2001), 471-474.
Jeon, Sanghun , et al., "Ultrathin nitrided-nanolaminate (Al<SUB>2</SUB>O<SUB>3</SUB>/ZrO<SUB>2</SUB>/Al<SUB>2</SUB>O<SUB>3</SUB>) for metal-oxide-semiconductor gate dielectric applications", Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 20(3), (May 2002), 1143-5.
Jeong, Chang-Wook , et al., "Plasma-Assisted Atomic Layer Growth of High-Quality Aluminum Oxide Thin Films", Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 40(1), (Jan. 2001), 285-289.
Jung, H S., et al., "Improved current performance of CMOSFETs with nitrogen incorporated HfO<SUB>2</SUB>-Al<SUB>2</SUB>O<SUB>3 </SUB>laminate gate dielectric", Technical Digest of International Electron Devices Meeting 2002, (2002), 853-856.
Kang, L , et al., "MOSFET devices with polysilicon on single-layer HfO<SUB>2 </SUB>high-K dielectrics", International Electron Devices Meeting 2000. Technical Digest. IEDM, (2000), 35-8.
Kawai, Y , et al., "Ultra-low-temperature growth of high-integrity gate oxide films by low-energy Ion-assisted oxidation", Applied Physics Letters, 64(17), (Apr. 1994), 2223-2225.
Keomany, D. , et al., "Sol gel preparation of mixed cerium-titanium oxide thin films", Solar Energy Materials and Solar Cells, 33(4), (Aug. 1994), 429-441.
Kim, Byoung-Youp , et al., "Comparison study for TiN films deposited from different method: chemical vapor deposition and atomic deposition", Mechanisms of Surface and Microstructure Evolution in Deposited Films and Film Structures Symposium (Materials Research Society Symposium Proceedings vol. 672), (2001), 7.8.1-7.8.6.
Kim, C T., et al., "Application of Al2O3 Grown by Atomic Layer Deposition to DRAM and FeRAM", International Symposium in Intergrated Ferroelectrics, (Mar. 2000), 316.
Kim, D. , et al., "Atomic Control of Substrate Termination and Heteroepitaxial Growth of SrTiO3/LaAlO3 Films", Journal of the Korean Physical Society, 36(6), (Jun. 2000), 444-448.
Kim, Taeseok , et al., "Correlation between strain and dielectric properties in ZrTiO<SUB>4 </SUB>thin films", Applied Physics Letters, 76(21), (May 2000), 3043-3045.
Kim, Taeseok , et al., "Dielectric properties and strain analysis in paraelectric ZrTiO<SUB>4 </SUB>thin films deposited by DC magnetron sputtering", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 39(7A), (2000), 4153-4157.
Kim, Y , et al., "Substrate dependence on the optical properties of Al<SUB>2</SUB>O<SUB>3 </SUB>films grown by atomic layer deposition", Applied Physics Letters, 71(25), (Dec. 22, 1997), 3604-3606.
Kim, Y W., et al., "50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications", Technical Digest of International Electron Devices Meeting 2002, (2002), 69-72.
Kim, Yongjo , et al., "Effect of microstructures on the microwave dielectric properties of ZrTiO<SUB>4 </SUB>thin films", Applied Physics Letters, 78(16), (Apr. 16, 2001), 2363-2365.
Krauter, G. , et al., "Room Temperature Silicon wafer Bonding with Ultra-Thin Polymer Films", Advanced Materials, 9(5), (1997), 417-420.
Kukli, K , et al., "Comparison of hafnium oxide films grown by atomic layer deposition from iodide and chloride precursors", Thin Solid Films, 416, (2002), 72-79.
Kukli, K , et al., "Controlled growth of yttrium oxysulphide thin films by atomic layer deposition", Materials Science Forum, 315-317, (1999), 216-221.
Kukli, K J., et al., "Properties of hafnium oxide films grown by atomic layer deposition from hafnium tetraiodide and oxygen", Journal of Applied Physics, 92(10), (Nov. 15, 2002), 5698-5703.
Kukli, Kaupo , "Atomic Layer Deposition of Titanium Oxide Til<SUB>4 </SUB>and H<SUB>2</SUB>O<SUB>2</SUB>", Chemical Vapor Deposition, 6(6), (2000), 303-310.
Kukli, Kaupo , "Dielectric Properties of Zirconium Oxide Grown by Atomic Layer deposition from Iodide Precursor", Journal of The Electrochemical Society, 148(12), (2001), F227-F232.
Kukli, Kaupo , et al., "Influence of thickness and growth temperature on the peoperties of zirconium oxide films growth by atomic layer deposition on silicon", Thin Solid Films, 410(1-2), (2002), 53-60.
Kukli, Kaupo , et al., "Low-Temperature deposition of Zirconium Oxide-Based Nanocrystalline Films by Alternate Supply of Zr[OC(CH<SUB>3</SUB>)<SUB>3</SUB>]<SUB>4 </SUB>and H<SUB>2</SUB>O", Chemical Vapor Deposition, 6(6), (2000), 297-302.
Kwo, J. , "Properties of high k gate dielectrics Gd<SUB>2</SUB>O<SUB>3 </SUB>and Y<SUB>2</SUB>O<SUB>3 </SUB>for Si", Journal of Applied Physics, 89(7), (2001), 3920-3927.
Kwo, J. , et al., "High epsilon gate dielectrics Gd<SUB>2</SUB>O<SUB>3 </SUB>and Y<SUB>2</SUB>O<SUB>3 </SUB>for silicon", Applied Physics Letters, 77(1), (Jul. 3, 2000), 130-132.
Laursen, T. , "Encapsulation of Copper by Nitridation of Cu-Ti Alloy/Bilayer Structures", International Conference on Metallurgical Coatings and Thin Films, Abstract No. H1.03, San Diego, CA,(Apr. 1997), 309.
Lee, A E., et al., "Epitaxially grown sputtered LaAlO<SUB>3 </SUB>films", Applied Physics Letters, 57(19), (Nov. 1990), 2019-2021.
Lee, Byoung H., et al., "Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8 A-12 A)", Electron Devices Meeting, 2000. IEDM Technical Digest. International(2000), 39-42.
Lee, Byoung H., et al., "Ultrathin Hafnium Oxide with Low Leakage and excellent Reliability for ALternative Gate Dielectric Application", IEEE Technical Digest of International Electron Devices Meeting 1999, (1999), 133-136.
Lee, Byoung H., et al., "Ultrathin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate Dielectric Application", Technical Digest of IEDM, (1999), 133-136.
Lee, C H., et al., "MOS Devices with High Quality Ultra Thin CVD ZrO<SUB>2 </SUB>Gate Dielectrics and Self-Aligned TaN and TaN/Poly-Si Gate electrodes", 2001 Symposium on VLSI, Technology Digest of Technical Papers, (2001), 137-138.
Lee, C. H., et al., "MOS Characteristics of Ultra Thin Rapid Thermal CVD ZrO<SUB>2 </SUB>and Zr Silicate Gate Dielectrics", Electron Devices Meeting, 2000. IDEM Technical Digest. International, (2000), 27-30.
Lee, Cheng-Chung , et al., "Ion-assisted deposition of silver thin films", Thin Solid Films, 359,(2000), pp. 95-97.
Lee, Dong H., et al., "Metalorganic chemical vapor deposition of TiO<SUB>2</SUB>:N anatase thin film on Si substrate", Applied Physics Letters, 66(7), (feb. 1995), 815-816.
Lee, Jung-Hyoung , et al., "Mass production worthy HfO<SUB>2</SUB>-Al<SUB>2</SUB>O<SUB>3 </SUB>laminate capacitor technology using Hf liquid precursor for sub-100 nm DRAMs", Electron Devices Meeting, 2002. IEDM '02. Digest. International, (2002), 221-224.
Lee, L P., et al., "Monolithic 77 K dc SQUID magnetometer", Applied Physics Letters, 59(23), (dec. 1991), 3051-3053.
Lee, S J., et al., "High quality ultra thin CVD HfO<SUB>2 </SUB>gate stack with poly-Si gate electrode", Electron Devices Meeting, 2000. IEDM Technical Digest. International, (2000), 31-34.
Lee, S. J., et al., "Hafnium oxide gate stack prepared by in situ rapid thermal chemical vapor deposition process for advanced gate dielectrics", Journal of Applied Physics92 (5), (Sep. 1, 2002), 2807-09.
Leskela, M, et al., "ALD precursor chemistry: Evolution and future challenges", Journal de Physique IV (Proceedings), 9(8), (Sep. 1999), 837-852.
Liu, C. T., "Circuit Requirement and Integration Challenges of Thin Gate Dielectrics for Ultra Small MOSFETs", International Electron Devices Meeting 1998. Technical Digest, (1998), 747-750.
Liu, Y C., et al., "Growth of ultrathin SiO<SUB>2 </SUB>on Si by surface irradiation with an O<SUB>2</SUB>+Ar electron cyclotron resonance microwave plasma at low temperatures", Journal of Applied Physics, 85(3), (Feb. 1999), 1911-1915.
Luan, et al., "High Quality Ta<SUB>2</SUB>O<SUB>5 </SUB>Gate Dielectrics and T<SUB>ox.eq</SUB><10å",IEEE Technical Digest of Int. Elec. Devices Mtng 1999, (1999), 141-142.
Lucovsky, G , et al., "Microscopic model for enhanced dielectric constants in low concentration SiO<SUB>2</SUB>-rich noncrystalline Zr and Hf silicate alloys", Applied Physics Letters, 77(18), (Oct. 2000), 2912-2914.
Luo, Z J., et al., "Ultra-thin ZrO2 (or Silicate) with High Thermal Stability for CMOS Gate Applications", 2001 Symposium on VLSI Technology DIgest of Technical Papers, (2001), 135-136.
Martin, et al., "Ion-beam-assisted deposition of thin films", Applied Optics, 22(1), (1983), 178-184.
Martin, P J., et al., "Ion-beam-assisted deposition of thin films", Applied Optics, 22(1), (Jan. 1983), 178-184.
Molodyk, A A., et al., "Volatile Surfactant-Assisted MOCVD: Application to LaAl03 Thin Film Growth", Chemical Vapor Deposition, 6(3), (Jun. 2000), 133-138.
Molsa, Heini , et al., "Growth of yttrium oxide thin films from beta -diketonate presursor", Advanced Materials for Optics and Electronics, 4(6), (Nov.-Dec. 1994), 389-400.
Muller, D. A., "The electronic structure at the atomic scale of ultrathin gate oxides", Nature, 399(6738), (Jun. 24, 1999), 758-61.
Nakagawara, Osamu , et al., "Electrical properties of (Zr, Sn)TiO4 dielectric thin film prepared by pulsed laser deposition", Journal of Applied Physics, 80(1), (Jul. 1996), 388-392.
Nakajima, Anri , et al., "Atomic-layer deposition of ZrO<SUB>2 </SUB>with a Si nitride barrier layer", Applied Physics Letters, 81(15), (Oct. 2002), 2824-2826.
Nakajima, Anri , et al., "NH<SUB>3</SUB>-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability", Applied Physics Letters, 80(7), (Feb. 2002), 1252-1254.
PCT Search Report dated Oct. 15, 2003 for application PCT/US03/17730 completed by S. Nesso.
Sanley Wolf Silicon Processing for the VLSI Era vol. 4 Lattice Press 2000 pp. 98, 146, and 173-174. *

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