US20020142536A1 - Method of making single c-axis PGO thin film on ZrO2 for non-volatile memory applications - Google Patents

Method of making single c-axis PGO thin film on ZrO2 for non-volatile memory applications Download PDF

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US20020142536A1
US20020142536A1 US10/128,604 US12860402A US2002142536A1 US 20020142536 A1 US20020142536 A1 US 20020142536A1 US 12860402 A US12860402 A US 12860402A US 2002142536 A1 US2002142536 A1 US 2002142536A1
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pgo
layer
oxide
insulator
film
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Fengyan Zhang
Yanjun Ma
Jer-shen Maa
Wei-Wei Zhuang
Sheng Hsu
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Definitions

  • This invention relates to a single c-axis Lead Germanium Oxide (PGO) thin film on an insulator layer for non-volatile memory applications and methods of making the same and, more particularly, to a PGO thin film on a Zirconium Oxide (ZrO 2 ) insulator for ferroelectric random access memory (FeRAM) and dynamic random access memory (DRAM) applications.
  • PGO Lead Germanium Oxide
  • ZrO 2 Zirconium Oxide
  • FeRAM ferroelectric random access memory
  • DRAM dynamic random access memory
  • PGO Lead Germanium Oxide
  • Pb 5 Ge 3 O 11 is a well-known ferroelectric material. Pure c-axis oriented PGO thin films have been successfully grown on Iridium (Ir), Platinum (Pt), Platinum/Iridium (Pt/Ir) and Iridium-Tantalum-Oxygen (Ir—Ta—O) conductive electrodes. These structures can be used for metal ferroelectric metal oxide semiconductor (MFMOS) single transistor memory applications.
  • MMOS metal ferroelectric metal oxide semiconductor
  • Ferroelectric devices have also been manufactured with SrBi 2 Ta 2 O 9 (SBT). Unlike the ferroelectric material SBT, which exhibits ferroelectric properties with a polycrystalline structure, PGO only exhibits ferroelectric properties when it is c-axis oriented. However, it is rather difficult to grow single-phase c-axis PGO films on insulators because PGO films usually exhibit amorphous or polycrystalline structure.
  • SBT SrBi 2 Ta 2 O 9
  • Metal ferroelectric semiconductor field effect transistors are an attractive alternative to MFMOS.
  • MFSFET Metal ferroelectric semiconductor field effect transistors
  • a strong interaction between the PGO film and the Silicon precludes the fabrication of such devices using a PGO ferroelectric layer.
  • Metal ferroelectric insulator semiconductor field effect transistors have also been investigated because their structure is simpler than that of MFMOS structures.
  • good insulator films for fabrication of MFISFET devices which include a PGO ferroelectric layer, have not been found. Accordingly, there is a need for finding a good insulator film that allows for the fabrication of MFISFET devices having a PGO ferroelectric layer.
  • the invention comprises a new thin film structure, including a single-phase c-axis PGO film on an insulator, such as ZrO 2 , for metal ferroelectric insulator semiconductor single transistor non-volatile memory applications.
  • This PGO-on-insulator structure can also be used in capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices.
  • an object of the invention is to provide a MFIS transistor structure including a PGO ferroelectric film.
  • Another object of the invention is to provide a MFIS transistor structure including a ZrO 2 insulator film.
  • a further object of the invention is to provide a MFIS transistor structure including a PGO ferroelectric layer on an insulator layer.
  • FIG. 1 is a schematic of the inventive PGO ferroelectric film on an insulator film.
  • FIG. 2 is a graph of an X-ray diffraction spectrum of a PGO film on a ZrO 2 insulator film.
  • FIG. 3 is a graph of a high frequency Capacitance-Voltage (CV) measurement of a metal ferroelectric insulator semiconductor (MFIS) capacitor comprising Pt/PGO/ZrO 2 /Si.
  • CV Capacitance-Voltage
  • FIG. 4 is a graph of a Capacitance-Voltage (CV) measurement of a Pt/PGO(180 nm)/Ir capacitor structure.
  • FIG. 5 is a graph of a leakage current (I-V) of a PGO/ZrO 2 film.
  • FIG. 6 is a schematic of a metal ferroelectric insulator semiconductor field effect transistor including a PGO layer on an insulator structure.
  • FIG. 7 is a flowchart of the method of making the PGO-on-insulator structure of the present invention.
  • FIG. 1 shows a schematic of the inventive device.
  • Device 10 includes a Semiconductor substrate 12 such as a Silicon substrate.
  • An Insulator film 14 such as ZrO 2 , is positioned on substrate 12 .
  • a ferroelectric layer 16 namely, a substantially single phase, c-axis Pb 5 Ge 3 O 11 (PGO) film, is positioned on insulator film 14 .
  • a metal top electrode 18 is positioned on PGO film 16 .
  • a typical method for preparing such a structure may include the following steps.
  • Third, the PGO film is deposited by any of the following methods: spin-on; physical vapor deposition; CVD; metal organic CVD (MOCVD); chemical solution deposition (CSD); and laser ablation.
  • the following device was manufactured.
  • ZrO 2 was sputtereddeposited onto a clean Silicon wafer by reactive sputtering of a Zirconium target in an Oxygen ambient.
  • the film thickness 20 was 135 Angstroms.
  • the thickness of the insulator layer typically will be greater than at least 20 Angstroms.
  • the PGO thin film 16 was spin coated using lead acetate (Pb(OAc) 2 ⁇ 3H 2 O) and germanium isopropoxide (Ge(OPr′) 4 ) in 2-(2-ethoxyethoxy) ethanol solution (H(OC 2 H 4 OC 2 H 4 OC 2 H 5 ), heated with an air exposure until a deep red brown color.
  • the Lead to Germanium ratio (Pb/Ge) was 5.25/3.
  • the baking temperature was approximately 50 to 350 degrees Celsius for 30 seconds to 3600 seconds.
  • the annealing temperature after each spin-on layer was approximately 400 to 550 degrees Celsius for 30 seconds to 3600 seconds.
  • the final annealing temperature was approximately 450 to 600 degrees Celsius for five minutes to three hours.
  • the thickness 22 of the PGO layer 16 was approximately 1600 Angstroms and typically will be in a range of 100 Angstroms to 5000 Angstroms.
  • the phases of the deposited PGO layer were examined by X-ray diffraction.
  • FIG. 2 is a graph of an X-ray diffraction spectrum of a PGO film on a ZrO 2 substrate, as manufactured by the steps listed above.
  • the x-axis represents two-times-theta (degrees) and the y-axis represents counts per second.
  • the graph shows that substantially pure c-axis PGO was obtained on the ZrO 2 substrate, as shown by the peaks labeled ( 001 ), ( 002 ), ( 003 ), ( 004 ), ( 005 ) and ( 006 ). No other peaks are observed (except for minimal peaks at 29 degrees), which indicates that no reaction, or only a minimal reaction (as shown by the secondary phases at 29 degrees), occurred at the interface of the PGO and ZrO 2 layers.
  • FIG. 3 is a graph of a high frequency Capacitance-Voltage (CV) measurement of a metal ferroelectric insulator semiconductor (MFIS) capacitor comprising Pt/PGO/ZrO 2 /Si.
  • the x-axis shows voltage and the y-axis shows Capacitance.
  • MFIS metal ferroelectric insulator semiconductor
  • a Platinum (Pt) top electrode was deposited on the PGO surface with a shallow mask. The area of the top electrode was approximately 4 ⁇ 10 ⁇ 4 cm 2 .
  • the PGO film had a thickness of approximately 1600 Angstroms and the ZrO 2 layer had a thickness of approximately 130 Angstroms.
  • the hysteresis in the C-V curve indicates a memory window of approximately 0.7 volts.
  • the memory window typically will be between 0.1 to 3.0 volts. This is less than the 1.3 volt memory window for an 1800 Angstrom PGO film in a metal ferroelectric metal (MFM) structure.
  • MFM metal ferroelectric metal
  • FIG. 4 is a graph of a Capacitance-Voltage (CV) measurement of a Pt/PGO(180 nm)/Ir capacitor structure.
  • the memory window shown is about 1.8 volts.
  • FIG. 5 is a graph of a leakage current (I-V) of a PGO film on a ZrO 2 film. As shown by the graph, the leakage current though the PGO/ZrO 2 structure is very small, indicating that a good interface is maintained between the PGO, the ZrO 2 and the Silicon substrate. In particular, the leakage current typically is less than 1 ⁇ 10 ⁇ 6 A/cm 2 at 100 KV/cm.
  • FIG. 6 is a schematic of a preferred embodiment of the composite PGO/insulator layered structure, namely, a metal ferroelectric insulator semiconductor field effect transistor (MFISFET) including a PGO film on an insulator layer.
  • Device 30 includes a Semiconductor substrate 32 such as a Silicon substrate, including a source region 34 and a drain region 36 .
  • An Insulator film 38 is positioned on substrate 32 .
  • Insulator film 38 may comprise Zirconium Oxide (ZrO 2 ), Hafnium Oxide (HfO 2 ), silicates of Zirconium or Hafnium, or mixtures of the above.
  • the insulator film 38 may also comprise Aluminum Oxide, Yttrium Oxide, Calcium Oxide, Lanthanum Oxide, Titanium Oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), doped ZrO 2 or doped HfO 2 , Zr—Al—O, Hf—Al—O, Zr—Ti—O, Hf—Ti—O, and La—Al—O, and combinations thereof.
  • the ferroelectric layer 40 comprises a single phase, c-axis Pb 5 Ge 3 O 11 (PGO) film, positioned on insulator film 38 .
  • the ferroelectric PGO layer may be deposited by the method set forth in U.S. Pat. Registration No. 6,190,925, issued on Feb.
  • a PGO layer can be deposited with a substantially c-axis crystalline orientation, i.e., more than a 70% c-axis orientation, but may be as high as 80%. In a preferred embodiment, the PGO layer will have approximately a 90% c-axis orientation or better.
  • a metal top electrode 42 is positioned on PGO film 40 .
  • the metal top electrode may comprise Platinum (Pt), Iridium (Ir), Tantalum (Ta), Ruthenium (Ru) or conductive oxides or alloys.
  • FIG. 7 is a flowchart of the method of making the PGO-on-insulator structure of the present invention.
  • Step 50 comprises preparing the semiconductor substrate using any state of the art process including isolation and well formation.
  • Step 52 comprises depositing the insulator film by any of the following means: physical vapor deposition (PVD); evaporation and oxidation; chemical vapor deposition (CVD); and atomic layer deposition.
  • Step 54 if required, comprises post deposition annealing of the insulator film in forming gas or Oxygen ambient at a temperature up to 800 degrees Celsius.
  • Step 56 comprises depositing the PGO film by any of the following methods: spin-on; physical vapor deposition; CVD; metal organic CVD (MOCVD); chemical solution deposition (CSD); and laser ablation.
  • Step 58 comprises depositing the metal gate electrode on the PGO layer by any means known in the art.
  • Step 60 comprises making any required contact and interconnect formations.

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Abstract

A thin film structure includes a substantially single-phase, c-axis PGO film on an insulator for use in metal ferroelectric insulator semiconductor single transistor nonvolatile memory applications. The PGO on insulator structure can also be used in capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. In a preferred embodiment, the PGO film is deposited on a Zirconium Oxide insulator layer.

Description

    FIELD OF THE INVENTION
  • This invention relates to a single c-axis Lead Germanium Oxide (PGO) thin film on an insulator layer for non-volatile memory applications and methods of making the same and, more particularly, to a PGO thin film on a Zirconium Oxide (ZrO[0001] 2) insulator for ferroelectric random access memory (FeRAM) and dynamic random access memory (DRAM) applications.
    • BACKGROUND OF THE INVENTION
  • Lead Germanium Oxide (PGO or Pb[0002] 5Ge3O11) is a well-known ferroelectric material. Pure c-axis oriented PGO thin films have been successfully grown on Iridium (Ir), Platinum (Pt), Platinum/Iridium (Pt/Ir) and Iridium-Tantalum-Oxygen (Ir—Ta—O) conductive electrodes. These structures can be used for metal ferroelectric metal oxide semiconductor (MFMOS) single transistor memory applications.
  • Ferroelectric devices have also been manufactured with SrBi[0003] 2Ta2O9 (SBT). Unlike the ferroelectric material SBT, which exhibits ferroelectric properties with a polycrystalline structure, PGO only exhibits ferroelectric properties when it is c-axis oriented. However, it is rather difficult to grow single-phase c-axis PGO films on insulators because PGO films usually exhibit amorphous or polycrystalline structure.
  • Metal ferroelectric semiconductor field effect transistors (MFSFET) are an attractive alternative to MFMOS. However, a strong interaction between the PGO film and the Silicon precludes the fabrication of such devices using a PGO ferroelectric layer. Metal ferroelectric insulator semiconductor field effect transistors (MFISFET) have also been investigated because their structure is simpler than that of MFMOS structures. However, heretofore, good insulator films for fabrication of MFISFET devices, which include a PGO ferroelectric layer, have not been found. Accordingly, there is a need for finding a good insulator film that allows for the fabrication of MFISFET devices having a PGO ferroelectric layer. [0004]
    • SUMMARY OF THE INVENTION
  • The invention comprises a new thin film structure, including a single-phase c-axis PGO film on an insulator, such as ZrO[0005] 2, for metal ferroelectric insulator semiconductor single transistor non-volatile memory applications. This PGO-on-insulator structure can also be used in capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices.
  • Accordingly, an object of the invention is to provide a MFIS transistor structure including a PGO ferroelectric film. [0006]
  • Another object of the invention is to provide a MFIS transistor structure including a ZrO[0007] 2 insulator film.
  • A further object of the invention is to provide a MFIS transistor structure including a PGO ferroelectric layer on an insulator layer.[0008]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic of the inventive PGO ferroelectric film on an insulator film. [0009]
  • FIG. 2 is a graph of an X-ray diffraction spectrum of a PGO film on a ZrO[0010] 2 insulator film.
  • FIG. 3 is a graph of a high frequency Capacitance-Voltage (CV) measurement of a metal ferroelectric insulator semiconductor (MFIS) capacitor comprising Pt/PGO/ZrO[0011] 2/Si.
  • FIG. 4 is a graph of a Capacitance-Voltage (CV) measurement of a Pt/PGO(180 nm)/Ir capacitor structure. [0012]
  • FIG. 5 is a graph of a leakage current (I-V) of a PGO/ZrO[0013] 2 film.
  • FIG. 6 is a schematic of a metal ferroelectric insulator semiconductor field effect transistor including a PGO layer on an insulator structure. [0014]
  • FIG. 7 is a flowchart of the method of making the PGO-on-insulator structure of the present invention.[0015]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Turning now to the drawings, FIG. 1 shows a schematic of the inventive device. [0016] Device 10 includes a Semiconductor substrate 12 such as a Silicon substrate. An Insulator film 14, such as ZrO2, is positioned on substrate 12. A ferroelectric layer 16, namely, a substantially single phase, c-axis Pb5Ge3O11 (PGO) film, is positioned on insulator film 14. A metal top electrode 18 is positioned on PGO film 16.
  • A typical method for preparing such a structure may include the following steps. First, the semiconductor substrate is prepared using any state of the art process including isolation and well formation. Second, the insulator film, such as ZrO[0017] 2, is deposited by any of the following means: physical vapor deposition (PVD); evaporation and oxidation; chemical vapor deposition (CVD); and atomic layer deposition. Any necessary post deposition anneal may include annealing in forming gas or Oxygen ambient at a temperature up to 800 degrees Celsius. Third, the PGO film is deposited by any of the following methods: spin-on; physical vapor deposition; CVD; metal organic CVD (MOCVD); chemical solution deposition (CSD); and laser ablation. Fourth, the metal gate electrode is deposited on the PGO layer by any means known in the art. Fifth, the contact and interconnect formations are made.
  • As an example, the following device was manufactured. ZrO[0018] 2 was sputtereddeposited onto a clean Silicon wafer by reactive sputtering of a Zirconium target in an Oxygen ambient. The film thickness 20, as measured by spectroscopic ellipsometry, was 135 Angstroms. The thickness of the insulator layer typically will be greater than at least 20 Angstroms. The PGO thin film 16 was spin coated using lead acetate (Pb(OAc)2 ·3H2O) and germanium isopropoxide (Ge(OPr′)4) in 2-(2-ethoxyethoxy) ethanol solution (H(OC2H4OC2H4OC2H5), heated with an air exposure until a deep red brown color. The Lead to Germanium ratio (Pb/Ge) was 5.25/3. The baking temperature was approximately 50 to 350 degrees Celsius for 30 seconds to 3600 seconds. The annealing temperature after each spin-on layer was approximately 400 to 550 degrees Celsius for 30 seconds to 3600 seconds. The final annealing temperature was approximately 450 to 600 degrees Celsius for five minutes to three hours. The thickness 22 of the PGO layer 16 was approximately 1600 Angstroms and typically will be in a range of 100 Angstroms to 5000 Angstroms. The phases of the deposited PGO layer were examined by X-ray diffraction.
  • FIG. 2 is a graph of an X-ray diffraction spectrum of a PGO film on a ZrO[0019] 2 substrate, as manufactured by the steps listed above. The x-axis represents two-times-theta (degrees) and the y-axis represents counts per second. The graph shows that substantially pure c-axis PGO was obtained on the ZrO2 substrate, as shown by the peaks labeled (001), (002), (003), (004), (005) and (006). No other peaks are observed (except for minimal peaks at 29 degrees), which indicates that no reaction, or only a minimal reaction (as shown by the secondary phases at 29 degrees), occurred at the interface of the PGO and ZrO2 layers.
  • FIG. 3 is a graph of a high frequency Capacitance-Voltage (CV) measurement of a metal ferroelectric insulator semiconductor (MFIS) capacitor comprising Pt/PGO/ZrO[0020] 2/Si. The x-axis shows voltage and the y-axis shows Capacitance. In order to measure the memory windows of a PGO thin film on a ZrO2 substrate, a Platinum (Pt) top electrode was deposited on the PGO surface with a shallow mask. The area of the top electrode was approximately 4×10−4 cm2. The PGO film had a thickness of approximately 1600 Angstroms and the ZrO2 layer had a thickness of approximately 130 Angstroms. The hysteresis in the C-V curve indicates a memory window of approximately 0.7 volts. The memory window typically will be between 0.1 to 3.0 volts. This is less than the 1.3 volt memory window for an 1800 Angstrom PGO film in a metal ferroelectric metal (MFM) structure.
  • FIG. 4 is a graph of a Capacitance-Voltage (CV) measurement of a Pt/PGO(180 nm)/Ir capacitor structure. The memory window shown is about 1.8 volts. [0021]
  • FIG. 5 is a graph of a leakage current (I-V) of a PGO film on a ZrO[0022] 2 film. As shown by the graph, the leakage current though the PGO/ZrO2 structure is very small, indicating that a good interface is maintained between the PGO, the ZrO2 and the Silicon substrate. In particular, the leakage current typically is less than 1×10−6 A/cm2 at 100 KV/cm.
  • FIG. 6 is a schematic of a preferred embodiment of the composite PGO/insulator layered structure, namely, a metal ferroelectric insulator semiconductor field effect transistor (MFISFET) including a PGO film on an insulator layer. [0023] Device 30 includes a Semiconductor substrate 32 such as a Silicon substrate, including a source region 34 and a drain region 36. An Insulator film 38 is positioned on substrate 32. Insulator film 38 may comprise Zirconium Oxide (ZrO2), Hafnium Oxide (HfO2), silicates of Zirconium or Hafnium, or mixtures of the above. The insulator film 38 may also comprise Aluminum Oxide, Yttrium Oxide, Calcium Oxide, Lanthanum Oxide, Titanium Oxide (TiO2), Tantalum Oxide (Ta2O5), doped ZrO2 or doped HfO2, Zr—Al—O, Hf—Al—O, Zr—Ti—O, Hf—Ti—O, and La—Al—O, and combinations thereof. The ferroelectric layer 40 comprises a single phase, c-axis Pb5Ge3O11 (PGO) film, positioned on insulator film 38. The ferroelectric PGO layer may be deposited by the method set forth in U.S. Pat. Registration No. 6,190,925, issued on Feb. 20, 2001, assigned to Sharp Laboratories of America, Inc., and entitled Epitaxially Grown Lead Germanate Film and Deposition Method, wherein said patent is incorporated herein by reference. By use of the disclosed PGO deposition method as set forth in the above listed patent, a PGO layer can be deposited with a substantially c-axis crystalline orientation, i.e., more than a 70% c-axis orientation, but may be as high as 80%. In a preferred embodiment, the PGO layer will have approximately a 90% c-axis orientation or better. A metal top electrode 42 is positioned on PGO film 40. The metal top electrode may comprise Platinum (Pt), Iridium (Ir), Tantalum (Ta), Ruthenium (Ru) or conductive oxides or alloys.
  • FIG. 7 is a flowchart of the method of making the PGO-on-insulator structure of the present invention. [0024] Step 50 comprises preparing the semiconductor substrate using any state of the art process including isolation and well formation. Step 52 comprises depositing the insulator film by any of the following means: physical vapor deposition (PVD); evaporation and oxidation; chemical vapor deposition (CVD); and atomic layer deposition. Step 54, if required, comprises post deposition annealing of the insulator film in forming gas or Oxygen ambient at a temperature up to 800 degrees Celsius. Step 56 comprises depositing the PGO film by any of the following methods: spin-on; physical vapor deposition; CVD; metal organic CVD (MOCVD); chemical solution deposition (CSD); and laser ablation. Step 58 comprises depositing the metal gate electrode on the PGO layer by any means known in the art. Step 60 comprises making any required contact and interconnect formations.
  • Thus, a single-phase, c-axis PGO thin film on an insulator for non-volatile memory applications, and a method for making the same, has been disclosed. Although preferred structures and methods of manufacturing the device have been disclosed, it should be appreciated that further variations and modifications may be made thereto without departing from the scope of the invention as defined in the appended claims. [0025]

Claims (20)

We claim:
1. A metal ferroelectric insulator semiconductor field effect transistor comprising:
a semiconductor;
a layer of insulator material positioned on said semiconductor; and
a layer of PGO positioned on said layer of insulator material.
2. The transistor of claim 1 wherein said insulator material is chosen from the group consisting of: Zirconium Oxide (ZrO2), Hafnium Oxide (HfO2), silicates of Zirconium, silicates of Hafnium, Aluminum Oxide, Yttrium Oxide, Calcium Oxide, Lanthanum Oxide, Titanium Oxide (TiO2), Tantalum Oxide (Ta2O5), doped ZrO2, doped HfO2, Zr—Al—O, Hf—Al—O, Zr—Ti—O, Hf—Ti—O, La—Al—O, and combinations thereof.
3. The transistor of claim 1 further comprising a top electrode layer positioned on said layer of PGO, wherein said top electrode layer is manufactured of a material chosen from the group consisting of: Platinum (Pt); Iridium (Ir); Tantalum (Ta); Ruthenium (Ru); a conductive oxide; and a conductive alloy.
4. The transistor of claim 1 wherein said layer of PGO comprises a single phase having a c-axis orientation throughout at least 70% of said layer of PGO.
5. The transistor of claim 3 wherein said transistor has a memory window in a range of 0.1 to 3.0 volts.
6. The transistor of claim 3 wherein said semiconductor includes a source region and a drain region.
7. The transistor of claim 1 wherein said layer of PGO has an at least 80% single-phase, c-axis orientation.
8. A thin film semiconductor structure comprising:
a substrate;
a layer of Zirconium Oxide positioned on said substrate; and
a ferroelectric layer of substantially single phase, c-axis oriented PGO positioned on said Zirconium Oxide layer.
9. The structure of claim 8 wherein said semiconductor structure is chosen from the group consisting of: a transistor; a capacitor; a pyroelectric infrared sensor; an optical display; an optical switch; a piezoelectric transducer; and a surface acoustic wave device.
10. The structure of claim 8 wherein said substrate comprises Silicon.
11. The structure of claim 8 wherein said semiconductor structure is a non-volatile memory device.
12. The structure of claim 8 further comprising an electrode positioned on said ferroelectric layer.
13. The structure of claim 8 wherein said ferroelectric layer has a thickness of at least 100 Angstroms.
14. The structure of claim 12 wherein said layer of Zirconium Oxide and said ferroelectric layer define a leakage current, and wherein said leakage current is less than 1×10−6 A/cm2 at 100 KV/cm.
15. A method of making a substantially single phase, c-axis PGO thin film on an insulator for use in a non-volatile memory device, comprising the steps of:
providing a semiconductor substrate;
depositing an insulator film on said semiconductor substrate; and
depositing a PGO film on said insulator film, wherein said PGO film comprises a substantially single phase, c-axis oriented film.
16. The method of claim 15 further comprising depositing a metal gate electrode on said PGO film.
17. The method of claim 15 wherein said semiconductor substrate comprises silicon and said insulator film is chosen from the group consisting of: Zirconium Oxide (ZrO2), Hafnium Oxide (HfO2), silicates of Zirconium, silicates of Hafnium, Aluminum Oxide, Yttrium Oxide, Calcium Oxide, Lanthanum Oxide, Titanium Oxide (TiO2), Tantalum Oxide (Ta2O5), doped ZrO2, doped HfO2, Zr—Al—O, Hf—Al—O, Zr—Ti—O, Hf—Ti—O, La—Al—O, and combinations thereof.
18. The method of claim 15 wherein said step of depositing said insulator film comprises a deposition method chosen from the group consisting of: physical vapor deposition (PVD); evaporation and oxidation; chemical vapor deposition (CVD); and atomic layer deposition.
19. The method of claim 15 wherein said step of depositing said PGO film comprises a deposition method chosen from the group consisting of: spin-on; physical vapor deposition; CVD; metal organic CVD (MOCVD); chemical solution deposition (CSD); and laser ablation.
20. The method of claim 16 wherein said metal gate electrode comprises a material chosen from the group consisting of: Platinum (Pt); Iridium (Ir); Tantalum (Ta); Ruthenium (Ru); a conductive oxide; and a conductive alloy.
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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050047252A1 (en) * 2002-01-11 2005-03-03 International Business Machines Corporation Rare earth metal oxide memory element based on charge storage and method for manufacturing same
US7026694B2 (en) 2002-08-15 2006-04-11 Micron Technology, Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
US7169673B2 (en) 2002-07-30 2007-01-30 Micron Technology, Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US7511326B2 (en) 2005-03-29 2009-03-31 Micron Technology, Inc. ALD of amorphous lanthanide doped TiOx films
US7554161B2 (en) * 2002-06-05 2009-06-30 Micron Technology, Inc. HfAlO3 films for gate dielectrics
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7670646B2 (en) 2002-05-02 2010-03-02 Micron Technology, Inc. Methods for atomic-layer deposition
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7719065B2 (en) 2004-08-26 2010-05-18 Micron Technology, Inc. Ruthenium layer for a dielectric layer containing a lanthanide oxide
US7727905B2 (en) 2004-08-02 2010-06-01 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7863667B2 (en) 2003-04-22 2011-01-04 Micron Technology, Inc. Zirconium titanium oxide films
US7867919B2 (en) 2004-08-31 2011-01-11 Micron Technology, Inc. Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer
US7915174B2 (en) 2004-12-13 2011-03-29 Micron Technology, Inc. Dielectric stack containing lanthanum and hafnium
US7989362B2 (en) 2006-08-31 2011-08-02 Micron Technology, Inc. Hafnium lanthanide oxynitride films
US8026161B2 (en) 2001-08-30 2011-09-27 Micron Technology, Inc. Highly reliable amorphous high-K gate oxide ZrO2
US8154066B2 (en) 2004-08-31 2012-04-10 Micron Technology, Inc. Titanium aluminum oxide films
US8501563B2 (en) 2005-07-20 2013-08-06 Micron Technology, Inc. Devices with nanocrystals and methods of formation
CN108328565A (en) * 2018-02-07 2018-07-27 华中科技大学 A kind of device based on controllable nano crackle and preparation method thereof and control method

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Publication number Priority date Publication date Assignee Title
US7554829B2 (en) 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
US7037574B2 (en) * 2001-05-23 2006-05-02 Veeco Instruments, Inc. Atomic layer deposition for fabricating thin films
US6844203B2 (en) 2001-08-30 2005-01-18 Micron Technology, Inc. Gate oxides, and methods of forming
US6664116B2 (en) * 2001-12-12 2003-12-16 Sharp Laboratories Of America, Inc. Seed layer processes for MOCVD of ferroelectric thin films on high-k gate oxides
US6900122B2 (en) 2001-12-20 2005-05-31 Micron Technology, Inc. Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics
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US6750066B1 (en) * 2002-04-08 2004-06-15 Advanced Micro Devices, Inc. Precision high-K intergate dielectric layer
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US7205218B2 (en) 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US7326988B2 (en) 2002-07-02 2008-02-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US6790791B2 (en) 2002-08-15 2004-09-14 Micron Technology, Inc. Lanthanide doped TiOx dielectric films
JP4887481B2 (en) * 2002-08-20 2012-02-29 独立行政法人産業技術総合研究所 Semiconductor ferroelectric memory device
US7199023B2 (en) 2002-08-28 2007-04-03 Micron Technology, Inc. Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
US7084078B2 (en) 2002-08-29 2006-08-01 Micron Technology, Inc. Atomic layer deposited lanthanide doped TiOx dielectric films
US7101813B2 (en) 2002-12-04 2006-09-05 Micron Technology Inc. Atomic layer deposited Zr-Sn-Ti-O films
US6958302B2 (en) 2002-12-04 2005-10-25 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films using TiI4
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US7192892B2 (en) 2003-03-04 2007-03-20 Micron Technology, Inc. Atomic layer deposited dielectric layers
US7135369B2 (en) 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US7192824B2 (en) 2003-06-24 2007-03-20 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectric layers
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US7071118B2 (en) * 2003-11-12 2006-07-04 Veeco Instruments, Inc. Method and apparatus for fabricating a conformal thin film on a substrate
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US7141857B2 (en) * 2004-06-30 2006-11-28 Freescale Semiconductor, Inc. Semiconductor structures and methods of fabricating semiconductor structures comprising hafnium oxide modified with lanthanum, a lanthanide-series metal, or a combination thereof
US7560395B2 (en) 2005-01-05 2009-07-14 Micron Technology, Inc. Atomic layer deposited hafnium tantalum oxide dielectrics
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US7390756B2 (en) 2005-04-28 2008-06-24 Micron Technology, Inc. Atomic layer deposited zirconium silicon oxide films
US20060272577A1 (en) * 2005-06-03 2006-12-07 Ming Mao Method and apparatus for decreasing deposition time of a thin film
KR101177277B1 (en) 2006-12-29 2012-08-24 삼성전자주식회사 Non-volatile memory device using metal-insulator transition material
JP6539900B2 (en) * 2013-07-25 2019-07-10 国立研究開発法人産業技術総合研究所 Ferroelectric device and method of manufacturing the same
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JP6751866B2 (en) 2016-04-22 2020-09-09 国立研究開発法人産業技術総合研究所 Manufacturing method of semiconductor ferroelectric storage element and semiconductor ferroelectric storage transistor
DE102018212736B4 (en) * 2018-07-31 2022-05-12 Christian-Albrechts-Universität Zu Kiel Semiconductor ferroelectric device having a mixed crystal ferroelectric memory layer and method of fabricating the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525357B1 (en) * 1999-10-20 2003-02-25 Agilent Technologies, Inc. Barrier layers ferroelectric memory devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6190925B1 (en) 1999-04-28 2001-02-20 Sharp Laboratories Of America, Inc. Epitaxially grown lead germanate film and deposition method
US6410343B1 (en) * 1999-04-28 2002-06-25 Sharp Laboratories Of America, Inc. C-axis oriented lead germanate film and deposition method
US6236076B1 (en) * 1999-04-29 2001-05-22 Symetrix Corporation Ferroelectric field effect transistors for nonvolatile memory applications having functional gradient material

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525357B1 (en) * 1999-10-20 2003-02-25 Agilent Technologies, Inc. Barrier layers ferroelectric memory devices

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8026161B2 (en) 2001-08-30 2011-09-27 Micron Technology, Inc. Highly reliable amorphous high-K gate oxide ZrO2
US8652957B2 (en) 2001-08-30 2014-02-18 Micron Technology, Inc. High-K gate dielectric oxide
US20050047252A1 (en) * 2002-01-11 2005-03-03 International Business Machines Corporation Rare earth metal oxide memory element based on charge storage and method for manufacturing same
US7078301B2 (en) 2002-01-11 2006-07-18 International Business Machines Corporation Rare earth metal oxide memory element based on charge storage and method for manufacturing same
US6894338B2 (en) * 2002-01-11 2005-05-17 International Business Machines Corporation Rare earth metal oxide memory element based on charge storage and method for manufacturing same
US7670646B2 (en) 2002-05-02 2010-03-02 Micron Technology, Inc. Methods for atomic-layer deposition
US7554161B2 (en) * 2002-06-05 2009-06-30 Micron Technology, Inc. HfAlO3 films for gate dielectrics
US7169673B2 (en) 2002-07-30 2007-01-30 Micron Technology, Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US8125038B2 (en) 2002-07-30 2012-02-28 Micron Technology, Inc. Nanolaminates of hafnium oxide and zirconium oxide
US7026694B2 (en) 2002-08-15 2006-04-11 Micron Technology, Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
US7863667B2 (en) 2003-04-22 2011-01-04 Micron Technology, Inc. Zirconium titanium oxide films
US8765616B2 (en) 2004-08-02 2014-07-01 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US8288809B2 (en) 2004-08-02 2012-10-16 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7727905B2 (en) 2004-08-02 2010-06-01 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7776762B2 (en) 2004-08-02 2010-08-17 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US8907486B2 (en) 2004-08-26 2014-12-09 Micron Technology, Inc. Ruthenium for a dielectric containing a lanthanide
US8558325B2 (en) 2004-08-26 2013-10-15 Micron Technology, Inc. Ruthenium for a dielectric containing a lanthanide
US7719065B2 (en) 2004-08-26 2010-05-18 Micron Technology, Inc. Ruthenium layer for a dielectric layer containing a lanthanide oxide
US7867919B2 (en) 2004-08-31 2011-01-11 Micron Technology, Inc. Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer
US8541276B2 (en) 2004-08-31 2013-09-24 Micron Technology, Inc. Methods of forming an insulating metal oxide
US8237216B2 (en) 2004-08-31 2012-08-07 Micron Technology, Inc. Apparatus having a lanthanum-metal oxide semiconductor device
US8154066B2 (en) 2004-08-31 2012-04-10 Micron Technology, Inc. Titanium aluminum oxide films
US7915174B2 (en) 2004-12-13 2011-03-29 Micron Technology, Inc. Dielectric stack containing lanthanum and hafnium
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US8102013B2 (en) 2005-03-29 2012-01-24 Micron Technology, Inc. Lanthanide doped TiOx films
US8076249B2 (en) 2005-03-29 2011-12-13 Micron Technology, Inc. Structures containing titanium silicon oxide
US8399365B2 (en) 2005-03-29 2013-03-19 Micron Technology, Inc. Methods of forming titanium silicon oxide
US7511326B2 (en) 2005-03-29 2009-03-31 Micron Technology, Inc. ALD of amorphous lanthanide doped TiOx films
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US8501563B2 (en) 2005-07-20 2013-08-06 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US8921914B2 (en) 2005-07-20 2014-12-30 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US8067794B2 (en) 2006-02-16 2011-11-29 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US8785312B2 (en) 2006-02-16 2014-07-22 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride
US7989362B2 (en) 2006-08-31 2011-08-02 Micron Technology, Inc. Hafnium lanthanide oxynitride films
CN108328565A (en) * 2018-02-07 2018-07-27 华中科技大学 A kind of device based on controllable nano crackle and preparation method thereof and control method

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KR100460595B1 (en) 2004-12-09
JP2003023140A (en) 2003-01-24

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