US7251801B2 - Method of designing circuit board - Google Patents
Method of designing circuit board Download PDFInfo
- Publication number
- US7251801B2 US7251801B2 US11/019,156 US1915604A US7251801B2 US 7251801 B2 US7251801 B2 US 7251801B2 US 1915604 A US1915604 A US 1915604A US 7251801 B2 US7251801 B2 US 7251801B2
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- Prior art keywords
- lines
- conductor lines
- circuit board
- conductor
- laid
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
Definitions
- the present invention relates to a method of designing a circuit board, and, more particularly, it relates to an improvement of the method of designing a circuit board applied to an electronic equipment, by computer-aided design (CAD).
- CAD computer-aided design
- An electronic equipment includes a semiconductor device itself such a semiconductor chip and/or other electrical/electronic elements or a circuit board having an electronic device mounted thereon.
- the electronic device and the circuit board forming the electronic equipment is designed to be smaller in size and higher in density.
- a high density circuit board is designed by a computer aided design (CAD).
- CAD computer aided design
- the circuit board is also named as a printed board, which is called as a circuit board here.
- the board covered is formed with a “rats nest”.
- This “rats nest” is used as road signs for laying conductor lines (for example, see Japanese Unexamined Patent Publication (Kokai) Nos. 4-34951, 9-91318, 10-171856, and 2003-345844).
- step S 100 a semiconductor device (electronic device) is drawn.
- step S 101 pads to which terminals of the electronic device are to be connected (in the case of wire bonding, bonding pads, while in the case of flip-chip, flip-chip connection pads) and external connection terminals are drawn.
- the external connection terminals are comprised of for example ball lands to which solder balls are mounted.
- the conductor lines include vias passing through the circuit board and via lands at the two ends of the vias.
- step S 102 the electronic devices are provisionally placed (for “floor plan”) at a designated region of the circuit board (region corresponding to external shape of circuit board).
- step S 103 the pads to which the terminals of the electronic devices are connected and the external connection terminals are connected by straight lines, and the pads to which the terminals of a plurality of electronic devices are connected are connected by straight lines.
- This group of straight lines is called a “rats nest” and serves as road signs for laying conductor lines.
- step S 104 the density of the rats nest is confirmed.
- a dense region of the rats nest also has dense conductor lines.
- the rats nest is preferably as sparse as possible.
- the routine returns to step S 102 , where the positions of the electronic devices themselves are moved so that the rats nest becomes sparse (correction of floor plan).
- step S 106 whether the arrangement and the laying of the conductor lines is possible or impossible is confirmed or checked.
- the routine returns to step S 102 , where the floor plan is redone.
- This method of designing the circuit board of the related art can be an effective means for the design of a circuit board with extra space for mounting parts, that is, a relatively large circuit board such as a mother board of a PC etc.
- the routine returns to the initial floor plan, and the arrangement of semiconductor devices is changed, the rats nest is formed, then the conductor lines are laid again.
- An object of the present invention is to provide a method of designing a circuit board enabling high density conductor lines to be drawn more efficiently.
- design rules enabling conductor lines to be laid are set and the conductor lines are laid in the region with the highest density of lines of the rats nest. After this, the design rules enabling conductor lines to be laid in the region with the highest density of lines of the rats nest are used to lay the conductor lines in the remaining regions.
- the region with the highest density of lines of the rats nest is the region where laying of the conductor lines is the most difficult, so if using the design rules set here, it is possible to lay the conductor lines reliably even in other regions. Therefore, it is possible to avoid the situation of the conductor lines being unable to be laid when reaching the final stage of laying the conductor lines. There is therefore little backtracking of the process and the conductor lines can be laid reliably in a short time.
- the number of design steps can be reduced down to about one-half that of the related art.
- FIG. 1 is a sectional view of an example of a semiconductor package designed according to the present invention
- FIGS. 2A to 2C are views of a typical example of some of the conductor lines of FIG. 1 , wherein FIG. 2A is a sectional view of a part A of FIG. 1 , FIG. 2B is a top view of FIG. 2A , and FIG. 2C is a bottom view of a see-through state of FIG. 2A ;
- FIG. 3 is a view of a control program setting design rules for designing a circuit board using a CAD
- FIG. 4 is a flow chart for explaining the method of designing a circuit board according to a first embodiment of the present invention
- FIGS. 5A to 5C are views of a display screen of a computer, wherein FIG. 5A is a view of a semiconductor device, FIG. 5B is a view of the semiconductor device and pads, and FIG. 5C is a view of a provisionally placed semiconductor device and rats nest;
- FIG. 6 is a view of part of a rats nest
- FIG. 7 is a view of an example of configuration of the density of a rats nest
- FIG. 8 is a view for explaining another example of the method of designing a circuit board
- FIGS. 9A to 9C show a reference example for setting design rules, wherein FIG. 9A is a top view, FIG. 9B is a sectional view, and FIG. 9C is a view in the see-through state;
- FIGS. 10A to 10C show an example of conductor lines laid according to the design rules of FIGS. 9A to 9C , wherein FIG. 10A is a top view, FIG. 10B is a sectional view, and FIG. 10C is a bottom view in the see-through state;
- FIGS. 11A to 11C show a reference example of conductor lines, wherein FIG. 11A is a top view, FIG. 11B is a sectional view, and FIG. 11C is a bottom view in the see-thru state;
- FIG. 12 is a view of an example of setting a line width of conductor lines and inter-line pitch
- FIGS. 13A to 13C show an example of conductor lines formed based on the rats nest of FIG. 12 , wherein FIG. 13A is a top view, FIG. 13B is a sectional view, and FIG. 13C is a bottom view in the see-through state;
- FIGS. 14A to 14C show a reference example for setting the design rules, wherein FIG. 14A is a top view, FIG. 14B is a sectional view, and FIG. 14C is a bottom view in the see-through state;
- FIGS. 15A to 15C show a reference example for setting the design rules, wherein FIG. 15A is a top view, FIG. 15B is a sectional view, and FIG. 15C is a bottom view in the see-through state;
- FIG. 16 is a flow chart for explaining the method of designing a circuit board according to a second embodiment of the present invention.
- FIG. 17 is a view of a circuit board having conductor lines formed by the design method of FIG. 16 ;
- FIG. 18 is a flow chart of the method of designing a circuit board of the related art.
- FIG. 1 shows an example of a semiconductor package including a circuit board to which the method of designing a circuit board according to the present invention is applied.
- the semiconductor package 10 is comprised of a circuit board 12 , a semiconductor device 16 mounted on the circuit board 12 by an adhesive 14 , and a resin 18 sealing the semiconductor device 16 .
- the semiconductor device 16 is a semiconductor chip formed with an integrated circuit and has terminals 20 formed along with the integrated circuit.
- the circuit board 12 is comprised of an insulating board made of glass epoxy etc.
- One major surface is formed with pads 22 to which terminals 20 of the semiconductor device 16 are connected.
- the terminals 20 of the semiconductor device 16 are connected to the pads 22 of the circuit board 12 by bonding wires 24 .
- the illustrated pads 22 are pads for wire bonding, but if the electrode configuration of the semiconductor device is a flip-chip configuration, the pads 22 can be made suitable for flip-chip bonding.
- the circuit board 12 has external connection terminals 26 at its other major surface.
- the external connection terminals 26 are formed as ball lands to which solder balls 28 are attached.
- the external connection terminals 26 will be called “ball lands” hereinafter, but the external connection terminals are not limited to ball lands.
- the semiconductor package 10 shown in FIG. 1 is generally called a ball grid array (BGA) type semiconductor package. It is mounted to a mother board (not shown) of electronic equipment using solder balls 28 .
- BGA ball grid array
- FIGS. 2A to 2C are views of a typical example of some of the conductor lines of FIG. 1 , wherein FIG. 2A is a sectional view of a part A of FIG. 1 , FIG. 2B is a top view of FIG. 2A , and FIG. 2C is a bottom view of see-through state of FIG. 2A .
- the pads 22 and ball lands 26 are electrically connected by conductor lines 30 .
- Each conductor line 30 includes a first linear part 32 provided on the first major surface of the circuit board 12 on which the semiconductor device 16 is mounted (hereinafter referred to as the “first side”), a second linear part 34 provided on the second major surface of the circuit board 12 on which the ball lands 26 are provided (hereinafter referred to as the “second side”), and a via 36 connecting the first linear part 32 and the second linear part 34 .
- the end of the via 36 at the first side is provided with a via land 38
- the end of the via 36 at the second side is provided with a via land 40 .
- the via lands 38 and 40 have areas larger than the via 36 .
- the via land 38 of the first side and the via land 40 of the second side usually have the same diameters.
- the diameters of the ball lands 26 are larger than the diameters of the via lands 38 and 40 .
- the circuit board 12 is formed with a plurality of conductor lines 30 at a high density.
- the conductor lines 30 are drawn by the routine explained below and are formed by selectively arranging a copper or other conductor layer on the circuit board 12 .
- FIG. 3 shows the configuration of a CAD system used for working the method of designing a circuit board according to the present invention.
- 50 indicates a CAD controller, 51 input information, and 52 output information.
- the input information 51 includes parts information 53 (external dimensions, number of pins, etc. of semiconductor device), net list (connection information) 54 , and design rules (initial values) 55 .
- This input information 51 is input by the user, that is, the circuit board designer, to the CAD controller 50 using a mouse, keyboard, or other input device.
- the CAD controller 50 draws a semiconductor device based on the parts information 53 or draws pads and ball lands from the parts information 53 and arranges these at suitable locations of the circuit board (parts arrangement 56 ).
- a rats nest is displayed from the parts layout 56 and the net list 54 (rats nest display 57 ).
- the arrangement information of the electronic device and rats nest are displayed as the output information 52 on the screen of the monitor 63 . Further, various information is displayed on the screen of the monitor 63 in accordance with need.
- this information is stored in a parts library 62 in the CAD controller 50 and is useful for design of parts.
- the region with the highest density of the rats nest displayed is extracted (dense region extraction 58 ).
- the conductor line laying control 59 is performed in accordance with the results.
- the design rules which the user inputs (initial values) 55 are incorporated once into the design rule file region 60 in the CAD controller 50 .
- design rules (initial values) 55 are used as initial values of the design rules of the conductor lines and the conductor lines are laid by the conductor line laying control 59 .
- the conductor line data of the densest part of the rats nest and the design rules at that time are output as the data file and simultaneously displayed on the monitor 63 .
- the design rules are changed while comparing them with the values of the database 61 stored in the CAD controller 50 , design rules enabling the conductor lines to be laid are searched for, and the conductor lines are laid.
- the output information 52 includes a data file 64 .
- the conductor lines can be laid (OK)
- the conductor line data of the densest part of the rats nest and the design rule at that time are output as the data 65 .
- FIG. 4 shows flow chart for explaining the method of designing a circuit board according to the present invention.
- This design method can be applied to mother boards, interposers, and many other circuit boards, but here the example of an interposer shown in FIG. 1 and FIGS. 2A to 2C will be explained.
- the mother board, interposer, or other circuit board comprises an insulating board made of polyimide or glass epoxy (dielectric board) on the surface and/or inside of which conductive wires are selectively arranged.
- insulating board made of polyimide or glass epoxy (dielectric board) on the surface and/or inside of which conductive wires are selectively arranged.
- material of the conductor lines in general a material mainly comprised of copper (Cu) is used.
- the semiconductor device 16 mounted on the circuit board 12 is drawn, based on the part information 53 ( FIG. 3 ) at step S 11 , using CAD.
- the circuit board 12 mounts a single semiconductor device 16 . Other times a plurality of semiconductor devices 16 are mounted on a common circuit board 12 .
- a semiconductor device 16 and other parts are mounted on a single circuit board 12 .
- step S 12 the pads corresponding to the electrodes of the semiconductor device 16 are drawn on one major surface (first surface) of the circuit board and the ball lands 26 are drawn on the other major surface (second surface) of the circuit board based on the net list 54 ( FIG. 3 ).
- step S 13 the semiconductor device 16 is floor-planned (provisionally placed) on in a designated region (region corresponding to external shape of circuit board 12 ). This corresponds to the parts arrangement 56 ( FIG. 3 ).
- step S 14 the rats nest is displayed (corresponding to rats nest display 57 ( FIG. 3 )).
- FIGS. 5A to 5C are views of a display screen of a computer, wherein FIG. 5A shows the external shape (maximum external shape) of the semiconductor device 16 drawn at step S 11 ( FIG. 4 ), while FIG. 5B shows the semiconductor device 16 and pads 22 corresponding to the electrodes of the semiconductor device 16 drawn at step S 12 ( FIG. 4 ). Further, FIG. 5C shows the semiconductor device 16 provisionally placed at steps S 13 and S 14 ( FIG. 4 ) and rats nest 44 .
- the rats nest 44 is only partially shown.
- the ball lands 26 drawn at step S 12 are shown in FIG. 5C .
- FIG. 6 shows part of a rats nest 44 in the case where the ball lands 26 are arranged in a concentrated manner.
- the rats nest 44 is formed by connecting the pads 22 and ball lands 26 , which are required to be electrically connected together, by lines 42 starting from the pads 22 and ending at the ball lands 26 .
- the rats nest 44 indicates the group of all lines 42 .
- the conductor lines 30 ( FIGS. 2A to 2C ) conductor line the pads 22 and the ball lands 26 , so the direction of extension and density of the lines 42 of the rats nest 44 substantially match with the direction of extension and density of the conductor lines 30 .
- the conductor lines 30 basically can be laid (drawn) along the lines 42 of the rats nest 44 .
- the lines 42 of the rats nest 44 are straight lines and are small in line width as well.
- the actual conductor lines 30 are not necessarily straight, and the line width must also be considered. Therefore, the actual laying of conductor lines is sometimes difficult.
- step S 15 the density of the rats nest 44 is confirmed and the region with the highest density of lines 42 of the rats nest 42 is extracted.
- the region with the dense lines 42 of the rats nest 44 is also dense with conductor lines 30 . In the region with the highest density of lines 42 of the rats nest 44 , laying the conductor lines 30 is also difficult.
- FIG. 7 An example of the technique for confirming the density of the rats nest 44 is shown in FIG. 7 .
- circuit board 12 (part of display of computer corresponding to circuit board 12 ) is divided into a plurality of regions and the region with the highest density of lines 42 of the rats nest 44 is extracted.
- the circuit board 12 is divided into 16 regions 12 A, 12 B, 12 C to 12 P.
- the densities of the rats nest in these regions are compared.
- the regions of dense rats nest 44 are so dense that they are filled in by the lines 42 of the rats nest 44 .
- the circuit board is preferably divided into four to 16 or so regions (in the case of a circuit board for a mobile phone).
- the external shapes of the divided regions were made equal squares, but shapes other than squares are also possible. Further, equal division is not required. The shapes can be selected in accordance with need.
- step S 16 the design rules relating to the routes and dimensions of the conductor lines 30 at the region with the highest density of lines 42 of the rats nest 44 are set and the conductor lines 30 are laid in the region with the highest density of lines 42 of the rats nest 44 .
- step S 17 it is confirmed whether or not the conductor lines 30 can be laid at the region with the highest density of lines 42 of the rats nest 44 .
- the design rules are set to
- the conductor lines are laid in the rats nest densest region based on the design rules.
- the input design rules (initial values) 55 are used to lay the conductor lines at step S 16 .
- step S 17 it is confirmed whether or not the conductor lines 30 can be laid at the region with the highest density of lines 42 of the rats nest 44 .
- step S 16 the routine returns to step S 16 , where setting of the design rules and the laying of the conductor lines are repeated at the region with the highest density of the lines 42 of the rats nest 44 .
- step S 16 alternative values for the design rules (initial values) are searched for from the data base 61 and the design rules are renewed. Further, the conductor lines are laid and the results of step S 17 are examined.
- step S 17 If it is judged at step S 17 that the conductor lines 30 can be laid in the region with the highest density of lines 42 of the rats nest 44 , the conductor lines 30 are laid in the remaining region at step S 18 ( FIG. 4 ).
- the conductor lines 30 are laid in accordance with the design rules set at step S 16 .
- the region with the highest density of the lines 42 of the rats nest 44 is the region where laying the conductor lines 30 is the most difficult, so if using the design rules set here, it is possible to lay the conductor lines reliably and easily at the other regions.
- step S 19 the wiring diagram is completed.
- the conductor lines 30 are formed on the circuit board 12 based on the wiring diagram.
- the routine proceeded until all conductor lines were laid at step S 18 ( FIG. 4 ), it was judged if the conductor lines could be laid at the final stage of laying the conductor lines, and, if not possible, the routine returned to step S 13 ( FIG. 4 ) where the design was redone.
- step S 18 In the design of the circuit board 12 , laying the conductor lines of step S 18 ( FIG. 4 ) is the process requiring the most time. If returning to the previous process after laying almost all conductor lines, the number of design steps greatly increases.
- feedback is performed at steps S 16 and S 17 .
- step S 16 right before step S 17 is returned to, the number of design steps can be greatly reduced, down to about one-half, compared with the method of related art.
- the basic priority order for setting the design rules is made (1) the arrangement of via lands considering suitable diameter, (2) line width of conductor lines and inter-line distance, (3) diameter of via lands, (4) diameter of ball lands, and (5) ball layout.
- the grounds for using this priority order are that, in the production of a circuit board, the positions of the via lands can be determined in advance to a certain extent at the initial stage and that the line width of the conductor lines and the inter-line distance can be changed relatively easily.
- the diameter of the via lands is related to the precision when forming the vias by drilling or laser boring. Further, the diameter of the ball lands is preferably kept from being made small as much as possible since contact area with the solder balls would become smaller if made smaller and the strength would fall when mounted to the mother board.
- the ball layout is related to the assembly jig (test socket or shipment tray) or mother board to be connected to.
- FIG. 8 shows another embodiment of the method of design of a circuit board according to the present invention.
- a single circuit board 12 mounts three electronic devices 16 A, 16 B, and 16 C.
- step S 14 of FIG. 4 the state in step S 14 of FIG. 4 is shown.
- Three electronic devices 16 A, 16 B, and 16 C to be mounted on the circuit board 12 are laid out in the floor plan, and a rats nest 44 is formed.
- This rats nest 44 is comprised by the lines (not shown in FIG. 8 ) interconnecting the pads 22 and the ball lands 26 , and the lines 42 connecting the pads corresponding to the three electronic devices 16 A, 16 B, and 16 C and the pads 22 corresponding to the other semiconductor devices.
- the design rules are set for the region 12 X.
- FIGS. 1 and 2A to 2 C the explanation will be given of an example of an interposer including two conductor layers ( FIGS. 1 and 2A to 2 C), but the present invention may also be applied to a circuit board including three or more conductor layers.
- the design of the circuit board becomes simpler by increasing the number of conductor layers, since the design rules for each conductor layer are eased.
- increasing the number of conductor layers invites a large rise in the cost of production (if increasing the number from two layers to four layers, the cost approximately doubles).
- FIGS. 9A to 9C show an example 56 a circuit board for explaining a reference example for setting a design rule, wherein FIG. 9A is a top view of the circuit board, FIG. 9C is a bottom view of the circuit board in the state seen from the top side in the see-through state, and FIG. 9B is a sectional view along the line X-X in FIG. 2A or FIG. 9C .
- the arrangement of the via lands 38 and 40 is set as follows.
- the via lands 38 and 40 are arranged near the ends of the lines 42 of the rats nest 44 , to reduce the portions of the conductor lines at the side of the circuit board 12 with a small area for conductor lines to be laid, that is, the side where the ball lands are arrayed.
- the first side (top side) of the circuit board 12 is provided with the first linear parts 32 and the via lands 38
- the second side (bottom side) of the circuit board 12 is provided with the second linear parts 34 , the via lands 40 , and the ball lands 26 .
- the second side has to be provided with the ball lands 26 , so there is no extra space for laying the conductor lines (low freedom of laying).
- the via lands 38 and 40 close to the ends of the lines 42 of the rats nest 44 , that is, close to the ball lands 26 , and to make the second linear parts 34 of the second side of the circuit board 12 shorter.
- FIGS. 10A to 10C show an example of conductor lines laid according to the design rules of FIGS. 9A to 9C , wherein FIG. 10A is a top view, FIG. 10C is a bottom view of the see-through state, and FIG. 10B is a sectional view along the line X-X in FIG. 10A or FIG. 10C .
- the via lands 38 and 40 are close to the ball lands 26 .
- the first side of the circuit board 12 is provided with the first linear parts 32 and the via lands 38 .
- the via lands 40 and the ball lands 26 are connected directly or through short second linear parts 34 .
- the second linear parts 34 can be made short and arranged near the ball lands 26 , the second linear parts 34 can be easily laid.
- FIGS. 11A to 11C show a reference example of conductor lines, wherein FIG. 11A is a top view, FIG. 11C is a bottom view in the see-through state, and FIG. 11B is a sectional view along the line X-X in FIG. 11A or FIG. 11C .
- the first side of the circuit board 12 is provided with the first linear parts 32 and the via lands 38
- the second side of the circuit board 12 is provided with the second linear parts.
- the plurality of second linear parts 34 have to be set between the adjoining columns of ball lands 26 .
- the pitch between the ball lands 26 is 0.8 mm and the diameter of the ball lands 26 is 0.55 mm, the distance between two ball lands 26 becomes 0.25 mm.
- the number of conductor lines which can be laid is limited to two.
- the interval between adjoining columns of the via lands 38 is 0.45 mm.
- FIG. 12 shows an example of setting the line width of the conductor lines and the inter-line distance.
- FIGS. 13A to 13C show an example of conductor lines formed based on the rats nest of FIG. 12 , wherein FIG. 13A is a top view, FIG. 13C is a bottom view of the see-through state, and FIG. 13B is a sectional view along the line X-X in FIG. 13A or 13 C.
- the rats nest 44 connecting the pads 22 B and via lands 38 positioned at one edge 12 E side of the circuit board 12 are dense.
- the conductor lines 32 connecting the pads 22 B and the via lands 38 are arranged at the region formed with the distance L between the pads 22 B and the edge 12 E of the circuit board 12 as shown in FIG. 13A .
- the distance L between the pads 22 B and the edge 12 E of the circuit board 12 is 1.1 mm, when laying 10 conductor lines there, distances of 10 conductor lines and 11 inter-line distances are required, i.e., 1.1 mm ⁇ (10+11) ⁇ 0.052 mm. That is, if the line width of the conductor lines 32 is 50 ⁇ m and the inter-line distance is 50 ⁇ m, the conductor lines can be laid.
- the numerical values of the line width of the conductor lines and the inter-line distance are made the same (50 ⁇ m/50 ⁇ m).
- the distance between the bottommost conductor line and the edge 12 E of the circuit board 12 and the inter-line distance are made the same, but they may also be made different.
- FIGS. 14A to 14C show a reference example for setting the design rules, wherein FIG. 14A is a plan view (top view), FIG. 14C is a bottom view of the see-through state, and FIG. 14B is a sectional view along the line X-X in FIG. 14A or 14 C.
- the remaining one conductor line connects the via lands 38 and 40 by a second line part 34 arranged at a different position from the ball lands 26 and laid at the second side of the circuit board 12 .
- the fourth conductor line is desirably laid at the first side of the circuit board 12 as shown by the arrow, but sometimes this is not possible.
- the line width of the two conductor lines is made 150 ⁇ m
- the line width of the remaining conductor lines is made 50 ⁇ m
- the inter-line distance is made 50 ⁇ m
- the interval between adjoining columns of via lands 38 is made 0.45 mm.
- one conductor line is laid at the second side of the circuit board between the column of via lands 40 and the column of ball lands 26 .
- the diameter of the ball lands 26 is 0.55 mm, the interval between adjoining columns of ball lands 26 is 0.25 mm, and the diameter of the via lands 40 is 0.35 mm, it is difficult to pass one conductor line between the column of via lands 40 and the column of ball lands 26 . Therefore, by changing the diameter of the via lands from 0.35 to 0.30 mm, it becomes possible to pass one conductor line with the-like width of 50 ⁇ m between a column of the via lands 40 and a column of the ball lands 26 . Conversely, it is also possible to leave the diameter of the via lands 40 as it is and change the diameter of the ball lands from 0.55 mm to 0.50 mm.
- FIGS. 15A to 15C shows a reference example in setting the design rule, wherein FIG. 15A is a top view, FIG. 15C is a bottom view in the see-through state, and FIG. 15B is a sectional view along the line X-X in FIG. 15A or FIG. 15C .
- this problem is dealt with by changing the diameter of the via lands 38 and 40 from 0.35 mm to 0.30 mm, but even so sometimes it is difficult to pass an conductor line between the column of the via lands 40 and the column of the ball lands 26 .
- this standard for determination of the design rules is preferably not used as much as possible.
- FIG. 16 is a flow chart explaining the method of designing a circuit board according to another embodiment of the present invention.
- FIG. 17 shows a circuit board having conductor lines formed by the design method of FIG. 16 .
- conductor lines 32 C there are the four critical net conductor lines 32 C. These conductor lines 32 C are for example power lines and other conductor lines with small inductance values.
- steps similar to steps S 11 to S 13 in the embodiment shown in FIG. 4 are performed, then step S 14 similar to the embodiment shown in FIG. 4 is executed and the rats nest is displayed.
- step S 21 to step S 24 the region with the highest density of lines of the rats nest is extracted, then the remaining conductor lines are laid while setting the design rules.
- the design rules are determined preferentially for a critical net.
- the rats nest is applied to complete the laying of the conductor lines, then all conductor lines are laid.
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JP2004238337A JP4275032B2 (en) | 2004-08-18 | 2004-08-18 | Circuit board design method |
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US7251801B2 true US7251801B2 (en) | 2007-07-31 |
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Also Published As
Publication number | Publication date |
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JP2006059013A (en) | 2006-03-02 |
US20060040532A1 (en) | 2006-02-23 |
JP4275032B2 (en) | 2009-06-10 |
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