New! View global litigation for patent families

US7169685B2 - Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive - Google Patents

Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive Download PDF

Info

Publication number
US7169685B2
US7169685B2 US10082372 US8237202A US7169685B2 US 7169685 B2 US7169685 B2 US 7169685B2 US 10082372 US10082372 US 10082372 US 8237202 A US8237202 A US 8237202A US 7169685 B2 US7169685 B2 US 7169685B2
Authority
US
Grant status
Grant
Patent type
Prior art keywords
layer
semiconductor
die
stress
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US10082372
Other versions
US20030162368A1 (en )
Inventor
Michael E. Connell
Tongbi Jiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Abstract

A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped are provided. The SBL may also serve as, or support, an adhesive layer for die attach, and be of a markable material for an enhance marking method.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to methods for making semiconductor dice. More specifically, the invention relates to methods and apparatus for balancing stress in a semiconductor die resulting from stress within a top side protective layer.

2. State of the Art

An individual integrated circuit semiconductor die is usually formed from a larger structure known as a semiconductor wafer. Wafers are usually formed by slicing a large cylindrically shaped crystal of silicon, although other materials such as gallium arsenide and indium phosphide are also used. The front side or surface of the wafer is first ground and polished to a smooth surface, for fabrication of multiple integrated circuits thereon. Each semiconductor wafer has a plurality of integrated circuits arranged in rows and columns with the periphery of each integrated circuit typically being substantially rectangular. In the electronics industry, there is a need for apparatus of smaller size, higher performance and higher memory storage. These factors drive the industry to produce smaller semiconductor dice by thinning each wafer, i.e., reducing the cross section using a mechanical and/or chemical grinding process or etching. After thinning, the wafer is sawn or diced into rectangularly shaped “dice” along two mutually perpendicular sets of parallel lines or streets separating each row and column of dice in the wafer. Thus, the individual integrated circuit semiconductor die in the form of semiconductor dice are singulated from the wafer.

Fabrication of the integrated circuits is performed on the active surface of the undivided wafer, and consists of various processes including known steps of layering, patterning, doping, etching and heat treatment, for example. Various layers applied to the active surface of the wafer typically include insulators, semiconductors and metallic conductors. The final layering step generally comprises the application of a passivation material to cover the integrated circuit with a smooth electrically insulative protective layer. The purpose of the passivation layer is to protect the electronic components on the active surface, i.e., front side during subsequent wafer thinning, die testing, die singulation from the wafer, die packaging, and use. Exemplary passivation materials include silicon dioxide and silicon nitride (doped or undoped with boron or phosphorus, for example), as well as other materials including polymer-based compositions as known in the art. Further protection from damage during thinning of the wafer back side may be provided by temporarily attaching an adhesive-backed polymer (e.g. vinyl) sheet to the front side of the wafer. Such is disclosed in U.S. Pat. No. 5,840,614 of Sim et al. and U.S. Pat. No. 6,030,485 of Yamada, in which a UV sensitive tape is attached to the active surface of a wafer and made removable by radiation following back side lapping. In U.S. Pat. No. 5,962,097 of Yamamoto et al., a protective member is removably attached to an active surface of a wafer by a pressure sensitive adhesive.

Wafer thinning is performed in order to (a) reduce the package size, (b) reduce the consumption of saw blades in subsequent die singulation from the wafer, and (c) remove any electrical junctions which have formed on the wafer back side during fabrication. The processes typically used for wafer thinning include mechanical grinding and chemical-mechanical polishing (CMP). Alternatively, etching may be used but is not generally preferred. Each of these processes requires protection of the front side or active surface of the wafer containing the electronic components of the semiconductor die and/or wafer. The wafer grinding/polishing step typically results in a somewhat rough back side which is not conducive to other semiconductor die manufacturing processes, such as direct laser marking of a semiconductor die.

Although wafer thinning produces semiconductor dice of much reduced size, it also tends to result in a higher incidence of semiconductor die breakage. In addition, stresses induced by any grinding and polishing processes must be carefully controlled to prevent wafer and semiconductor die warping or bowing. Wafer warp interferes with precise semiconductor die separation (singulation), and semiconductor die warping results in die-attach problems in subsequent packaging. In addition, warping may cause breakage of wire bonds, etc.

Stresses produced in a semiconductor die by application of a layer thereto may be classified as either “intrinsic” or result from “thermal mismatch” between the material of the semiconductor die and the material of the applied layer. In the former case, the applied layer may be in tensile or compressive stress as applied or cured. For example, a polymeric layer may shrink during a curing step to produce intrinsic compressive stress in the active surface of a semiconductor die to which it is attached. Stress resulting from thermal mismatch is particularly evident where the layer deposition is not done at room temperature. Upon cooling to ambient temperature or to a working temperature, different coefficients of expansion (CTE) result in differential contraction or expansion between the semiconductor die substrate, the wafer, and the applied layer. Each of these stress components is important in the fabrication of semiconductor die, particularly where the ratio of semiconductor die thickness to semiconductor die length (or width) is very low.

Application of an effective passivation layer to the front side of a wafer typically results in stresses in the wafer and the semiconductor die singulated therefrom. Stresses introduced by the passivation layer may be sufficient to produce undesirable warping in the semiconductor dice, particularly where the wafer has been thinned to a high degree. A rigid unwarped substrate is particularly critical in forming known-good-die (KGD) with wire bonds.

In one sawing method of singulation, the wafer back side is attached to a flexible plastic film to hold the individual semiconductor die in place during cutting. The film is subsequently separated and removed from the singulated semiconductor die, and has no effect upon die warping. In one version, the film is stretched to release the semiconductor dice, which are then simply picked off the film. The semiconductor dice may then be processed to form differing types of semiconductor packages.

In one commonly used die-attach method, an adhesive material (e.g., epoxy) is used to join the back side of a die to a carrier. The adhesive material may be insulative or be electrically conductive and heat conductive.

Layer formation on a wafer back side has been done for another purpose. Such layers have been applied to provide a smooth surface for marking a semiconductor die or wafer with indicia identifying the manufacturer, serial number, lot number, and/or bar code, for example.

Conventional laser marking techniques utilize a very high intensity beam of light to alter the surface of a semiconductor die by melting, burning, or ablating the device surface directly, or by discoloration or decoloration of a laser reactive coating applied to a surface of the bare semiconductor die or packaged semiconductor die. The beam of light may be scanned over the surface of the bare or packaged semiconductor die in the requisite pattern, or can be directed through a mask which projects the desired inscriptions onto the desired surface of the bare or packaged semiconductor die. The surface or coating of the semiconductor die thus modified, the laser marking creates a reflectivity difference from the rest of the surface of the semiconductor die.

Numerous methods for laser marking are known in the art. One method of laser marking involves applications where a laser beam is directed to contact the surface of a semiconductor device directly, as shown in U.S. Pat. No. 5,357,077 to Tsuruta, U.S. Pat. No. 5,329,090 to Woelki et al., U.S. Pat. No. 4,945,204 to Nakamura et al., U.S. Pat. No. 4,638,144 to Latta, Jr., U.S. Pat. No. 4,585,931 to Duncan et al., and U.S. Pat. No. 4,375,025 to Carlson.

Another method of laser marking makes use of various surface coating, e.g., carbon black and zinc borate, of a different color than the underlying device material. Two examples of this type of marking are described in U.S. Pat. No. 5,985,377 to Corbett and U.S. Pat. No. 4,707,722 to Folk et al.

In U.S. Pat. No. 5,866,644 to Mercx et al., molding compounds are disclosed which form products which may be laser marked. The molding compound contains a pigment as well as glass fibers for reinforcing the molded object.

The above-indicated methods have been found to be inadequate for marking the back side of a wafer or semiconductor die, inasmuch as the thinning methods, including mechanical grinding, chemical mechanical polishing, and etching all leave the back side in a nonsmooth condition with a surface topography unsuited for laser marking (with or without a thin surface coating).

Moreover, none of the coatings, if applied to the back side of a wafer or semiconductor die, will balance wafer stress or semiconductor die stress to prevent or significantly reduce warp.

BRIEF SUMMARY OF THE INVENTION

The present invention provides a method for balancing stresses resulting from application of a passivation layer or other layer on the front side of a semiconductor wafer. The term “passivation layer” will be used herein to denote any front side layer (compressive or tensile) which creates stress in the singulated die tending to form warp. The method and apparatus have particular application to wafers or semiconductor die which have been subjected to a thinning process, including backgrinding in particular. The present method comprises application of a stress-balancing layer (SBL) on the opposite side from a stress-creating layer such as a photoresist passivation layer, for example. Thus, a passivation layer covering the circuitry of each semiconductor die of a wafer will typically introduce compressive stresses into the dice; a stress-balancing layer (SBL) which is applied after wafer thinning but before singulation will result in individual semiconductor die in which the front side stresses and back side stresses are balanced, preventing dice warp.

The stress-balancing layer may be formed of a rigid material which resists deformation. The stress-balancing layer may be formed to have mechanical properties similar to the passivation layer and be applied under similar conditions so that the stress it creates on the die back side will approximately equal the stress on the die front side. The composition and thickness of the SBL may be varied to provide the desired balancing stress forces.

The stress-balancing layer may be applied by various methods. In a preferred method, an SBL may be applied by a chemical vapor deposition (CVD), epitaxy or other process over portions or all of the wafer back side. In particular, various CVD processes permit a uniform layer of material to be accurately deposited. Other methods which may be used to form the SBL on the back side include various evaporation methods and molecular beam epitaxy (MBE), for example.

The stress-balancing layer may comprise a composite of two or more materials. For example, semiconductor die having large aspect ratios may have formed thereon a rigid composite SBL having different reinforcing properties in the X and Y directions. Alternatively, two or more materials may be sequentially formed on the thinned wafer back side as a multilayer composite. Preferably, however, the stress-balancing layer comprises a single layer of a matrix material containing distributed particles of a reinforcing component which provide rigidity in the X-Y plane, and more preferably, in all directions. Careful selection of materials enables the SBL to be a very thin layer which contributes little to the overall Y-dimension of a die. The stress balancing layer of this invention is generally intended to be a permanent part of a semiconductor die. An exception to this rule is when a stress-causing layer requiring an SBL is subsequently removed or its stress causing effect otherwise ameliorated, in which case the SBL may optionally be removed. Inasmuch as the SBL is a very thin layer, and its removal would weaken the semiconductor die, it is generally considered to be a permanent part of the semiconductor die. Furthermore, the SBL may serve other purposes. For example, the SBL or adhesive applied thereto may comprise a laser markable material for applying indicia to each individual semiconductor die, as discussed infra. Also, the SBL may itself comprise an adhesive material useful for bonding the die back side to a substrate such as a circuit board.

In another aspect of the invention, an adhesive layer is applied to the highly planar stress-balancing layer for back side semiconductor die attachment to a package substrate, etc.

Application of the invention results in improved ease in the manufacture of semiconductor dice, with improved semiconductor die quality (planarity and wire bonds), and concomitant reduction in defective semiconductor die.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The nature of the present invention as well as other embodiments thereof may be more clearly understood by reference to the following detailed description of the invention, to the appended claims, and to the several drawings herein, wherein dimensions may be exaggerated for the sake of clarity, and wherein:

FIG. 1 is a schematic perspective view of a multidie semiconductor wafer that has been thinned and with visible die-separating streets;

FIG. 2A is a cross-sectional view of a semiconductor die with compressive stress applied thereto by a passivation layer on its front side to create die warp;

FIG. 2B is a cross-sectional view of a semiconductor die with tensile stress applied thereto by a passivation layer on its front side to create die warp;

FIGS. 3 through 10 are cross-sectional edge views of a portion of a semiconductor wafer during manufacturing processes to form semiconductor dice in accordance with the invention, wherein:

FIG. 3 is a cross-sectional view of a raw sliced wafer;

FIG. 4 is a cross-sectional view of a wafer following front side grinding and polishing;

FIG. 5 is a cross-sectional view of a wafer showing a plurality of representative electronic devices fabricated on the front side thereof;

FIG. 6 is a cross-sectional view of a wafer following deposition of a passivation layer over the electronic devices fabricated on the front side thereof;

FIG. 7 is a cross-sectional view of a wafer following back side thinning;

FIG. 8 is a cross-sectional view of a wafer following application of a stress-balancing layer on the thinned back side thereof;

FIG. 9 is a cross-sectional view of a wafer following curing of a stress-balancing layer on the thinned back side thereof;

FIG. 10 is a cross-sectional view of a semiconductor die following singulation of a wafer;

FIG. 11 is a simplified side view of a conventional backgrinding apparatus and semiconductor wafer mounted thereon;

FIG. 12 is a cross-sectional view of a wafer of the invention wherein an applied stress-balancing layer comprises a single component or a homogeneous mixture of more than one component;

FIG. 13 is a cross-sectional view of a wafer of the invention wherein an applied stress-balancing layer comprises a heterogeneous mixture of a reinforcing material in a matrix base material;

FIG. 14 is a cross-sectional view of a wafer of the invention wherein an applied stress-balancing layer comprises two separately applied sub-layers having reinforcement properties in different directions;

FIG. 15 is a cross-sectional view of a wafer following applying an adhesive layer to a stress-balancing layer on the thinned back side;

FIG. 16 is a cross-sectional view of wafer following attaching a carrier member to the stress-balancing layer in accordance with the invention;

FIG. 17A is a side view of an exemplary semiconductor die formed in accordance with the invention, illustrating a balancing of compressive stress;

FIG. 17B is a side view of another exemplary semiconductor die formed in accordance with the invention, illustrating a balancing of tensile stress;

FIG. 18 is a view of the back side of exemplary portions of a semiconductor wafer to which three forms of a stress-balancing layer are applied in accordance with the invention; and

FIG. 19 is a simplified schematic view of a conventional laser marking system.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to semiconductor dice 20 formed in a multidie wafer 10 as shown in FIG. 1. As depicted, wafer 10 is typically circular in shape with a circumferential edge 28. The circumferential edge 28 is shown with an optional upper beveled surface 38 for ease of handling without breakage. The wafer 10 may optionally be of another shape. Semiconductor dice 20 are configured with opposing major surfaces, front side or active surface 11 and back side 12. Electronic components, not shown in this figure, are fabricated in the wafer 10 front side, i.e., active surface 11 and will be identified herein as integrated circuits. Each semiconductor die 20 of the wafer 10 is bounded by “streets” or saw lines 26 in both the X and Y directions and has an integrated circuit with bond pads thereon. The back side 12 of wafer 10 typically is free from circuitry. Following fabrication of the integrated circuits, a layer 40A (FIG. 2A) of protective passivating material is typically applied to cover the circuitry and front side surfaces.

Turning now to FIG. 2A, a side cross-sectional view of a prior art semiconductor die 20A having a thickness 42 is shown with a passivation layer 40A having a thickness 44 joined to the front side 11. Some features are exaggerated for the sake of clarity. The passivation layer 40A is shown as having laterally “shrunk” relative to the semiconductor die 20A at the extant temperature, resulting in compressive lateral stress forces 16 acting at the die-layer interface 22. Reactive stress forces 18 in the semiconductor die 20A oppose the applied stress forces 16, and the stress forces 16, 18 result in what is denoted herein as compressive warp.

As shown in FIG. 2B, die 20B of a prior art is shown with passivation layer 40B joined to the front side 11. The passivation layer 40B has laterally “expanded” relative to the semiconductor die 20B, creating tensile lateral stress forces 16 acting at the die-layer interface 22. Reactive stress forces 18 in semiconductor die 20B oppose the applied stress forces 16, and the result is what is denoted herein as tensile warp.

The degree of warp, whether compressive or tensile, depends upon the aspect ratio of the semiconductor die 20 and the active stress forces 16, 18. Minimization or elimination of die warp is important to the manufacture of a high quality die with a minimum number of defects.

FIGS. 3 through 10 illustrate one embodiment of the method useful for balancing stresses in semiconductor dice 20.

A portion of a semiconductor wafer 10 is depicted in FIG. 3 as comprising a wafer substrate 32. The wafer 10 has a front side 11, an opposing back side 12, and a circumferential edge 28. The wafer 10 is sliced from a crystalline cylinder of a semiconductive material such as silicon, germanium, gallium arsenide, etc. which comprises the wafer substrate 32.

As shown in FIG. 4, the front side 11 of the wafer 10 is ground and polished to a smooth surface which becomes the active surface of each resulting semiconductor die 20. The portion 15 of the wafer substrate material removed from the wafer 10 reduces the wafer thickness 42. This planarization step is typically conducted by chemical-mechanical polishing (CMP).

The integrated microcircuits 30 are then fabricated in accordance with a pattern on the front side (active surface) 11 of the wafer's substrate 32. As shown in FIG. 5, each microcircuit 30 is associated with a semiconductor die 20 which will be singulated along streets 26 in a later step. The microcircuit 30 typically comprises various electronic components such as transistors, diodes, resistors, capacitors, insulators, conductors, and the like, as known in the art. Typically, a series of conductive “bond pads” on the active surface permit electrical connection of the microcircuit 30 to a circuit board, a testing machine, or to the microcircuit of another die or dice. Each microcircuit 30 is configured to provide a desired electronic result in a very small space.

Referring now to FIG. 6, it is seen that an electrically insulative passivation layer 40 is typically applied to cover the microcircuit 30 following circuit fabrication. The passivation layer 40 protects the microcircuit 30 from damage during subsequent manufacturing steps as well as in ultimate use. Unprotected, the microcircuit 30 may be degraded by contamination, chemical action, corrosion, and/or handling. Passivation layer 40 may comprise any of a variety of materials, including silicon dioxide and silicon nitride as examples. Such materials are typically applied by a chemical vapor deposition (CVP) process at elevated temperature. Thus, a difference in coefficient of thermal expansion (CTE) between the passivation layer 40 and the die material to which it is applied will result in a residual stress in the wafer 10, and in dice 20 when the wafer is diced (die singulation). For example, silicon has a CTE which is several times the CTE of silicon dioxide and will contract much more than a silicon dioxide passivation layer upon cooling from an elevated temperature, creating stress which is concentrated at the interface 22 between the wafer 10 and the passivation layer 40.

As depicted in FIG. 7, the back side 12 of the wafer 10 is then ground to reduce the wafer thickness 42 of the wafer substrate 32. In a conventional back-grinding process, illustrated in FIG. 11, a grinding wheel 52 with grinding surface 53 grinds away a portion 25 (see FIG. 7) of semiconductor wafer substrate 32 from the back side 12. Such grinding to fully thin the wafer thickness 42 typically leaves a somewhat nonsmooth ground surface 24 with grooves and/or swirls present. However, the unevenness makes the ground surface 24 conducive to later adhesive attachment of a stress-balancing layer 50 (FIG. 8) thereto.

As shown by the arrows in FIG. 11, grinding wheel 52 of backgrinding apparatus 60 typically rotates in one direction 54 while a platen 56 providing physical support for semiconductor wafer 10 rotates in another direction 58. This results in the grinding pattern referred to above, which tends to vary from one side of wafer 10 as opposed to the other. A submount 17, formed of tape, wax, molding compound, etc., typically provides protection for the active surface 11 of the unsingulated semiconductor die 20 formed on semiconductor wafer 10 as well as structural support during the thinning process.

Turning now to FIG. 8, in accordance with this invention, a stress-balancing layer (SBL) 50 is applied to the ground surface 24 to balance the stress created by the passivation layer 40 in the wafer substrate 32. The SBL 50 is configured to adhere tightly to the ground surface 24 and to oppose warping stresses in the wafer 10 as well as in the subsequently singulated semiconductor die 20.

The stress-balancing layer 50 may be formed in a variety of ways. For example, the SBL 50 may comprise a single rigid layer or a multifilm layer with each layer formed to resist deformation in a different direction, or with different deformation properties. In another form, homogeneously distributed inorganic particles may be bound in a matrix for uniform stress resistance in an X-Y plane, or optionally, omnidirectional. The stress-balancing layer 50 may be formed of any material or materials which when applied in a thin layer to the back side semiconductor die ground surface 24, will provide a rigid structure resistant to warping of the semiconductor die 20.

In the event that the stress-balancing layer 50 requires a curing step to fully harden the layer, it is conducted, typically by exposure to heat or radiation (see FIG. 9).

As shown in FIG. 12, an exemplary SBL 50 is shown as a single-component highly rigid layer such as, for example, a metal, alloy, metallorganic material, a photo-resist material or other material with the proper loadbearing characteristics.

In FIG. 13, SBL 50 is shown as a heterogeneous composite structure comprising uniformly distributed strong particles in a matrix material 74. For example, very small particles of reinforcing material 72 such as metal, glass, etc. may be distributed in a matrix material of silicon oxide, silicon nitride or a polymeric material.

In a further embodiment shown in FIG. 14, two or more layers of composite materials (depicted as 50A and 50B) are sequentially deposited as a stress-balancing layer 50. Each layer is shown with a reinforcing material 74A or 74B configured to resist stresses (i.e., have highest rigidity) in a particular direction, so that the layer combination provides the desired warping resistance.

Various methods may be used to deposit the materials forming the SBL 50. For example, the SBL 50 may be formed by an epitaxy process such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or complementary field effect transistor epitaxy (CMOSE). Sputtering and other methods may be used including physical vapor deposition (PVD). Preferably, a chemical vapor deposition (CVD) method is used. Various CVD methods include low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), metal-organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), and ultra-high vacuum chemical vapor deposition (UHVCVD), any of which may be used to produce a particular stress-balancing layer 50.

The SBL 50 may itself comprise an adhesive material, particularly when combined with added reinforcement particles. For example, polymeric materials known in the art may be applied to form a rigid structure, yet retain adhesive properties. Thus, semiconductor dice 20 formed therefrom may be adhesively attached to a circuit board or other substrate.

In an alternative embodiment of the present invention, an adhesive layer 48 may be applied to the stress-balancing layer 50, as depicted in FIG. 15. The adhesive layer 48 may be formed of a type of adhesive material characterized as being epoxy, or other suitable adhesive material. This adhesive layer 48 may be used as a die attach adhesive, or may be used to temporarily attach a carrier tape 62 to the wafer 10, as in FIG. 16. As discussed, infra, the adhesive layer 48 may also comprise a markable material such as a UV acrylic, thio-phene, poly-paraxylylene, (Paralene), urethanes, silicones, and acrylics, provided its strength is sufficient to resist die warping. Carrier tapes 62 are generally used to protect and hold the semiconductor dice 20 in place during sawing of the wafer 10 and enable convenient pick-off of individual semiconductor die 20 for transfer to a substrate in a semiconductor die 20 attach step.

Another embodiment of the invention utilizes a tape as a stress-balancing layer 50, wherein stresses in the plane of the tape are resisted by rigidity. The tape may be monolayer or multilayer and may be formed of or include a metal film. It is important to utilize an adhesive which will rigidly adhere to the tape and semiconductor die 20 as a very thin film. The tape may be thinly adhesed on both sides, for temporary attachment to a carrier tape 62 or for permanent semiconductor die attach to a circuit board or other substrate, not shown in the figures.

Whether the stress-balancing layer 50 is applied as a tape or as a CVD layer, it may be applied to overcover the entire thinned ground surface 24, or alternatively cover selected portions of the wafer 10 or of each semiconductor die 20. For example, as shown in FIG. 18, an SBL 50 may be applied in various patterns of stress-balancing layers 50X, 50Y and 50Z on the thinned semiconductor die back side 12 of each semiconductor die 20 of a wafer 10. As shown in these examples, stress-balancing layer 50X is configured to cover the entire back side 12 as a contiguous layer. In another embodiment, the stress-balancing layer 50Y may be patterned, for example, as a continuous longitudinal strip extending over a row of semiconductor dice 20. In a further variation, stress-balancing layers 50Z are shown as discrete coverings for each individual semiconductor die 20. The SBL 50Z is shown as comprising a rectangular covering over a majority of a semiconductor die back side 12. However, it may comprise any pattern 68 which achieves the desired stress balancing. If applied as a tape, stress-balancing layer 50 may be applied by an automated process such that the tape is in a highly regular and standard pattern corresponding to placement on predetermined specific areas on the semiconductor dice 20, or on wafer areas which will correspond to individual semiconductor dice after singulation. As such, vision systems for reading marks on semiconductor dice can be adjusted to scan the desired marked areas. In the view of FIG. 18, the outer surface 36 of the stress-balancing layers 50X, 50Y or 50Z is uniformly planar for subsequent semiconductor die attach.

Although the stress-balancing layer 50 may be sometimes usefully applied to already singulated semiconductor die 20, it is preferred to apply stress-balancing layer 50 to the wafer ground surface 24 prior to singulation, because this avoids warpage resulting from singulation and is generally more cost-effective.

Exemplary semiconductor dice 20C and 20D formed by the method of the invention are illustrated in FIGS. 17A and 17B. As illustrated in FIGS. 17A and 17B, a stress-balancing layer 50C or 50D is applied to the back side 12 of a semiconductor die 20C, 20D, respectively. This stress-balancing layer 50C or 50D balances reactive stress forces 18 in semiconductor die 20C or 20D caused by compressive or tensile stress forces 16 in passivation layers 40C and 40D, and maintain the semiconductor dice in a generally warp-free condition. The counter forces 70 in the SBL 50C, 50D balance the warping forces 16 in the passivation layers 40C, 40D.

The SBL 50 is particularly useful when it, or an adhesive layer 48 applied thereto, is configured to be used as an indicia marking layer. FIG. 19 illustrates in a simplified schematic view of a conventional laser marking system 100 capable of readily marking semiconductor dice 20 to which a laser markable material has been applied. The system 100 comprises a laser 102, a lens system 104, a shadow mask 106 and a laser control system 108 for monitoring and controlling the function of the apparatus. For purposes of this invention, a “laser” is considered to be any optical energy source capable of marking a surface of a stress-balancing layer 50 through the use of light energy and/or heat. Preferably, laser 102 is comprised of an Nd:YAG (yttrium aluminum garnet), Nd:YLP (pulsed yttrium fiber laser), carbon dioxide, or other suitable optical energy devices known in the art. It is understood, however, that laser 102 may also comprise an ultraviolet (UV) energy source or other energy beam. When laser 102 is energized, an intense beam of light 115 is projected from lens system 104 through shadow mask 106 onto the surface of the laser-markable material (SBL 50 or adhesive layer 48 applied thereto). When laser beam 115 impinges on laser markable material SBL 50 or adhesive layer 48, the material in, on, embedded in, attached to or under the material is altered, e.g., by heating, vaporization, burning, melting, chemical reaction, residue or dye transfer, or combinations thereof. The result comprises a color or texture change, or both, having an image of shadow mask 106 appearing on the ground surface 24 of the semiconductor die 20. Although a shadow mask 106 is shown in this embodiment, the present invention contemplates computer-directed operation, including mechanical movement of laser 102 in conjunction with, or without, shadow mask 106.

The stress-balancing layer 50 may advantageously be formed of a material which also has antistatic properties.

The present invention is applicable to semiconductor dice of any electronic or physical configuration, in which stresses tending to warp the semiconductor dice are present. Thus, for example, the semiconductor die may be one of a DIP, SIP, ZIP, PLCC, SOJ, SIMM, DIMM, LCC, QFP, SOP, TSOP, flip-chip, etc.

Thus, in the present invention, a stress-balancing layer 50 may be formed on the ground surface 24 of a semiconductor wafer 10 to balance warping stresses in the subsequently singulated semiconductor dice 20. In addition, the stress-balancing layer 50 may be configured to be or support a markable layer on the die's thinned ground surface 24. The stress-balancing layer 50 may also be configured to comprise or support a semiconductor die attach adhesive or carrier adhesive.

The stress-balancing layer 50 which is applied to the back side 12, ground surface 24 of a thinned wafer 10 may comprise only a very small portion of the Z dimension of the subsequently singulated dice. The wafer thickness 42 of the SBL 50 will depend upon the footprint size and thickness of the die and will generally be larger as the footprint increases. Typically, for the stresses normally encountered in small semiconductor dice 20, i.e., less than about 10 mm in the X and Y dimensions and less than about 1.5 mm in the Z dimension, the wafer thickness 42 of the SBL 50 is generally less than about 0.1 mm and effectively prevents or counteracts the tendency to warp. The SBL 50 may be formed of the same material as the stress-causing passivation layer 40 and be of a similar wafer thickness 42.

While the present invention has been disclosed herein in terms of certain exemplary embodiments, those of ordinary skill in the art will recognize and appreciate that it is not so limited. Various combinations or modifications to the disclosed embodiments may be effected without departing from the scope of the invention. Moreover, features from one embodiment may be combined with features from other embodiments.

For example, this invention, while being described with reference to semiconductor wafers containing integrated circuits and individual semiconductor dice, has equal utility to any type of substrate in which compressive or tensile stresses require balancing. Furthermore, the invention finds added utility where two or more of stress balancing, marking, adhesion, and surface protection of a substrate are desired to be simultaneously achieved. The scope of the instant invention is only to be limited by the claims which follow and equivalents thereof.

Claims (74)

1. A method for producing nonwarped semiconductor die from a wafer of a semiconductive material forming a substrate, said wafer of semiconductive material having a front side having integrated circuits formed on said semiconductive material, a back side, and a front side passivation layer on a portion of said wafer of semiconductor material causing a stress, said method comprising:
reducing a cross-section of said nonwarped semiconductor die by thinning said semiconductive material from said back side of said substrate for said nonwarped semiconductor die;
applying a stress-balancing layer to said wafer of semiconductor material substantially balancing said stress caused by said front side passivation layer; and
singulating said wafer of semiconductor material into a plurality of semiconductor dice.
2. A method in accordance with claim 1, wherein said front side passivation layer comprises a layer applied in fabrication of said nonwarped semiconductor die.
3. A method in accordance with claim 1, wherein said front side passivation layer comprises a layer of passivation material.
4. A method in accordance with claim 1, wherein said thinning comprises grinding.
5. A method in accordance with claim 1, wherein said thinning comprises a chemical-mechanical method.
6. A method in accordance with claim 1, wherein said semiconductor die comprises an integrated circuit semiconductor die.
7. A method in accordance with claim 1, wherein said stress-balancing layer comprises a layer substantially covering said back side.
8. A method in accordance with claim 1, wherein said stress-balancing layer comprises a strip covering a selected portion of a row of semiconductor dice on said wafer of semiconductor material.
9. A method in accordance with claim 1, wherein said stress-balancing layer comprises a plurality of portions, each portion of said plurality covering a selected portion of said thinned nonwarped semiconductor die on said wafer of semiconductive material.
10. A method in accordance with claim 9, wherein said selected portion comprises a majority of said thinned nonwarped semiconductor die.
11. A method in accordance with claim 1, wherein said stress-balancing layer comprises a film.
12. A method in accordance with claim 1, wherein said stress-balancing layer comprises a layer applied to said thinned nonwarped semiconductor die by one of a chemical vapor deposition (CVD) process, an evaporation process, and an epitaxy process.
13. A method in accordance with claim 1, wherein said stress-balancing layer comprises a layer applied to said thinned nonwarped semiconductor die by one of LPCVD, APCVD, MOCVD, PECVD, and UHVCVD.
14. A method in accordance with claim 1, wherein said stress-balancing layer comprises a layer applied to said thinned nonwarped semiconductor die by one of VPE, MBE, and CMOSE.
15. A method in accordance with claim 1, wherein said stress-balancing layer comprises a single homogeneous component.
16. A method in accordance with claim 15, wherein said stress-balancing layer comprises one of a metal, alloy, metalorganic material, photoresist material, and an organic polymer.
17. A method in accordance with claim 1, wherein said stress-balancing layer comprises a heterogeneous composite structure comprising reinforcing particles in a solid matrix material.
18. A method in accordance with claim 17, wherein said reinforcing particles comprise inorganic particles.
19. A method in accordance with claim 17, wherein said reinforcing particles comprise one of a metal, an alloy, glass, and a combination thereof.
20. A method in accordance with claim 17, wherein said reinforcing particles comprise particles for providing reinforcement in the X-Y plane of said stress-balancing layer.
21. A method in accordance with claim 17, wherein said reinforcing particles comprise particles for providing reinforcement in the X, Y, and Z directions.
22. A method in accordance with claim 17, wherein said solid matrix material comprises one of silicon dioxide, silicon nitride, and an organic polymeric material.
23. A method in accordance with claim 1, wherein said nonwarped semiconductor die comprises one of a DIP, SIP, ZIP, PLCC, SOJ, SIMM, DIMM, LOC, QFP, SOP, TSOP, and a flip-chip.
24. A method in accordance with claim 1, wherein said stress-balancing layer comprises a material markable with indicia.
25. A method in accordance with claim 22, wherein said stress-balancing layer comprises a material markable by optical radiation energy.
26. A method in accordance with claim 22, wherein said stress-balancing layer comprises a polytetrafluoroethylene tape.
27. A method in accordance with claim 25, further comprising exposing a portion of said material markable with optical energy exposing at least a portion of said material markable to one of a Nd:YAG (yttrium aluminum garnet), Nd:YLP (pulsed yttrium fiber laser) or carbon dioxide laser.
28. A method for producing nonwarped semiconductor die from a wafer having a front side, a back side, and a front side layer on a portion of said wafer causing a stress, said method comprising:
reducing a cross-section of said nonwarped semiconductor die by thinning said semiconductor die;
applying a stress-balancing layer to said wafer; and
applying a tape over said stress-balancing layer, said tape comprising a UV-penetrable polyvinyl chloride tape having an acrylic UV-sensitive adhesive disposed thereon;
exposing a portion of said tape with optical energy exposing at least a portion of said tape to one of a Nd:YAG, Nd-YLP or carbon dioxide laser; and singulating said wafer into a plurality of semiconductor dice.
29. A method in accordance with claim 28, wherein said stress-balancing layer comprises a first sublayer having high rigidity in the X-direction and a second sub-layer having high rigidity in the Y-direction.
30. A method in accordance with claim 28, wherein said stress-balancing layer comprises a layer having a coefficient of thermal expansion substantially similar to a coefficient of thermal expansion of said front side layer.
31. A method in accordance with claim 28, further comprising applying a die-attach adhesive to at least a portion of a surface of said stress-balancing layer.
32. A method in accordance with claim 28, further comprising applying a temporary reinforcement layer over at least a portion of said front side layer prior to thinning said back side.
33. A method for producing a small Z-dimension nonwarped semiconductor die from a semiconductor wafer of a semiconductive material forming a substrate, said semiconductive wafer of said semiconductive material having a front side having integrated circuits formed on said semiconductive material, a back side, and a stress applied thereto by a front side passivation layer, said method comprising:
reducing a cross-section of said small Z-dimension nonwarped semiconductor die by thinning semiconductive material from said back side thereof;
applying a rigid stress-balancing layer to a portion of said thinned back side for substantially balancing said stress of said front side passivation layer; and
singulating said semiconductor wafer into a plurality of nonwarped semiconductor dice.
34. A method in accordance with claim 33, wherein said front side passivation layer comprises a layer applied in a microcircuit fabrication step.
35. A method in accordance with claim 33, wherein said front side passivation layer comprises a layer of passivation material.
36. A method in accordance with claim 33, wherein said thinning comprises grinding by a grinding apparatus.
37. A method in accordance with claim 33, wherein said thinning comprises a chemical-physical method.
38. A method in accordance with claim 33, wherein said small Z-dimension nonwarped semiconductor die comprises an integrated circuit semiconductor die.
39. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a layer substantially covering said thinned back side.
40. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a strip covering a selected portion of a row of semiconductor dice on said semiconductor wafer.
41. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a plurality of discrete portions, each of said plurality of discrete portion covering a selected portion of said thinned back side of a die on said semicondutor wafer.
42. A method in accordance with claim 41, wherein said selected portion comprises a majority of said thinned die back side.
43. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a film.
44. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a layer applied to said thinned back side by one of a chemical vapor deposition (CVD) process, an evaporation process, and an epitaxy process.
45. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a layer applied to said thinned back side by one of LPCVD, APCVD, MOCVD, PECVD, and UHVCVD.
46. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a layer applied to said thinned back side by one of VPE, MBE, and CMOSE.
47. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a single homogeneous component.
48. A method in accordance with claim 47, wherein said rigid stress-balancing layer comprises one of a metal, alloy, metalorganic material, photoresist material, and an organic polymer.
49. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a heterogeneous composite structure comprising reinforcing particles in a solid matrix material.
50. A method in accordance with claim 49, wherein said reinforcing particles comprise particles of inorganic material.
51. A method in accordance with claim 49, wherein said reinforcing particles comprise one of a metal, an alloy, and glass.
52. A method in accordance with claim 49, wherein said reinforcing particles comprise particles for providing reinforcement in the X-Y plane of said rigid stress-balancing layer.
53. A method in accordance with claim 49, wherein said reinforcing particles comprise particles for providing reinforcement in the X, Y, and Z directions.
54. A method in accordance with claim 49, wherein said solid matrix material comprises one of silicon dioxide, silicon nitride, and an organic polymeric material.
55. A method in accordance with claim 33, wherein said small Z-dimension nonwarped semiconductor die comprises one of a DIP, SIP, ZIP, PLCC, SOJ, SM, DIMM, LOC, QFP, SOP, TSOP, and a flip-chip.
56. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a material markable with indicia.
57. A method in accordance with claim 56, wherein said rigid stress-balancing layer comprises a material markable by optical radiation energy.
58. A method in accordance with claim 56, wherein said rigid stress-balancing layer comprises a polytetrafluoroethylene tape.
59. A method for producing a small Z-dimension nonwarped semiconductor die from a semiconductor wafer having a front side, a back side, and a stress applied thereto by a front side layer, said method comprising:
reducing a cross-section of said small Z-dimension nonwarped semiconductor die by thinning said back side thereof;
applying a rigid stress-balancing layer to a portion of said thinned back side, said rigid stress-balancing layer comprising a material markable with indicia;
exposing a portion of said material markable with optical energy exposing at least a portion of said material markable to one of a Nd:YAG (yttrium aluminum garnet), Nd:YLP (pulsed yttrium fiber laser) or carbon dioxide laser; and
singulating said semiconductor wafer into a plurality of nonwarped semiconductor dice.
60. A method for producing a small Z-dimension nonwarped semiconductor die from a semiconductor wafer having a front side, a back side, and a stress applied thereto by a front side layer, said method comprising:
reducing a cross-section of said small Z-dimension nonwarped semiconductor die by thinning said back side thereof;
applying a rigid stress-balancing layer to a portion of said thinned back side;
applying a tape over said rigid stress-balancing layer, said tape comprising a UV-penetrable polyvinyl chloride tape having an acrylic UV-sensitive adhesive disposed thereon;
exposing a portion of said tape with optical energy exposing at least a portion of said tape to one of a Nd:YAG, Nd-YLP, or carbon dioxide laser; and
singulating said semiconductor wafer into a plurality of nonwarped semiconductor dice.
61. A method in accordance with claim 60, wherein said rigid stress-balancing layer comprises a first sublayer having high rigidity in the X-direction, and a second sublayer having high rigidity in the Y-direction.
62. A method in accordance with claim 60, wherein said rigid stress-balancing layer comprises a layer having a coefficient of thermal expansion substantially similar to that of said front side layer.
63. A method in accordance with claim 60, further comprising applying a die-attach adhesive to at least a portion of an outer surface of said rigid stress-balancing layer.
64. A method in accordance with claim 60, further comprising applying a temporary reinforcement layer over said front side layer prior to thinning said back side.
65. A method for producing low Z-dimension nonwarped semiconductor dice having a die front side, a die back side, and a stress applied thereto by a die front side passivation layer, said method comprising:
forming a semiconductor wafer of a semiconductive material, said semiconductive wafer of said semiconductive material having a front side, a back side, a plurality of microcircuits on said front side of said semiconductive material of said semiconductor wafer, and said die front side passivation layer applying stress to said semiconductor wafer;
reducing a cross-section of said semiconductor wafer by thinning said back side of said semiconductive material of said semicondutor wafer;
singulating said semiconductor wafer into a plurality of semiconductor dice; and
applying a rigid stress-balancing layer to said thinned back side of said semiconductive material of said semiconductor wafer under conditions which apply a back side stress generally equivalent to said front side stress of said die front side passivation layer upon restoration to conditions of use of said low Z-dimension nonwarped semiconductor die.
66. A method in accordance with claim 65, wherein said die front side passivation layer comprises a layer of passivation material.
67. A method in accordance with claim 65, wherein said rigid stress-balancing layer comprises a layer applied to said back side by one of a chemical vapor deposition (CVD) process, an evaporation process, and an epitaxy process.
68. A method in accordance with claim 65, wherein said rigid stress-balancing layer comprises a layer applied to said back side by one of LPCVD, APCVD, MOCVD, PECVD, and UHVCVD.
69. A method in accordance with claim 65, wherein said rigid stress-balancing layer comprises a layer applied to said back side by one of VPE, MBE, and CMOSE.
70. A method in accordance with claim 65, wherein said rigid stress-balancing layer comprises a single homogeneous component.
71. A method in accordance with claim 70, wherein said rigid stress-balancing layer comprises one of a metal, alloy, metalorganic material, photoresist material, and an organic polymer.
72. A method in accordance with claim 65, wherein said rigid stress-balancing layer comprises a heterogeneous composite structure comprising reinforcing particles in a solid matrix material.
73. A method in accordance with claim 72, wherein said reinforcing particles comprises particles of inorganic material.
74. A method in accordance with claim 72, wherein said reinforcing particles comprise one of a metal, an alloy, and glass.
US10082372 2002-02-25 2002-02-25 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive Active US7169685B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10082372 US7169685B2 (en) 2002-02-25 2002-02-25 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10082372 US7169685B2 (en) 2002-02-25 2002-02-25 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
US10706212 US20040104491A1 (en) 2002-02-25 2003-11-12 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as a die attach adhesive
US11269069 US7727785B2 (en) 2002-02-25 2005-11-07 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10706212 Division US20040104491A1 (en) 2002-02-25 2003-11-12 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as a die attach adhesive

Publications (2)

Publication Number Publication Date
US20030162368A1 true US20030162368A1 (en) 2003-08-28
US7169685B2 true US7169685B2 (en) 2007-01-30

Family

ID=27753075

Family Applications (3)

Application Number Title Priority Date Filing Date
US10082372 Active US7169685B2 (en) 2002-02-25 2002-02-25 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
US10706212 Abandoned US20040104491A1 (en) 2002-02-25 2003-11-12 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as a die attach adhesive
US11269069 Active 2023-02-14 US7727785B2 (en) 2002-02-25 2005-11-07 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive

Family Applications After (2)

Application Number Title Priority Date Filing Date
US10706212 Abandoned US20040104491A1 (en) 2002-02-25 2003-11-12 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as a die attach adhesive
US11269069 Active 2023-02-14 US7727785B2 (en) 2002-02-25 2005-11-07 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive

Country Status (1)

Country Link
US (3) US7169685B2 (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070007664A1 (en) * 2005-07-06 2007-01-11 Chung-Sun Lee Semiconductor package with molded back side and method of fabricating the same
US20070093038A1 (en) * 2005-10-26 2007-04-26 Andreas Koenig Method for making microchips and microchip made according to this method
US20070212812A1 (en) * 2006-03-07 2007-09-13 Stats Chippac Ltd. Wafer level chip scale package system with a thermal dissipation structure
US20070224718A1 (en) * 2006-03-22 2007-09-27 Texas Instruments Incorporated MEMS fabrication method
US20080029859A1 (en) * 2006-08-04 2008-02-07 Stats Chippac Ltd. Integrated circuit package system employing wafer level chip scale packaging
US20080237811A1 (en) * 2007-03-30 2008-10-02 Rohit Pal Method for preserving processing history on a wafer
US20090197394A1 (en) * 2008-02-04 2009-08-06 Micron Technology, Inc. Wafer processing
US20100075482A1 (en) * 2008-09-25 2010-03-25 Daryl Ross Koehl Bonded Wafer Assembly System and Method
US20120074591A1 (en) * 2010-09-29 2012-03-29 Varian Semiconductor Equipment Associates, Inc. Thin wafer support assembly
US8257985B2 (en) 2008-09-25 2012-09-04 Texas Instruments Incorporated MEMS device and fabrication method
US8455991B2 (en) 2010-09-24 2013-06-04 Stats Chippac Ltd. Integrated circuit packaging system with warpage control and method of manufacture thereof
US20140302642A1 (en) * 2012-11-15 2014-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage Control for Flexible Substrates
US8927334B2 (en) 2012-09-25 2015-01-06 International Business Machines Corporation Overcoming chip warping to enhance wetting of solder bumps and flip chip attaches in a flip chip package
US20150044783A1 (en) * 2013-08-12 2015-02-12 Micron Technology, Inc. Methods of alleviating adverse stress effects on a wafer, and methods of forming a semiconductor device
WO2015084848A2 (en) 2013-12-03 2015-06-11 Invensas Corporation Warpage reduction in structures with electrical circuitry
CN104157577B (en) * 2014-08-26 2016-11-02 上海华虹宏力半导体制造有限公司 The method of forming a semiconductor device
US9543255B2 (en) 2014-12-02 2017-01-10 International Business Machines Corporation Reduced-warpage laminate structure

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1447844A3 (en) * 2003-02-11 2004-10-06 Axalto S.A. Reinforced semiconductor wafer
JP4123027B2 (en) * 2003-03-31 2008-07-23 セイコーエプソン株式会社 A method of manufacturing a semiconductor device
JP2004361878A (en) * 2003-06-09 2004-12-24 Sano Fuji Koki Co Ltd Method for manufacturing chip type film deposited component
DE102004008475A1 (en) * 2004-02-20 2005-09-29 Infineon Technologies Ag Semiconductor chip breaking strength increasing method for use during manufacturing of chips, involves applying coating on backside of wafer for protecting chips from physical or chemical effects, where thickness of coating is large
US7470462B2 (en) * 2004-02-20 2008-12-30 Rochester Institute Of Technology Method to control residual stress in a film structure and a system thereof
US7135385B1 (en) 2004-04-23 2006-11-14 National Semiconductor Corporation Semiconductor devices having a back surface protective coating
US7015064B1 (en) * 2004-04-23 2006-03-21 National Semiconductor Corporation Marking wafers using pigmentation in a mounting tape
JP4878738B2 (en) * 2004-04-30 2012-02-15 株式会社ディスコ Processing method of the semiconductor device
US7432204B2 (en) * 2004-05-10 2008-10-07 Mosel Vitelic, Inc. Wafer and the manufacturing and reclaiming methods thereof
US6984876B2 (en) 2004-05-27 2006-01-10 Semiconductor Components Industries, L.L.C. Semiconductor device formed having a metal layer for conducting the device current and for high contrast marking and method thereof
US7459377B2 (en) 2004-06-08 2008-12-02 Panasonic Corporation Method for dividing substrate
JP2006049591A (en) * 2004-08-05 2006-02-16 Disco Abrasive Syst Ltd Fracture method and fracture equipment of adhesive film stuck on wafer
US7101620B1 (en) 2004-09-07 2006-09-05 National Semiconductor Corporation Thermal release wafer mount tape with B-stage adhesive
US7371630B2 (en) * 2004-09-24 2008-05-13 Intel Corporation Patterned backside stress engineering for transistor performance optimization
US7354790B2 (en) * 2005-01-19 2008-04-08 Lsi Logic Corporation Method and apparatus for avoiding dicing chip-outs in integrated circuit die
CN101847611B (en) * 2005-06-29 2012-05-23 罗姆股份有限公司 Semiconductor device
DE102005048826B3 (en) * 2005-10-10 2007-04-12 Infineon Technologies Ag Semiconductor component has pretensioned double-sided adhesive foil between back of semiconductor chip and chip connecting surface with circuit carrier to separate into individual areas without tools
US7871899B2 (en) * 2006-01-11 2011-01-18 Amkor Technology, Inc. Methods of forming back side layers for thinned wafers
US20070212813A1 (en) * 2006-03-10 2007-09-13 Fay Owen R Perforated embedded plane package and method
US8829661B2 (en) 2006-03-10 2014-09-09 Freescale Semiconductor, Inc. Warp compensated package and method
JP4786403B2 (en) * 2006-04-20 2011-10-05 エルピーダメモリ株式会社 Semiconductor device and manufacturing method thereof
US7880278B2 (en) * 2006-05-16 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having stress tuning layer
US8030138B1 (en) 2006-07-10 2011-10-04 National Semiconductor Corporation Methods and systems of packaging integrated circuits
US8293584B2 (en) * 2006-08-04 2012-10-23 Stats Chippac Ltd. Integrated circuit package system with filled wafer recess
US7422707B2 (en) * 2007-01-10 2008-09-09 National Starch And Chemical Investment Holding Corporation Highly conductive composition for wafer coating
US7750449B2 (en) * 2007-03-13 2010-07-06 Micron Technology, Inc. Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components
US7670931B2 (en) * 2007-05-15 2010-03-02 Novellus Systems, Inc. Methods for fabricating semiconductor structures with backside stress layers
US7749809B2 (en) * 2007-12-17 2010-07-06 National Semiconductor Corporation Methods and systems for packaging integrated circuits
US8048781B2 (en) * 2008-01-24 2011-11-01 National Semiconductor Corporation Methods and systems for packaging integrated circuits
US8115195B2 (en) * 2008-03-20 2012-02-14 Siltronic Ag Semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer
US20100015329A1 (en) * 2008-07-16 2010-01-21 National Semiconductor Corporation Methods and systems for packaging integrated circuits with thin metal contacts
JP2010027857A (en) * 2008-07-18 2010-02-04 Disco Abrasive Syst Ltd Semiconductor device manufacturing method
US8212346B2 (en) * 2008-10-28 2012-07-03 Global Foundries, Inc. Method and apparatus for reducing semiconductor package tensile stress
US9054111B2 (en) * 2009-04-07 2015-06-09 Freescale Semiconductor, Inc. Electronic device and method of packaging an electronic device
US20100314725A1 (en) * 2009-06-12 2010-12-16 Qualcomm Incorporated Stress Balance Layer on Semiconductor Wafer Backside
JP2011091286A (en) * 2009-10-26 2011-05-06 Fujitsu Semiconductor Ltd Method of manufacturing semiconductor device
CN102549716B (en) 2009-12-11 2016-08-03 国家半导体公司 Stress compensation backside of a semiconductor device based on gallium nitride or other nitride
CN102034912B (en) 2009-12-29 2015-03-25 比亚迪股份有限公司 Light-emitting diode epitaxial wafer, manufacturing method and manufacturing method of chip
JP5545000B2 (en) * 2010-04-14 2014-07-09 富士電機株式会社 A method of manufacturing a semiconductor device
CN102005521A (en) * 2010-11-16 2011-04-06 王卫国 Processing method of light-emitting diode (LED) chip
US8487405B2 (en) * 2011-02-17 2013-07-16 Maxim Integrated Products, Inc. Deep trench capacitor with conformally-deposited conductive layers having compressive stress
US9608130B2 (en) 2011-12-27 2017-03-28 Maxim Integrated Products, Inc. Semiconductor device having trench capacitor structure integrated therein
US9196672B2 (en) 2012-01-06 2015-11-24 Maxim Integrated Products, Inc. Semiconductor device having capacitor integrated therein
US9230888B2 (en) * 2013-02-11 2016-01-05 Henkel IP & Holding GmbH Wafer back side coating as dicing tape adhesive
US20140225231A1 (en) * 2013-02-12 2014-08-14 International Business Machines Corporation Modulating bow of thin wafers
US9882075B2 (en) 2013-03-15 2018-01-30 Maxim Integrated Products, Inc. Light sensor with vertical diode junctions
US9184041B2 (en) * 2013-06-25 2015-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit with backside structures to reduce substrate warp
WO2015157507A1 (en) * 2014-04-09 2015-10-15 Tokyo Electron Limited Method for correcting wafer bow from overlay
CN105810557A (en) * 2014-12-31 2016-07-27 格科微电子(上海)有限公司 Semiconductor wafer, flattening method therefor, and packaging method
DE102015217202A1 (en) * 2015-09-09 2017-03-09 Robert Bosch Gmbh Grave capacitor and method for manufacturing a capacitor grave
US20170178891A1 (en) * 2015-12-16 2017-06-22 Ostendo Technologies, Inc. Methods for Improving Wafer Planarity and Bonded Wafer Assemblies Made from the Methods

Citations (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444490B1 (en) *
US2357600A (en) 1942-08-24 1944-09-05 Walter W Pabst Conveyer
US2413767A (en) 1944-10-17 1947-01-07 Crucible Steel Company Conveyer mechanism
US2454548A (en) 1947-07-05 1948-11-23 Edward J Brinkert Lifting device
US2495541A (en) 1946-11-20 1950-01-24 Central Foundry Company Metal pouring apparatus for centrifugal castings
US3239218A (en) 1963-11-13 1966-03-08 Hudson D Reeves Wedge-type stack leveling platform for sheet material
US3254776A (en) 1964-04-10 1966-06-07 Socony Mobil Oil Co Inc Pipe handling and storage apparatus
US3327889A (en) 1965-03-08 1967-06-27 Pentwater Wire Products Inc Folding container
US3625384A (en) 1968-09-26 1971-12-07 Ibm Article-handling apparatus
US3628672A (en) 1970-01-05 1971-12-21 Streator Dependable Mfg Co Captive pallet for load-stacking racks
US3751587A (en) 1972-01-20 1973-08-07 Saxon Ind Inc Laser printing system
US3774352A (en) 1970-05-30 1973-11-27 Waldrich Werkzeugmasch Aligning device for workpieces on machine tool tables
US3799017A (en) 1972-09-14 1974-03-26 D Halligan Component lead cutter
US3837510A (en) 1971-01-21 1974-09-24 Williams J Mc Method of loading bagged mail from a loading dock into a highway vehicle
US3861969A (en) * 1970-03-31 1975-01-21 Hitachi Ltd Method for making III{14 V compound semiconductor devices
US3887997A (en) 1973-11-09 1975-06-10 Gen Motors Corp Magnetic alignment for semiconductor device bonding
US3903934A (en) 1974-12-31 1975-09-09 Mann Henry Inc Collapsible forming die
US3917983A (en) 1973-11-12 1975-11-04 Bunker Ramo Multiwafer electrical circuit construction and method of making
US3937386A (en) 1973-11-09 1976-02-10 General Motors Corporation Flip chip cartridge loader
US3969813A (en) 1975-08-15 1976-07-20 Bell Telephone Laboratories, Incorporated Method and apparatus for removal of semiconductor chips from hybrid circuits
US3973665A (en) 1975-03-07 1976-08-10 Gca Corporation Article delivery and transport apparatus for evacuated processing equipment
US4024545A (en) 1974-04-22 1977-05-17 Mb Associates Laser-excited marking system
US4027246A (en) 1976-03-26 1977-05-31 International Business Machines Corporation Automated integrated circuit manufacturing system
US4030622A (en) 1975-05-23 1977-06-21 Pass-Port Systems, Inc. Wafer transport system
US4058217A (en) 1973-05-01 1977-11-15 Unisearch Limited Automatic article sorting system
US4095095A (en) 1976-03-31 1978-06-13 Tokyo Shibaura Electric Co., Ltd. Apparatus for manufacturing semiconductor devices
US4097715A (en) 1977-05-16 1978-06-27 General Refractories Company Laser jet bell kiln
US4123044A (en) 1977-05-07 1978-10-31 Ludwig Riedhammer Gmbh & Co. K.G. Tunnel furnace
US4148057A (en) 1977-10-25 1979-04-03 Solution Sciences, Inc. Direct laser printing and forming apparatus
US4178531A (en) 1977-06-15 1979-12-11 Rca Corporation CRT with field-emission cathode
US4203486A (en) 1977-01-11 1980-05-20 Anchor Hocking Corporation Food preparation apparatus and process
US4285433A (en) 1979-12-19 1981-08-25 Western Electric Co., Inc. Method and apparatus for removing dice from a severed wafer
US4323755A (en) 1979-09-24 1982-04-06 Rca Corporation Method of making a machine-readable marking in a workpiece
US4346284A (en) 1980-06-18 1982-08-24 Philip Morris Incorporated Dual path web transport and processing apparatus with radiant energy directing means
US4352617A (en) 1979-04-12 1982-10-05 Murata Kikai Kabushiki Kaisha Bucket stacking and conveying apparatus
US4353796A (en) 1977-07-22 1982-10-12 Mitsubishi Mining & Cement Co., Ltd. Apparatus for digging and transporting soil and sand, stones and rocks, minerals and the like
US4354770A (en) 1980-05-19 1982-10-19 The United States Of America As Represented By The Secretary Of The Navy Wedge assembly
US4370542A (en) 1980-05-22 1983-01-25 Westland Aircraft Limited Cable marking method and apparatus
US4375025A (en) 1980-06-19 1983-02-22 Automated Industrial Systems, Inc. Laser strip marker
US4382580A (en) 1979-04-11 1983-05-10 Handelsbolaget Rodoverken Lifting and shifting apparatus
US4403134A (en) 1981-03-17 1983-09-06 Trumpf Gmbh & Co. Method and apparatus for cutting by means of a laser beam
US4454413A (en) 1982-02-19 1984-06-12 Precision Monolithics, Inc. Apparatus for tracking integrated circuit devices
US4461073A (en) 1982-10-27 1984-07-24 At&T Technologies, Inc. Device for inserting and extracting circuit modules with dual-in-line leads
US4493767A (en) 1983-04-28 1985-01-15 Guido Monteyne Conveyor belt for transporting slag material from a filtering apparatus
US4510673A (en) 1983-06-23 1985-04-16 International Business Machines Corporation Laser written chip identification method
US4513539A (en) 1983-03-15 1985-04-30 Acrometal Products, Inc. Position setting device for abrasive belt grinding machine
US4517436A (en) 1982-09-20 1985-05-14 Automated Industrial Systems Laser marker for articles of manufacture
US4523319A (en) 1983-05-10 1985-06-11 Brown University Laser tape systems
US4534695A (en) 1983-05-23 1985-08-13 Eaton Corporation Wafer transport system
US4539878A (en) 1983-10-31 1985-09-10 American Tech. Manufacturing, Inc. Method and apparatus for trimming the leads of electronic components
US4543716A (en) 1983-09-23 1985-10-01 The Wiremold Company Method and apparatus for electrical connection of flat cables
US4552271A (en) 1984-03-27 1985-11-12 Kranz Kermit W Collapsible container construction
US4561541A (en) 1983-09-26 1985-12-31 Spectrolab, Incorporated Carrier system for photovoltaic cells
US4577563A (en) 1984-07-11 1986-03-25 Sidler Karl J Safekeeping box assembly
US4585931A (en) 1983-11-21 1986-04-29 At&T Technologies, Inc. Method for automatically identifying semiconductor wafers
US4594263A (en) 1984-12-17 1986-06-10 Motorola, Inc. Laser marking method and ablative coating for use therein
US4607744A (en) 1984-09-10 1986-08-26 Pak Chong Il Method and apparatus for removing integrated circuit chips from a flexible carrier
US4610359A (en) 1983-02-23 1986-09-09 Licentia Patent-Verwaltungs-Gmbh Method for recognizing and sorting articles
US4616414A (en) 1985-03-13 1986-10-14 At&T Technologies, Inc. Method and apparatus for gripping multilead articles
US4626656A (en) 1984-07-19 1986-12-02 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for indicating the contact structure of electromagnetic contactor on the housing thereof using laser light
US4630513A (en) 1985-02-14 1986-12-23 Ernst Keller Automatic dip trimmer apparatus
US4638144A (en) 1985-04-24 1987-01-20 Automated Industrial Systems Indexing laser marker
US4644126A (en) 1984-12-14 1987-02-17 Ford Motor Company Method for producing parallel-sided melt zone with high energy beam
US4654290A (en) 1985-02-01 1987-03-31 Motorola, Inc. Laser markable molding compound, method of use and device therefrom
US4660282A (en) 1985-12-16 1987-04-28 Pfaff Wayne Method and apparatus for unloading electronic circuit packages from zero insertion force sockets
US4665298A (en) 1984-08-20 1987-05-12 Fiat Auto S.P.A. Apparatus for effecting treatment of metal workpieces by means of a power laser
US4677370A (en) 1985-10-31 1987-06-30 Unisys Corporation Method of testing wire bonds for defects using a magnetic field
US4696096A (en) 1986-02-21 1987-09-29 Micro Electronic Systems, Inc. Reworking methods and apparatus for surface mounted technology circuit boards
US4702788A (en) 1983-02-28 1987-10-27 Uzo Tomii Method of receiving small-sized electronic parts
US4707722A (en) 1984-12-17 1987-11-17 Motorola, Inc. Laser marking method and ablative coating for use therein
US4711334A (en) 1986-08-28 1987-12-08 Barry Joseph A Telescopic chute for mixer discharge
US4718531A (en) 1986-02-24 1988-01-12 Amp Incorporated Electrical connector pick-up station
US4719502A (en) 1985-08-07 1988-01-12 Kabushiki Kaisha Toshiba Epoxy resin composition, and resin-sealed semiconductor device in which this composition is used
US4720317A (en) 1985-02-14 1988-01-19 Bando Chemical Industries, Ltd. Method for dicing a semiconductor wafer
US4749631A (en) 1986-12-04 1988-06-07 Dow Corning Corporation Multilayer ceramics from silicate esters
US4753863A (en) 1985-02-01 1988-06-28 Motorola Inc. Laser markable molding compound
US4756977A (en) 1986-12-03 1988-07-12 Dow Corning Corporation Multilayer ceramics from hydrogen silsesquioxane
US4759675A (en) 1984-03-22 1988-07-26 Sgs-Thomson Microelectronics, Inc. Chip selection in automatic assembly of integrated circuit
US4767984A (en) 1985-10-04 1988-08-30 Amp Incorporated Protective fixture for chip carrier
US4769345A (en) 1987-03-12 1988-09-06 Olin Corporation Process for producing a hermetically sealed package for an electrical component containing a low amount of oxygen and water vapor
US4772079A (en) 1986-09-26 1988-09-20 General Electric Co. Cover assembly for removably mounted electronic equipment
US4778326A (en) 1983-05-24 1988-10-18 Vichem Corporation Method and means for handling semiconductor and similar electronic devices
US4791267A (en) 1987-01-28 1988-12-13 Mitsubishi Denki Kabushiki Kaisha Method of forming identifying indicium on cathode ray tubes
US4790515A (en) 1987-07-27 1988-12-13 Silvano Pocci Force multiplier useful as a lifting device
US4818835A (en) 1987-03-02 1989-04-04 Hitachi, Ltd. Laser marker and method of laser marking
US4821151A (en) 1985-12-20 1989-04-11 Olin Corporation Hermetically sealed package
US4832612A (en) 1986-10-31 1989-05-23 Amp Incorporated Protective carrier and securing means therefor
US4850780A (en) 1987-09-28 1989-07-25 Kulicke And Soffa Industries Inc. Pre-peel die ejector apparatus
US4861620A (en) 1986-11-14 1989-08-29 Mitsubishi Denki Kabushiki Kaisha Method of laser marking
US4884420A (en) 1986-02-24 1989-12-05 Dennis E. McGoldrick, Trustee Cage with floating nut assembly
US4891242A (en) 1986-07-05 1990-01-02 Kabushiki Kaisha Toyoda Jidoshokki Seisakusho Substrate of a hybrid ic, method of forming a circuit pattern and apparatus of forming the same
US4914269A (en) 1989-07-24 1990-04-03 Micron Technology, Inc. Method of sealing a ceramic lid on a ceramic semiconductor package with a high-power laser
US4916293A (en) 1987-02-25 1990-04-10 Rolls-Royce Plc Identification in manufacture
US4926677A (en) 1987-12-03 1990-05-22 Kurt Waldner Die apparatus
US4945204A (en) 1988-11-10 1990-07-31 Mitsubishi Denki Kabushiki Kaisha Method of laser-marking semiconductor devices
US4944492A (en) 1988-06-24 1990-07-31 Matsuo Engineering Co., Ltd. Wedge-type jack apparatus for raising structure while sustaining very large pressure due to same and temporarily supporting the structure
US4947981A (en) 1989-04-13 1990-08-14 Dorner Mfg. Corp. Apparatus for inverting articles
US4967260A (en) 1988-05-04 1990-10-30 International Electronic Research Corp. Hermetic microminiature packages
US4965927A (en) 1989-09-21 1990-10-30 Eli Holzman Apparatus for applying surface-mounted electronic components to printed circuit boards
US4990051A (en) 1987-09-28 1991-02-05 Kulicke And Soffa Industries, Inc. Pre-peel die ejector apparatus
US5183783A (en) * 1990-12-28 1993-02-02 Shin-Etsu Handotai Co., Ltd Method for production of dielectric-separation substrate
US5663096A (en) * 1990-02-14 1997-09-02 Nippondenso Co., Ltd. Method of manufacturing a vertical semiconductor device with ground surface providing a reduced ON resistance
US5701084A (en) * 1995-09-22 1997-12-23 Magnetrol International, Inc. Insulated capacitance probe
US5780311A (en) * 1992-06-17 1998-07-14 Harris Corporation bonded wafer processing
US5827771A (en) * 1996-03-19 1998-10-27 Raytheon Company Readout backside processing for hybridization
US5827711A (en) * 1997-03-20 1998-10-27 Incyte Pharmaceuticals, Inc. Succinate-ubiquinone reductase subunit
US5856230A (en) * 1996-12-31 1999-01-05 Hyundai Electronics Industries Co., Ltd. Method for making field oxide of semiconductor device
US5893760A (en) * 1996-03-27 1999-04-13 Kabushiki Kaisha Toshiba Method of heat treating a semiconductor wafer to reduce stress
US6303471B1 (en) * 1998-10-14 2001-10-16 Nippon Telegraph And Telephone Corporation Method of manufacturing semiconductor device having reinforcing member and method of manufacturing IC card using the device
US6323060B1 (en) * 1999-05-05 2001-11-27 Dense-Pac Microsystems, Inc. Stackable flex circuit IC package and method of making same
US20020048906A1 (en) * 2000-10-20 2002-04-25 Tadahiko Sakai Semiconductor device, method of manufacturing the device and mehtod of mounting the device
US6444490B2 (en) * 1998-06-26 2002-09-03 International Business Machines Corporation Micro-flex technology in semiconductor packages
US6489178B2 (en) * 2000-01-26 2002-12-03 Texas Instruments Incorporated Method of fabricating a molded package for micromechanical devices
US20030011765A1 (en) * 2001-07-03 2003-01-16 Xie Xiaoliang Sunney System and method for polarization coherent anti-stokes raman scattering microscopy
US20030017652A1 (en) * 1999-02-15 2003-01-23 Masako Sakaki Semiconductor device, its fabrication method and electronic device
US6579748B1 (en) * 1999-05-18 2003-06-17 Sanyu Rec Co., Ltd. Fabrication method of an electronic component
US6603191B2 (en) * 2000-05-18 2003-08-05 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US6656820B2 (en) * 2000-11-08 2003-12-02 Sharp Kabushiki Kaisha Method for manufacturing a semiconductor device having a reliable thinning step

Family Cites Families (195)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US577162A (en) * 1897-02-16 schiemer
CA843232A (en) 1970-06-02 Colas Francois Handling pallets
FR1284603A (en) 1961-01-05 1962-02-16 removable shelf camping, forming support and flame for portable stoves
US5014159A (en) * 1982-04-19 1991-05-07 Olin Corporation Semiconductor package
JPH0115144B2 (en) 1983-01-18 1989-03-15 Mitsubishi Electric Corp
US5158818A (en) 1984-01-30 1992-10-27 National Starch And Chemical Investment Holding Corporation Conductive die attach tape
US4915565A (en) * 1984-03-22 1990-04-10 Sgs-Thomson Microelectronics, Inc. Manipulation and handling of integrated circuit dice
US5245166A (en) 1987-04-20 1993-09-14 Cognitronics Imaging Systems, Inc. Method of processing a document carrying two kinds of indicia
US5102291A (en) * 1987-05-21 1992-04-07 Hine Design Inc. Method for transporting silicon wafers
DE3731835A1 (en) 1987-09-22 1989-03-30 Siemens Ag color printing, laser-induced
DE59002516D1 (en) 1989-04-06 1993-10-07 Ciba Geigy Laser marking ceramic materials, glazes, glass ceramics and glasses.
US5020959A (en) 1989-04-14 1991-06-04 Universal Instruments Corporation Adjustable shutter for containment of electrical components in tape feeders
US5127837A (en) 1989-06-09 1992-07-07 Labinal Components And Systems, Inc. Electrical connectors and IC chip tester embodying same
US5289113A (en) * 1989-08-01 1994-02-22 Analog Devices, Inc. PROM for integrated circuit identification and testing
US5003251A (en) * 1989-09-12 1991-03-26 Grumman Aerospace Corporation Bar code reader for printed circuit board
JPH03106721A (en) * 1989-09-21 1991-05-07 Mitsubishi Electric Corp Vertical wafer transfer device
US5204987A (en) * 1990-01-12 1993-04-20 Hans Klingel Apparatus for treating steel edges of skis and other runner devices
US5128737A (en) 1990-03-02 1992-07-07 Silicon Dynamics, Inc. Semiconductor integrated circuit fabrication yield improvements
GB9005872D0 (en) * 1990-03-15 1990-05-09 British Aerospace A laser markable white pigment composition
CA2014800A1 (en) 1990-04-18 1991-10-18 Siegfried Dojnik Die press unloader
US5018938A (en) * 1990-05-18 1991-05-28 At&T Bell Laboratories Method and apparatus for separating chips
US5153034A (en) 1990-05-23 1992-10-06 Binks Manufacturing Company Paint spray booth with plenum means of reduced cross section and method of operating the same
USH906H (en) * 1990-06-04 1991-04-02 The United States Of America As Represented By The United States Department Of Energy Wedge assembly for electrical transformer component spacing
US5043657A (en) 1990-07-13 1991-08-27 Analog Devices, Incorporated Marking techniques for identifying integrated circuit parts at the time of testing
JP2921937B2 (en) 1990-07-18 1999-07-19 東京エレクトロン株式会社 Ic inspection equipment
US5118369A (en) 1990-08-23 1992-06-02 Colorcode Unlimited Corporation Microlabelling system and process for making microlabels
US5219765A (en) 1990-09-12 1993-06-15 Hitachi, Ltd. Method for manufacturing a semiconductor device including wafer aging, probe inspection, and feeding back the results of the inspection to the device fabrication process
JPH07123101B2 (en) * 1990-09-14 1995-12-25 株式会社東芝 Semiconductor device
US5197650A (en) * 1990-09-18 1993-03-30 Sharp Kabushiki Kaisha Die bonding apparatus
US5175774A (en) 1990-10-16 1992-12-29 Micron Technology, Inc. Semiconductor wafer marking for identification during processing
DE69130962T2 (en) 1990-11-07 1999-10-28 Teijin Ltd Polyester resin composition
US5260542A (en) 1990-11-30 1993-11-09 Hitachi, Ltd. Laser Marking apparatus
US5117963A (en) 1990-12-12 1992-06-02 Micron Technology, Inc. System for automated handling of symmetrical supply tubes
DE69219165T2 (en) * 1991-01-11 1997-08-07 Texas Instruments Inc Testing and baking system for a wafer and method for their preparation
US5653900A (en) 1991-01-17 1997-08-05 United Distillers Plc Dynamic laser marking
JPH07114319B2 (en) * 1991-01-22 1995-12-06 松下電器産業株式会社 Supply device of chip-type electronic parts
JPH04300126A (en) * 1991-03-27 1992-10-23 Matsushita Electric Ind Co Ltd Assembly device
US5302798A (en) * 1991-04-01 1994-04-12 Canon Kabushiki Kaisha Method of forming a hole with a laser and an apparatus for forming a hole with a laser
US5090664A (en) * 1991-04-10 1992-02-25 General Electric Company Combination jack and roller for precision movement of heavy loads
US5258236A (en) 1991-05-03 1993-11-02 Ibm Corporation Multi-layer thin film structure and parallel processing method for fabricating same
US5278442A (en) * 1991-07-15 1994-01-11 Prinz Fritz B Electronic packages and smart structures formed by thermal spray deposition
US5375320A (en) 1991-08-13 1994-12-27 Micron Technology, Inc. Method of forming "J" leads on a semiconductor device
US5335458A (en) 1991-09-23 1994-08-09 Read-Rite Corporation Processing of magnetic head flexures with slider elements
US5315094A (en) 1991-09-23 1994-05-24 R. R. Donnelley & Sons Co. Automated receiving station for inventorying stock items
JP2862413B2 (en) 1991-10-02 1999-03-03 ポリプラスチックス株式会社 Laser marking method
US5177368A (en) * 1991-10-18 1993-01-05 The Coca-Cola Company Method and device for corrupting bar codes on articles prior to packing
US5218894A (en) 1991-10-31 1993-06-15 Amp Incorporated Apparatus and method for cutting a pin header
US5300172A (en) * 1991-11-01 1994-04-05 The Furukawa Electric Co., Ltd. Surface-protection method during etching
US5148969A (en) 1991-11-27 1992-09-22 Digital Equipment Corporation Component reclamation apparatus and method
US5290134A (en) * 1991-12-03 1994-03-01 Advantest Corporation Pick and place for automatic test handler
US5313156A (en) 1991-12-04 1994-05-17 Advantest Corporation Apparatus for automatic handling
US5323051A (en) 1991-12-16 1994-06-21 Motorola, Inc. Semiconductor wafer level package
US5256578A (en) 1991-12-23 1993-10-26 Motorola, Inc. Integral semiconductor wafer map recording
US5294770A (en) * 1992-01-14 1994-03-15 Alza Corporation Laser tablet treatment system with dual access to tablet
US5332463A (en) 1992-01-15 1994-07-26 Cray Research, Inc. Self-aligned sealing fixture for use in assembly of microelectronic packages
US5279975A (en) * 1992-02-07 1994-01-18 Micron Technology, Inc. Method of testing individual dies on semiconductor wafers prior to singulation
US5319183A (en) 1992-02-18 1994-06-07 Fujitsu Limited Method and apparatus for cutting patterns of printed wiring boards and method and apparatus for cleaning printed wiring boards
US5220754A (en) 1992-03-02 1993-06-22 Amad Tayebi Recovered compact disk and a method and an apparatus for recovery thereof
US5455459A (en) 1992-03-27 1995-10-03 Martin Marietta Corporation Reconstructable interconnect structure for electronic circuits
US5203143A (en) * 1992-03-28 1993-04-20 Tempo G Multiple and split pressure sensitive adhesive stratums for carrier tape packaging system
US5427349A (en) 1992-04-13 1995-06-27 Reo Hydraulic Pierce & Form, Inc. Adjustable base assembly
US5545367A (en) 1992-04-15 1996-08-13 Soane Technologies, Inc. Rapid prototype three dimensional stereolithography
US5226361A (en) 1992-05-19 1993-07-13 Micron Technology, Inc. Integrated circuit marking and inspecting system
FR2691670B1 (en) 1992-05-26 1994-08-26 Plastic Omnium Cie Polytetrafluoroethylene tape suitable for laser marking.
JP3102822B2 (en) 1992-05-29 2000-10-23 日本ジーイープラスチックス株式会社 Laser marking resin composition
US5322173A (en) 1992-06-09 1994-06-21 Kay Leslie A Ventilated wooden closet shelf and its method of construction
US5463227A (en) 1992-06-24 1995-10-31 Robotic Vision Systems, Inc. Method for obtaining three-dimensional data from multiple parts or devices in a multi-pocketed tray
US5793051A (en) 1995-06-07 1998-08-11 Robotic Vision Systems, Inc. Method for obtaining three-dimensional data from semiconductor devices in a row/column array and control of manufacturing of same with data to eliminate manufacturing errors
US5600150A (en) 1992-06-24 1997-02-04 Robotic Vision Systems, Inc. Method for obtaining three-dimensional data from semiconductor devices in a row/column array and control of manufacturing of same with data to eliminate manufacturing errors
US5362667A (en) * 1992-07-28 1994-11-08 Harris Corporation Bonded wafer processing
JP2707189B2 (en) 1992-08-26 1998-01-28 株式会社日立製作所 Removal method and apparatus of the board of the electronic component
JP2658809B2 (en) * 1992-08-27 1997-09-30 三菱電機株式会社 The laser processing apparatus
JP2714520B2 (en) * 1992-08-28 1998-02-16 株式会社日立製作所 Mounted components removable devices
CA2104340A1 (en) * 1992-08-31 1994-03-01 Grish Chandra Hermetic protection for integrated circuits
US5268059A (en) 1992-09-02 1993-12-07 Vlsi Technology, Inc. Detaping machine for removal of integrated circuit devices from sealed pocket tape
EP0660967B1 (en) 1992-09-14 2001-04-11 Shellcase Ltd. Method for producing integrated circuit devices
US5336928A (en) 1992-09-18 1994-08-09 General Electric Company Hermetically sealed packaged electronic system
US5445923A (en) 1992-09-30 1995-08-29 Somar Corporation Laser beam absorbing resin composition and laser beam marking method
JPH07110455B2 (en) 1992-10-27 1995-11-29 住友電気工業株式会社 Wafer fixing device
JP3261770B2 (en) * 1992-11-19 2002-03-04 松下電器産業株式会社 Component mounting apparatus
JP2588281Y2 (en) 1992-11-25 1999-01-06 株式会社小松製作所 Laser marking device
US5263567A (en) 1992-11-25 1993-11-23 Robotic Vision Systems, Inc. Horizontal vibrator method for orienting articles
US5605641A (en) * 1992-11-25 1997-02-25 Komatsu Ltd. Method and apparatus for laser marking a continuously moving workpiece
JP2751089B2 (en) 1992-11-30 1998-05-18 大日本インキ化学工業株式会社 Laser marking method and printing ink
US5301143A (en) * 1992-12-31 1994-04-05 Micron Semiconductor, Inc. Method for identifying a semiconductor die using an IC with programmable links
JPH0810729B2 (en) 1993-01-20 1996-01-31 日本電気株式会社 Stamping machine
WO1994016858A1 (en) 1993-01-29 1994-08-04 Kabushiki Kaisha Komatsu Seisakusho Laser marking system and method
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JP3309478B2 (en) 1993-02-26 2002-07-29 ソニー株式会社 Chip management system and chip manufacturing method according to the input processing method and lot processing method and chip management system
US5557148A (en) 1993-03-30 1996-09-17 Tribotech Hermetically sealed semiconductor device
US5458158A (en) 1993-03-30 1995-10-17 Toyo Communication Equipment Co., Ltd. Lead cutting apparatus and an anticorrosive coat structure of lead
US5329090A (en) 1993-04-09 1994-07-12 A B Lasers, Inc. Writing on silicon wafers
US5479694A (en) 1993-04-13 1996-01-02 Micron Technology, Inc. Method for mounting integrated circuits onto printed circuit boards and testing
US5360747A (en) 1993-06-10 1994-11-01 Xilinx, Inc. Method of reducing dice testing with on-chip identification
US5481202A (en) * 1993-06-17 1996-01-02 Vlsi Technology, Inc. Optical scan and alignment of devices under test
US5365653A (en) 1993-08-03 1994-11-22 John Padrun Tool for inserting/removing integrated circuit chips
US5632083A (en) 1993-08-05 1997-05-27 Hitachi Construction Machinery Co., Ltd. Lead frame fabricating method and lead frame fabricating apparatus
JP2575406Y2 (en) 1993-08-24 1998-06-25 住友電装株式会社 Connector inspection apparatus
US5793115A (en) 1993-09-30 1998-08-11 Kopin Corporation Three dimensional processor using transferred thin film circuits
US5566414A (en) 1993-10-20 1996-10-22 Matsuo Engineering Co., Ltd. Bridge raising/supporting method and bearing device for the method
DK0674680T3 (en) 1993-10-21 1997-09-01 Isovolta Oesterreichische Isolie Halogen-free resin mixture, a self-extinguishing prepreg filled with this resin mixture, and the use thereof
US5801067A (en) 1993-10-27 1998-09-01 Ronald Shaw Method for recording and identifying integrated circuit chips and the like
DE4338656C2 (en) 1993-11-12 1995-11-16 Multiline International Europa Device for aligning circuit boards and disks
DE4338774A1 (en) 1993-11-12 1995-05-18 Baasel Carl Lasertech An apparatus for labeling of workpieces
US5423716A (en) 1994-01-05 1995-06-13 Strasbaugh; Alan Wafer-handling apparatus having a resilient membrane which holds wafer when a vacuum is applied
US5928842A (en) 1994-02-24 1999-07-27 Nippon Kayaku Kabushiki Kaisha Marking method
JP2644184B2 (en) * 1994-06-06 1997-08-25 ソマール株式会社 Film peeling method and device
US5588797A (en) 1994-07-18 1996-12-31 Advantek, Inc. IC tray handling apparatus and method
US5654204A (en) 1994-07-20 1997-08-05 Anderson; James C. Die sorter
US5454900A (en) 1994-08-10 1995-10-03 Telford Industries Pte Ltd. Detaping apparatus
US5551959A (en) 1994-08-24 1996-09-03 Minnesota Mining And Manufacturing Company Abrasive article having a diamond-like coating layer and method for making same
US5632915A (en) 1994-08-29 1997-05-27 Gerber Garment Technology, Inc. Laser material processing apparatus and a work table therefor
US5465470A (en) 1994-08-31 1995-11-14 Lsi Logic Corporation Fixture for attaching multiple lids to multi-chip module (MCM) integrated circuit
DE19581661C2 (en) 1994-09-22 1998-11-26 Advantest Corp Ic cradles bearing structure and assembly device for this
US5484314A (en) * 1994-10-13 1996-01-16 Micron Semiconductor, Inc. Micro-pillar fabrication utilizing a stereolithographic printing process
US5487471A (en) * 1994-10-19 1996-01-30 Molex Incorporated Packaging container assembly for electrical connector components
US5715592A (en) * 1994-11-08 1998-02-10 Nec Corporation Parts disassembling apparatus
DE69536108D1 (en) 1994-11-17 2010-10-28 Panasonic Corp Optical disc and method of reproducing data from an optical disk
JP2682475B2 (en) * 1994-11-17 1997-11-26 日本電気株式会社 Beam scanning type laser marking method and apparatus
US5976955A (en) 1995-01-04 1999-11-02 Micron Technology, Inc. Packaging for bare dice employing EMR-sensitive adhesives
US5590787A (en) * 1995-01-04 1997-01-07 Micron Technology, Inc. UV light sensitive die-pac for securing semiconductor dies during transport
JPH08243765A (en) 1995-03-07 1996-09-24 Komatsu Ltd Laser marking device
JPH08253455A (en) * 1995-03-17 1996-10-01 Agro Kanesho Co Ltd Hexahydropyridazine derivative and herbicide comprising the same as active ingredient
US5692873A (en) 1995-03-31 1997-12-02 Motorola, Inc. Apparatus for holding a piece of semiconductor
JP2709283B2 (en) * 1995-04-07 1998-02-04 山一電機株式会社 Ic career
US5665609A (en) 1995-04-21 1997-09-09 Sony Corporation Prioritizing efforts to improve semiconductor production yield
US5629484A (en) 1995-05-19 1997-05-13 Micron Technology, Inc. Method and apparatus for monitoring a laser ablation operation involving multiple ablation sites on a workpiece
US5600181A (en) * 1995-05-24 1997-02-04 Lockheed Martin Corporation Hermetically sealed high density multi-chip package
JPH08324981A (en) * 1995-05-26 1996-12-10 Matsuo Eng Kk Multistep type wedge-shaped jack
US5643477A (en) 1995-06-30 1997-07-01 Motoman Inc. Laser enclosure
US5648136A (en) 1995-07-11 1997-07-15 Minnesota Mining And Manufacturing Co. Component carrier tape
US6028134A (en) * 1995-07-12 2000-02-22 Teijin Limited Thermoplastic resin composition having laser marking ability
JP2763754B2 (en) 1995-07-27 1998-06-11 株式会社ケンウッド The recording medium reproducing apparatus
US5638958A (en) 1995-09-08 1997-06-17 Micron Technology, Inc. Semiconductor film wafer cassette
KR0175267B1 (en) 1995-09-30 1999-04-01 김광호 Die bonding apparatus equipped with a pick-up tool to a rotary motion
DE19537409A1 (en) * 1995-10-09 1997-04-10 Leybold Ag Device for producing exposed and metallized substrates
JPH09148280A (en) 1995-11-08 1997-06-06 Samsung Electron Co Ltd Manufacturing method of semiconductor element with polishing of back side of wafer, using uv-sensitive tape
US6137125A (en) 1995-12-21 2000-10-24 The Whitaker Corporation Two layer hermetic-like coating for on-wafer encapsulatuon of GaAs MMIC's having flip-chip bonding capabilities
US5932119A (en) 1996-01-05 1999-08-03 Lazare Kaplan International, Inc. Laser marking system
JP3376198B2 (en) 1996-01-09 2003-02-10 日東電工株式会社 The protective member of the semiconductor wafer
US5838361A (en) 1996-01-11 1998-11-17 Micron Technology, Inc. Laser marking techniques
US5838431A (en) 1996-01-16 1998-11-17 Asahi Kogaku Kogyo Kabushiki Kaisha Laser marking device
US5937270A (en) 1996-01-24 1999-08-10 Micron Electronics, Inc. Method of efficiently laser marking singulated semiconductor devices
JP3226780B2 (en) 1996-02-27 2001-11-05 東芝マイクロエレクトロニクス株式会社 Test handler of the semiconductor device
US5682065A (en) 1996-03-12 1997-10-28 Micron Technology, Inc. Hermetic chip and method of manufacture
EP0798765A3 (en) * 1996-03-28 1998-08-05 Shin-Etsu Handotai Company Limited Method of manufacturing a semiconductor wafer comprising a dopant evaporation preventive film on one main surface and an epitaxial layer on the other main surface
US5855969A (en) * 1996-06-10 1999-01-05 Infosight Corp. CO2 laser marking of coated surfaces for product identification
US5808268A (en) 1996-07-23 1998-09-15 International Business Machines Corporation Method for marking substrates
DE19630932A1 (en) 1996-07-31 1998-02-05 Wacker Siltronic Halbleitermat Carrier for a semiconductor wafer and using the carrier
US5731954A (en) * 1996-08-22 1998-03-24 Cheon; Kioan Cooling system for computer
US5829115A (en) 1996-09-09 1998-11-03 General Electro Mechanical Corp Apparatus and method for actuating tooling
JP3844824B2 (en) 1996-11-26 2006-11-15 株式会社Adeka Energy beam curable epoxy resin composition, for stereolithography resin composition and optical stereolithography methods
JPH10173003A (en) * 1996-12-13 1998-06-26 Sharp Corp Semiconductor device and its manufacturing method, and film carrier tape and its manufacturing method
US5927512A (en) 1997-01-17 1999-07-27 Micron Technology, Inc. Method for sorting integrated circuit devices
JP4020337B2 (en) * 1997-02-07 2007-12-12 株式会社ルネサステクノロジ A method of manufacturing a semiconductor device
US5844803A (en) 1997-02-17 1998-12-01 Micron Technology, Inc. Method of sorting a group of integrated circuit devices for those devices requiring special testing
US5915231A (en) 1997-02-26 1999-06-22 Micron Technology, Inc. Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture
US5866644A (en) * 1997-03-17 1999-02-02 General Electric Company Composition for laser marking
US5856923A (en) * 1997-03-24 1999-01-05 Micron Technology, Inc. Method for continuous, non lot-based integrated circuit manufacturing
KR100214562B1 (en) * 1997-03-24 1999-08-02 구본준 Stacked semiconductor chip package and making method thereof
KR100205497B1 (en) 1997-04-08 1999-07-01 윤종용 Support table for supporting board for for applying module and screen print method using the same
US5907492A (en) 1997-06-06 1999-05-25 Micron Technology, Inc. Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs
US5966307A (en) 1997-06-10 1999-10-12 Behavior Tech Computer Corporation Laser marker control system
EP0895850A1 (en) * 1997-08-03 1999-02-10 Micromod R.P. Ltd. Rapid prototyping
US6008476A (en) 1997-08-04 1999-12-28 Motorola, Inc. Apparatus for indexing and affixing components to a substrate
JP3993918B2 (en) * 1997-08-25 2007-10-17 富士通株式会社 A method of manufacturing a semiconductor device
US6244634B1 (en) 1997-09-04 2001-06-12 Micron Electronics, Inc. Apparatus for actuating the retaining locks of a cassette
US5875544A (en) * 1997-09-18 1999-03-02 Chou; Shu Chun Yu Multifunctional IC hand tool
US6062119A (en) 1998-01-29 2000-05-16 Micron Electronics, Inc. Method for handling and manipulating microelectronic components
US6138542A (en) 1998-01-29 2000-10-31 Micron Electronics, Inc. Apparatus for handling and manipulating microelectronic components
US5972234A (en) 1998-04-06 1999-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Debris-free wafer marking method
US6229323B1 (en) 1998-04-23 2001-05-08 Micron Technology, Inc. Automated multi-chip module handler, method of module handling, and module magazine
US6008070A (en) 1998-05-21 1999-12-28 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
US5999252A (en) 1998-07-22 1999-12-07 Seh America, Inc. Method for marking workpieces
US6100486A (en) 1998-08-13 2000-08-08 Micron Technology, Inc. Method for sorting integrated circuit devices
US6202292B1 (en) * 1998-08-26 2001-03-20 Micron Technology, Inc. Apparatus for removing carrier film from a semiconductor die
JP3661444B2 (en) * 1998-10-28 2005-06-15 株式会社ルネサステクノロジ Semiconductor device, a semiconductor wafer, a method of manufacturing a semiconductor module and semiconductor device
US6287068B1 (en) 1998-12-21 2001-09-11 Micron Technology, Inc. Self-aligning tray carrier apparatus with tilt feature
US6244569B1 (en) 1998-12-21 2001-06-12 Micron Electronics, Inc. Controlled motion lift mechanism
US6380558B1 (en) * 1998-12-29 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6524861B1 (en) * 1999-01-22 2003-02-25 Medical Laboratory Automation, Inc. Blood coagulation analyzer
JP4959080B2 (en) * 1999-06-07 2012-06-20 エクストリーム、ウルトラバイオレット、リミテッド、ライアビリティ、カンパニーExtreme Ultraviolet Limited Liability Company Coating of reflective mask substrate
US6277725B1 (en) * 1999-07-07 2001-08-21 United Microelectronics Corp. Method for fabricating passivation layer on metal pad
US7108192B2 (en) * 1999-09-17 2006-09-19 Silverbrook Research Pty Ltd Rotationally symmetric tags
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6337122B1 (en) * 2000-01-11 2002-01-08 Micron Technology, Inc. Stereolithographically marked semiconductors devices and methods
EP1138804A3 (en) 2000-03-27 2003-06-25 Infineon Technologies AG Component with at least two contiguous insulating layers and manufacturing method therefor
US6524881B1 (en) * 2000-08-25 2003-02-25 Micron Technology, Inc. Method and apparatus for marking a bare semiconductor die
US7139083B2 (en) * 2000-09-20 2006-11-21 Kla-Tencor Technologies Corp. Methods and systems for determining a composition and a thickness of a specimen
US6737201B2 (en) 2000-11-22 2004-05-18 Hoya Corporation Substrate with multilayer film, reflection type mask blank for exposure, reflection type mask for exposure and production method thereof as well as production method of semiconductor device
GB0028822D0 (en) * 2000-11-25 2001-01-10 Mitel Corp Method of making a functional device with deposited layers subject to hih temperature anneal
US6742873B1 (en) * 2001-04-16 2004-06-01 Silverbrook Research Pty Ltd Inkjet printhead construction
US20030017626A1 (en) * 2001-07-23 2003-01-23 Motorola Inc. Method and apparatus for controlling propagation of dislocations in semiconductor structures and devices
US6749893B2 (en) * 2002-01-31 2004-06-15 Dalsa Semiconductor Inc. Method of preventing cracking in optical quality silica layers
JP4860113B2 (en) * 2003-12-26 2012-01-25 ルネサスエレクトロニクス株式会社 The method of manufacturing a semiconductor integrated circuit device

Patent Citations (121)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444490B1 (en) *
US2357600A (en) 1942-08-24 1944-09-05 Walter W Pabst Conveyer
US2413767A (en) 1944-10-17 1947-01-07 Crucible Steel Company Conveyer mechanism
US2495541A (en) 1946-11-20 1950-01-24 Central Foundry Company Metal pouring apparatus for centrifugal castings
US2454548A (en) 1947-07-05 1948-11-23 Edward J Brinkert Lifting device
US3239218A (en) 1963-11-13 1966-03-08 Hudson D Reeves Wedge-type stack leveling platform for sheet material
US3254776A (en) 1964-04-10 1966-06-07 Socony Mobil Oil Co Inc Pipe handling and storage apparatus
US3327889A (en) 1965-03-08 1967-06-27 Pentwater Wire Products Inc Folding container
US3625384A (en) 1968-09-26 1971-12-07 Ibm Article-handling apparatus
US3628672A (en) 1970-01-05 1971-12-21 Streator Dependable Mfg Co Captive pallet for load-stacking racks
US3861969A (en) * 1970-03-31 1975-01-21 Hitachi Ltd Method for making III{14 V compound semiconductor devices
US3774352A (en) 1970-05-30 1973-11-27 Waldrich Werkzeugmasch Aligning device for workpieces on machine tool tables
US3837510A (en) 1971-01-21 1974-09-24 Williams J Mc Method of loading bagged mail from a loading dock into a highway vehicle
US3751587A (en) 1972-01-20 1973-08-07 Saxon Ind Inc Laser printing system
US3799017A (en) 1972-09-14 1974-03-26 D Halligan Component lead cutter
US4058217A (en) 1973-05-01 1977-11-15 Unisearch Limited Automatic article sorting system
US3887997A (en) 1973-11-09 1975-06-10 Gen Motors Corp Magnetic alignment for semiconductor device bonding
US3937386A (en) 1973-11-09 1976-02-10 General Motors Corporation Flip chip cartridge loader
US3917983A (en) 1973-11-12 1975-11-04 Bunker Ramo Multiwafer electrical circuit construction and method of making
US4024545A (en) 1974-04-22 1977-05-17 Mb Associates Laser-excited marking system
US3903934A (en) 1974-12-31 1975-09-09 Mann Henry Inc Collapsible forming die
US3973665A (en) 1975-03-07 1976-08-10 Gca Corporation Article delivery and transport apparatus for evacuated processing equipment
US4030622A (en) 1975-05-23 1977-06-21 Pass-Port Systems, Inc. Wafer transport system
US3969813A (en) 1975-08-15 1976-07-20 Bell Telephone Laboratories, Incorporated Method and apparatus for removal of semiconductor chips from hybrid circuits
US4027246A (en) 1976-03-26 1977-05-31 International Business Machines Corporation Automated integrated circuit manufacturing system
US4095095A (en) 1976-03-31 1978-06-13 Tokyo Shibaura Electric Co., Ltd. Apparatus for manufacturing semiconductor devices
US4203486A (en) 1977-01-11 1980-05-20 Anchor Hocking Corporation Food preparation apparatus and process
US4123044A (en) 1977-05-07 1978-10-31 Ludwig Riedhammer Gmbh & Co. K.G. Tunnel furnace
US4097715A (en) 1977-05-16 1978-06-27 General Refractories Company Laser jet bell kiln
US4178531A (en) 1977-06-15 1979-12-11 Rca Corporation CRT with field-emission cathode
US4353796A (en) 1977-07-22 1982-10-12 Mitsubishi Mining & Cement Co., Ltd. Apparatus for digging and transporting soil and sand, stones and rocks, minerals and the like
US4148057A (en) 1977-10-25 1979-04-03 Solution Sciences, Inc. Direct laser printing and forming apparatus
US4382580A (en) 1979-04-11 1983-05-10 Handelsbolaget Rodoverken Lifting and shifting apparatus
US4352617A (en) 1979-04-12 1982-10-05 Murata Kikai Kabushiki Kaisha Bucket stacking and conveying apparatus
US4323755A (en) 1979-09-24 1982-04-06 Rca Corporation Method of making a machine-readable marking in a workpiece
US4285433A (en) 1979-12-19 1981-08-25 Western Electric Co., Inc. Method and apparatus for removing dice from a severed wafer
US4354770A (en) 1980-05-19 1982-10-19 The United States Of America As Represented By The Secretary Of The Navy Wedge assembly
US4370542A (en) 1980-05-22 1983-01-25 Westland Aircraft Limited Cable marking method and apparatus
US4346284A (en) 1980-06-18 1982-08-24 Philip Morris Incorporated Dual path web transport and processing apparatus with radiant energy directing means
US4375025A (en) 1980-06-19 1983-02-22 Automated Industrial Systems, Inc. Laser strip marker
US4403134A (en) 1981-03-17 1983-09-06 Trumpf Gmbh & Co. Method and apparatus for cutting by means of a laser beam
US4454413A (en) 1982-02-19 1984-06-12 Precision Monolithics, Inc. Apparatus for tracking integrated circuit devices
US4517436A (en) 1982-09-20 1985-05-14 Automated Industrial Systems Laser marker for articles of manufacture
US4461073A (en) 1982-10-27 1984-07-24 At&T Technologies, Inc. Device for inserting and extracting circuit modules with dual-in-line leads
US4610359A (en) 1983-02-23 1986-09-09 Licentia Patent-Verwaltungs-Gmbh Method for recognizing and sorting articles
US4702788A (en) 1983-02-28 1987-10-27 Uzo Tomii Method of receiving small-sized electronic parts
US4513539A (en) 1983-03-15 1985-04-30 Acrometal Products, Inc. Position setting device for abrasive belt grinding machine
US4493767A (en) 1983-04-28 1985-01-15 Guido Monteyne Conveyor belt for transporting slag material from a filtering apparatus
US4523319A (en) 1983-05-10 1985-06-11 Brown University Laser tape systems
US4534695A (en) 1983-05-23 1985-08-13 Eaton Corporation Wafer transport system
US4778326A (en) 1983-05-24 1988-10-18 Vichem Corporation Method and means for handling semiconductor and similar electronic devices
US4510673A (en) 1983-06-23 1985-04-16 International Business Machines Corporation Laser written chip identification method
US4543716A (en) 1983-09-23 1985-10-01 The Wiremold Company Method and apparatus for electrical connection of flat cables
US4561541A (en) 1983-09-26 1985-12-31 Spectrolab, Incorporated Carrier system for photovoltaic cells
US4539878A (en) 1983-10-31 1985-09-10 American Tech. Manufacturing, Inc. Method and apparatus for trimming the leads of electronic components
US4585931A (en) 1983-11-21 1986-04-29 At&T Technologies, Inc. Method for automatically identifying semiconductor wafers
US4759675A (en) 1984-03-22 1988-07-26 Sgs-Thomson Microelectronics, Inc. Chip selection in automatic assembly of integrated circuit
US4552271A (en) 1984-03-27 1985-11-12 Kranz Kermit W Collapsible container construction
USD288273S (en) 1984-04-02 1987-02-17 Food support
US4577563A (en) 1984-07-11 1986-03-25 Sidler Karl J Safekeeping box assembly
US4626656A (en) 1984-07-19 1986-12-02 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for indicating the contact structure of electromagnetic contactor on the housing thereof using laser light
US4665298A (en) 1984-08-20 1987-05-12 Fiat Auto S.P.A. Apparatus for effecting treatment of metal workpieces by means of a power laser
US4607744A (en) 1984-09-10 1986-08-26 Pak Chong Il Method and apparatus for removing integrated circuit chips from a flexible carrier
US4644126A (en) 1984-12-14 1987-02-17 Ford Motor Company Method for producing parallel-sided melt zone with high energy beam
US4707722A (en) 1984-12-17 1987-11-17 Motorola, Inc. Laser marking method and ablative coating for use therein
US4594263A (en) 1984-12-17 1986-06-10 Motorola, Inc. Laser marking method and ablative coating for use therein
US4654290A (en) 1985-02-01 1987-03-31 Motorola, Inc. Laser markable molding compound, method of use and device therefrom
US4753863A (en) 1985-02-01 1988-06-28 Motorola Inc. Laser markable molding compound
US4720317A (en) 1985-02-14 1988-01-19 Bando Chemical Industries, Ltd. Method for dicing a semiconductor wafer
US4630513A (en) 1985-02-14 1986-12-23 Ernst Keller Automatic dip trimmer apparatus
US4616414A (en) 1985-03-13 1986-10-14 At&T Technologies, Inc. Method and apparatus for gripping multilead articles
US4638144A (en) 1985-04-24 1987-01-20 Automated Industrial Systems Indexing laser marker
US4719502A (en) 1985-08-07 1988-01-12 Kabushiki Kaisha Toshiba Epoxy resin composition, and resin-sealed semiconductor device in which this composition is used
US4767984A (en) 1985-10-04 1988-08-30 Amp Incorporated Protective fixture for chip carrier
US4677370A (en) 1985-10-31 1987-06-30 Unisys Corporation Method of testing wire bonds for defects using a magnetic field
US4660282A (en) 1985-12-16 1987-04-28 Pfaff Wayne Method and apparatus for unloading electronic circuit packages from zero insertion force sockets
US4821151A (en) 1985-12-20 1989-04-11 Olin Corporation Hermetically sealed package
US4696096A (en) 1986-02-21 1987-09-29 Micro Electronic Systems, Inc. Reworking methods and apparatus for surface mounted technology circuit boards
US4884420A (en) 1986-02-24 1989-12-05 Dennis E. McGoldrick, Trustee Cage with floating nut assembly
US4718531A (en) 1986-02-24 1988-01-12 Amp Incorporated Electrical connector pick-up station
US4891242A (en) 1986-07-05 1990-01-02 Kabushiki Kaisha Toyoda Jidoshokki Seisakusho Substrate of a hybrid ic, method of forming a circuit pattern and apparatus of forming the same
US4711334A (en) 1986-08-28 1987-12-08 Barry Joseph A Telescopic chute for mixer discharge
US4772079A (en) 1986-09-26 1988-09-20 General Electric Co. Cover assembly for removably mounted electronic equipment
US4832612A (en) 1986-10-31 1989-05-23 Amp Incorporated Protective carrier and securing means therefor
US4861620A (en) 1986-11-14 1989-08-29 Mitsubishi Denki Kabushiki Kaisha Method of laser marking
US4756977A (en) 1986-12-03 1988-07-12 Dow Corning Corporation Multilayer ceramics from hydrogen silsesquioxane
US4749631A (en) 1986-12-04 1988-06-07 Dow Corning Corporation Multilayer ceramics from silicate esters
US4749631B1 (en) 1986-12-04 1993-03-23 Multilayer ceramics from silicate esters
US4791267A (en) 1987-01-28 1988-12-13 Mitsubishi Denki Kabushiki Kaisha Method of forming identifying indicium on cathode ray tubes
US4916293A (en) 1987-02-25 1990-04-10 Rolls-Royce Plc Identification in manufacture
US4818835A (en) 1987-03-02 1989-04-04 Hitachi, Ltd. Laser marker and method of laser marking
US4769345A (en) 1987-03-12 1988-09-06 Olin Corporation Process for producing a hermetically sealed package for an electrical component containing a low amount of oxygen and water vapor
US4790515A (en) 1987-07-27 1988-12-13 Silvano Pocci Force multiplier useful as a lifting device
US4990051A (en) 1987-09-28 1991-02-05 Kulicke And Soffa Industries, Inc. Pre-peel die ejector apparatus
US4850780A (en) 1987-09-28 1989-07-25 Kulicke And Soffa Industries Inc. Pre-peel die ejector apparatus
US4926677A (en) 1987-12-03 1990-05-22 Kurt Waldner Die apparatus
US4967260A (en) 1988-05-04 1990-10-30 International Electronic Research Corp. Hermetic microminiature packages
US4944492A (en) 1988-06-24 1990-07-31 Matsuo Engineering Co., Ltd. Wedge-type jack apparatus for raising structure while sustaining very large pressure due to same and temporarily supporting the structure
US4945204A (en) 1988-11-10 1990-07-31 Mitsubishi Denki Kabushiki Kaisha Method of laser-marking semiconductor devices
US4947981A (en) 1989-04-13 1990-08-14 Dorner Mfg. Corp. Apparatus for inverting articles
US4914269A (en) 1989-07-24 1990-04-03 Micron Technology, Inc. Method of sealing a ceramic lid on a ceramic semiconductor package with a high-power laser
US4965927A (en) 1989-09-21 1990-10-30 Eli Holzman Apparatus for applying surface-mounted electronic components to printed circuit boards
US5663096A (en) * 1990-02-14 1997-09-02 Nippondenso Co., Ltd. Method of manufacturing a vertical semiconductor device with ground surface providing a reduced ON resistance
US5183783A (en) * 1990-12-28 1993-02-02 Shin-Etsu Handotai Co., Ltd Method for production of dielectric-separation substrate
US5780311A (en) * 1992-06-17 1998-07-14 Harris Corporation bonded wafer processing
US5801084A (en) * 1992-06-17 1998-09-01 Harris Corporation Bonded wafer processing
US5701084A (en) * 1995-09-22 1997-12-23 Magnetrol International, Inc. Insulated capacitance probe
US5827771A (en) * 1996-03-19 1998-10-27 Raytheon Company Readout backside processing for hybridization
US5893760A (en) * 1996-03-27 1999-04-13 Kabushiki Kaisha Toshiba Method of heat treating a semiconductor wafer to reduce stress
US5856230A (en) * 1996-12-31 1999-01-05 Hyundai Electronics Industries Co., Ltd. Method for making field oxide of semiconductor device
US5827711A (en) * 1997-03-20 1998-10-27 Incyte Pharmaceuticals, Inc. Succinate-ubiquinone reductase subunit
US6444490B2 (en) * 1998-06-26 2002-09-03 International Business Machines Corporation Micro-flex technology in semiconductor packages
US6303471B1 (en) * 1998-10-14 2001-10-16 Nippon Telegraph And Telephone Corporation Method of manufacturing semiconductor device having reinforcing member and method of manufacturing IC card using the device
US20030017652A1 (en) * 1999-02-15 2003-01-23 Masako Sakaki Semiconductor device, its fabrication method and electronic device
US6323060B1 (en) * 1999-05-05 2001-11-27 Dense-Pac Microsystems, Inc. Stackable flex circuit IC package and method of making same
US6579748B1 (en) * 1999-05-18 2003-06-17 Sanyu Rec Co., Ltd. Fabrication method of an electronic component
US6489178B2 (en) * 2000-01-26 2002-12-03 Texas Instruments Incorporated Method of fabricating a molded package for micromechanical devices
US6603191B2 (en) * 2000-05-18 2003-08-05 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US20020048906A1 (en) * 2000-10-20 2002-04-25 Tadahiko Sakai Semiconductor device, method of manufacturing the device and mehtod of mounting the device
US6656820B2 (en) * 2000-11-08 2003-12-02 Sharp Kabushiki Kaisha Method for manufacturing a semiconductor device having a reliable thinning step
US20030011765A1 (en) * 2001-07-03 2003-01-16 Xie Xiaoliang Sunney System and method for polarization coherent anti-stokes raman scattering microscopy

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070007664A1 (en) * 2005-07-06 2007-01-11 Chung-Sun Lee Semiconductor package with molded back side and method of fabricating the same
US20070093038A1 (en) * 2005-10-26 2007-04-26 Andreas Koenig Method for making microchips and microchip made according to this method
US20070212812A1 (en) * 2006-03-07 2007-09-13 Stats Chippac Ltd. Wafer level chip scale package system with a thermal dissipation structure
US7939368B2 (en) * 2006-03-07 2011-05-10 Stats Chippac Ltd. Wafer level chip scale package system with a thermal dissipation structure
US7378293B2 (en) * 2006-03-22 2008-05-27 Texas Instruments Incorporated MEMS fabrication method
US20070224718A1 (en) * 2006-03-22 2007-09-27 Texas Instruments Incorporated MEMS fabrication method
US20080029859A1 (en) * 2006-08-04 2008-02-07 Stats Chippac Ltd. Integrated circuit package system employing wafer level chip scale packaging
US20100148355A1 (en) * 2006-08-04 2010-06-17 Byung Tai Do Integrated circuit package system employing wafer level chip scale packaging
US9048197B2 (en) 2006-08-04 2015-06-02 Stats Chippac Ltd. Integrated circuit package system employing wafer level chip scale packaging
US7700458B2 (en) * 2006-08-04 2010-04-20 Stats Chippac Ltd. Integrated circuit package system employing wafer level chip scale packaging
US20080237811A1 (en) * 2007-03-30 2008-10-02 Rohit Pal Method for preserving processing history on a wafer
US20090280584A1 (en) * 2008-02-04 2009-11-12 Micron Technology, Inc. Wafer processing
US7622365B2 (en) 2008-02-04 2009-11-24 Micron Technology, Inc. Wafer processing including dicing
US7897485B2 (en) 2008-02-04 2011-03-01 Micron Technology, Inc. Wafer processing including forming trench rows and columns at least one of which has a different width
US20090197394A1 (en) * 2008-02-04 2009-08-06 Micron Technology, Inc. Wafer processing
US20100075482A1 (en) * 2008-09-25 2010-03-25 Daryl Ross Koehl Bonded Wafer Assembly System and Method
US7943489B2 (en) 2008-09-25 2011-05-17 Texas Instruments Incorporated Bonded wafer assembly system and method
US8257985B2 (en) 2008-09-25 2012-09-04 Texas Instruments Incorporated MEMS device and fabrication method
US8530984B2 (en) 2008-09-25 2013-09-10 Texas Instruments Incorporated Semiconductor device structures and their fabrication
US8455991B2 (en) 2010-09-24 2013-06-04 Stats Chippac Ltd. Integrated circuit packaging system with warpage control and method of manufacture thereof
US8963337B2 (en) * 2010-09-29 2015-02-24 Varian Semiconductor Equipment Associates Thin wafer support assembly
US20120074591A1 (en) * 2010-09-29 2012-03-29 Varian Semiconductor Equipment Associates, Inc. Thin wafer support assembly
US8927334B2 (en) 2012-09-25 2015-01-06 International Business Machines Corporation Overcoming chip warping to enhance wetting of solder bumps and flip chip attaches in a flip chip package
US9502271B2 (en) * 2012-11-15 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control for flexible substrates
US20140302642A1 (en) * 2012-11-15 2014-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage Control for Flexible Substrates
US20150044783A1 (en) * 2013-08-12 2015-02-12 Micron Technology, Inc. Methods of alleviating adverse stress effects on a wafer, and methods of forming a semiconductor device
WO2015084848A2 (en) 2013-12-03 2015-06-11 Invensas Corporation Warpage reduction in structures with electrical circuitry
US9397051B2 (en) 2013-12-03 2016-07-19 Invensas Corporation Warpage reduction in structures with electrical circuitry
US9853000B2 (en) 2013-12-03 2017-12-26 Invensas Corporation Warpage reduction in structures with electrical circuitry
CN104157577B (en) * 2014-08-26 2016-11-02 上海华虹宏力半导体制造有限公司 The method of forming a semiconductor device
US9543255B2 (en) 2014-12-02 2017-01-10 International Business Machines Corporation Reduced-warpage laminate structure
US9613915B2 (en) 2014-12-02 2017-04-04 International Business Machines Corporation Reduced-warpage laminate structure

Also Published As

Publication number Publication date Type
US20060051938A1 (en) 2006-03-09 application
US20040104491A1 (en) 2004-06-03 application
US7727785B2 (en) 2010-06-01 grant
US20030162368A1 (en) 2003-08-28 application

Similar Documents

Publication Publication Date Title
US6444499B1 (en) Method for fabricating a snapable multi-package array substrate, snapable multi-package array and snapable packaged electronic components
US6624505B2 (en) Packaged integrated circuits and methods of producing thereof
US6319354B1 (en) System and method for dicing semiconductor components
US5286679A (en) Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer
US6271469B1 (en) Direct build-up layer on an encapsulated die package
US6534849B1 (en) Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same
US6750082B2 (en) Method of assembling a package with an exposed die backside with and without a heatsink for flip-chip
US20030143819A1 (en) Method of producing semiconductor chips with a chip edge guard, in particular for wafer level packaging chips
US6852607B2 (en) Wafer level package having a side package
US20010016400A1 (en) Method of making wafer level chip scale package
US6548376B2 (en) Methods of thinning microelectronic workpieces
US7211168B2 (en) Substrate supporting plate and stripping method for supporting plate
US6432796B1 (en) Method and apparatus for marking microelectronic dies and microelectronic devices
US20020192867A1 (en) Chip-like electronic components, a method of manufacturing the same, a pseudo wafer therefor and a method of manufacturing thereof
US20020096743A1 (en) Method and device for protecting micro electromechanical systems structures during dicing of a wafer
US6734032B2 (en) Method and apparatus for marking a bare semiconductor die
US6551906B2 (en) Method of fabricating semiconductor device
US20030190795A1 (en) Method of manufacturing a semiconductor device
EP1094511A2 (en) Low profile integrated circuit packages
US7135385B1 (en) Semiconductor devices having a back surface protective coating
US6767764B2 (en) Microelectromechanical system device packaging method
US7202107B2 (en) Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method
US6558975B2 (en) Process for producing semiconductor device
US5389579A (en) Method for single sided polishing of a semiconductor wafer
US20080157103A1 (en) Laminating Encapsulant Film Containing Phosphor Over LEDs

Legal Events

Date Code Title Description
AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CONNELL, MICHAEL E.;JIANG, TONGBI;REEL/FRAME:012711/0928

Effective date: 20020211

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426