JPH02208954A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02208954A JPH02208954A JP1028851A JP2885189A JPH02208954A JP H02208954 A JPH02208954 A JP H02208954A JP 1028851 A JP1028851 A JP 1028851A JP 2885189 A JP2885189 A JP 2885189A JP H02208954 A JPH02208954 A JP H02208954A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- wafers
- wafer
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 235000012431 wafers Nutrition 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000853 adhesive Substances 0.000 claims description 13
- 230000001070 adhesive effect Effects 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000007767 bonding agent Substances 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 150000001875 compounds Chemical class 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 239000010931 gold Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置の製造方法に係り、特に化合物半導体装置の
製造方法に関し。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a compound semiconductor device.
ウェハプロセス中にウェハの欠けや破損の発生するのを
防止して半導体素子チップを作成することを目的とし。The purpose is to create semiconductor element chips by preventing wafer chipping or damage during the wafer process.
異なるサイズを有する複数種類の半導体ウェハをその主
面より広い面を持つ固定サイズの基板上に接着材を用い
て接着し、その接着がはずれない温度で該半導体ウェハ
に処理を施して素子形成を完了させた後、該半導体ウェ
ハを該基板と一体化したまま或いは該基板からはずして
チップに切断分離する半導体装置の製造方法により構成
する。Multiple types of semiconductor wafers of different sizes are bonded using an adhesive onto a fixed-sized substrate with a surface wider than the main surface, and elements are formed by processing the semiconductor wafers at a temperature that does not allow the bond to come off. After completion of the process, the semiconductor device is manufactured by a method of manufacturing a semiconductor device in which the semiconductor wafer is cut into chips while being integrated with the substrate or separated from the substrate.
本発明は半導体装置の製造方法に係り、特に化合物半導
体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a compound semiconductor device.
InPやInAs等の化合物半導体は材質的に脆く。Compound semiconductors such as InP and InAs are brittle materials.
ウェハに素子を形成してそのウェハをチップに切断する
プロセスにおいて、ウェハに欠けや破損が発生しやすい
。そのため、プロセスの自動化がなかなか困難で1手作
業によるか、高度の専用自動化装置を必要とする。In the process of forming elements on a wafer and cutting the wafer into chips, the wafer is likely to be chipped or damaged. Therefore, it is difficult to automate the process, requiring either manual work or highly specialized automation equipment.
このため1手作業に頌らず、比較的容易にしかも安価に
自動化できる製造方法が要求される。For this reason, there is a need for a manufacturing method that can be automated relatively easily and inexpensively without relying on manual labor.
(従来の技術〕
従来、化合物半導体装置の製造においては、ウェハ状態
で素子形成を完了した後、チップに分割する時そのウェ
ハをそれより広い面を持つ基板に張りつけて切断分離を
行っていた。(Prior Art) Conventionally, in the manufacture of compound semiconductor devices, after completion of element formation in a wafer state, when dividing the wafer into chips, the wafer was attached to a substrate having a wider surface and cut and separated.
ところが、化合物半導体は材質的に脆いのでウェハ状態
でのプロセス(以下ウェハプロセスと呼ぶ)中に破損し
たり、特にウェハの縁の部分の欠けが発生することが多
く1問題となっていた。However, since compound semiconductors are brittle materials, they often break during processing in a wafer state (hereinafter referred to as wafer processing), and chipping occurs particularly at the edges of the wafer, which has been a problem.
従って、化合物半導体装置の製造においては。 Therefore, in manufacturing compound semiconductor devices.
欠けを防ぐため細心の注意を払って手作業を進めたり、
自動の場合は高度の専用自動化装置を必要とした。Hand work is done with great care to prevent chipping,
If automatic, highly specialized automation equipment was required.
本発明は、ウェハプロセス中のウェハの破損や欠けを防
止し、また1手作業が困難な小さなウェハや自動化が困
難な不定形のウェハにも適用できる半導体装置の製造方
法を提供することを目的とする。An object of the present invention is to provide a semiconductor device manufacturing method that prevents damage and chipping of wafers during wafer processing and can also be applied to small wafers that are difficult to handle manually and irregularly shaped wafers that are difficult to automate. shall be.
〔課題を解決するための手段〕
第1図は実施例を示す。第1図及び図中の符号を参照し
ながら、上記課題を解決するための手段について説明す
る。[Means for solving the problem] FIG. 1 shows an embodiment. Means for solving the above problem will be explained with reference to FIG. 1 and the reference numerals in the figure.
上記課題は、異なるサイズを有する複数種類の半導体ウ
ェハ1をその主面より広い面を持つ固定サイズの基板3
上に接着材41乃至43を用いて接着し、その接着がは
ずれない温度で該半導体ウェハ1に処理を施して素子形
成を完了させた後、該半導体ウェハ1を該基板3と一体
化したまま或いは該基板3からはずしてチップ81乃至
83に切断分離する半導体装置の製造方法によって解決
される。The above-mentioned problem is to convert a plurality of types of semiconductor wafers 1 having different sizes into a fixed size substrate 3 having a surface wider than the main surface of the semiconductor wafer 1.
After the semiconductor wafer 1 is bonded using adhesives 41 to 43 and processed at a temperature at which the bond does not come off to complete element formation, the semiconductor wafer 1 remains integrated with the substrate 3. Alternatively, the problem can be solved by a method of manufacturing a semiconductor device in which the semiconductor device is removed from the substrate 3 and cut into chips 81 to 83.
本発明では半導体ウェハを、その主面より広い面を持つ
基板上に接着材を用いて接着している。In the present invention, a semiconductor wafer is bonded to a substrate having a surface wider than its main surface using an adhesive.
この状態でウェハプロセスを進めればウェハプロセス中
の半導体ウェハの破損、特に縁の部分の欠けを防止する
ことができる。If the wafer process is carried out in this state, it is possible to prevent damage to the semiconductor wafer during the wafer process, especially chipping of the edge portion.
ただし、ウェハプロセスは半導体ウェハと基板の接着が
はずれない温度で行う必要があり1本発明の適用は当た
っては接着がはずれる温度以上のプロセスは済ましであ
ることを前提とする。However, the wafer process must be carried out at a temperature at which the bond between the semiconductor wafer and the substrate does not come off, and the application of the present invention is based on the premise that the process at a temperature higher than the temperature at which the bond comes off has already been completed.
半導体ウェハを基板に接着した後ウェハプロセスを進め
、素子形成を完了した後、その半導体ウェハを基板と一
体化したまま、或いは基板からはずしてチップに切断分
離する。After a semiconductor wafer is bonded to a substrate, the wafer process is carried out, and after element formation is completed, the semiconductor wafer is cut into chips either while being integrated with the substrate or separated from the substrate.
このようにすれば、ウェハプロセスからチップ切出しに
いたる工程で、半導体ウェハの破損、欠けの発生を極め
て少な(することができる。In this way, damage and chipping of the semiconductor wafer can be extremely minimized in the steps from wafer processing to chip cutting.
なお、半導体ウェハを張りつける基板を自動化装置に適
する定型のものにしておけば、半導体ウェハは定型でも
不定形でも、また手作業が困難な小さな寸法のものでも
ウェハプロセスを自動化できる。Note that if the substrate to which the semiconductor wafer is attached is of a standard shape suitable for automation equipment, the wafer process can be automated even if the semiconductor wafer is a regular or irregular shape, or has a small size that is difficult to handle manually.
〔実施例] 第1図は実施例で、第1図(a)乃至(g)は。〔Example] FIG. 1 shows an example, and FIGS. 1(a) to (g) show an example.
本発明による化合物半導体受光素子の製造工程を断面図
で示すものである。1 is a cross-sectional view showing the manufacturing process of a compound semiconductor light-receiving device according to the present invention.
以下、第1図(a)乃至(g)を参照しながら説明する
。This will be explained below with reference to FIGS. 1(a) to 1(g).
第1図(a)参照 半導体ウェハ1として長辺30柵、短辺26+n+n。See Figure 1(a) The semiconductor wafer 1 has 30 long sides and 26 short sides + n + n.
厚さ150μmのn−[nPウェハ1を用いる。An n-[nP wafer 1 with a thickness of 150 μm is used.
第1図(b)参照
全面にP型不純物カドミウム(Cd)を熱拡散して、厚
さ3μmのp−1nP層2を形成する。Referring to FIG. 1(b), a P-type impurity cadmium (Cd) is thermally diffused over the entire surface to form a p-1nP layer 2 having a thickness of 3 μm.
第1図(c)参照 片面を研磨して5片側のp−1nP層を除去する。See Figure 1(c) One side is polished to remove the p-1nP layer on one side of 5.
第1図(d)参照
研磨した片面に接着材41として厚さ0.2μmのAu
Ge41を蒸着する。基板3としてオリフラ付き2イン
チのSiウェハ3を用い9片面に接着材として厚さ0.
2μmのAu42を蒸着する。n−fnPウェハ1の^
uGe形成面とSiウェハ3のAu形成面の間に接着材
としてAuSn箔或いはAuSn塊を挟んで加圧し、窒
素雰囲気中で300°C程度で加熱溶解した後冷却する
。Refer to FIG. 1(d). Au with a thickness of 0.2 μm is used as adhesive material 41 on one side of the polished surface.
Deposit Ge41. A 2-inch Si wafer 3 with an orientation flat is used as the substrate 3, and adhesive material is applied to one side of the substrate 9 to a thickness of 0.
Deposit 2 μm of Au42. n-fnP wafer 1 ^
An AuSn foil or a block of AuSn is sandwiched between the uGe forming surface and the Au forming surface of the Si wafer 3 as an adhesive and pressurized, heated and melted at about 300° C. in a nitrogen atmosphere, and then cooled.
かくして、 n−1nPウエハ1は接着材を介してSi
ウェハ3に接着される。Thus, the n-1nP wafer 1 is bonded to Si through the adhesive.
It is bonded to the wafer 3.
第1図(e)参照
p−1nP層2の上に厚さ0.1 μmのレジスト膜を
被着し、電極形成用の開孔を持つレジストマスク5を形
成する。Referring to FIG. 1(e), a resist film having a thickness of 0.1 μm is deposited on the p-1nP layer 2 to form a resist mask 5 having openings for forming electrodes.
第1図(f)参照
レジストマス−り5をマスクとして金めつきを行い、厚
さ3μmのp電極61.62.63を形成した後。After gold plating was performed using the resist mask 5 as a mask, as shown in FIG. 1(f), p-electrodes 61, 62, and 63 having a thickness of 3 μm were formed.
レジストマスクをエツチングして除去する。Etch and remove the resist mask.
第1図(g)参照
n−1nPウエハ1をSiウェハ3と一体化した状態で
、チップ81.82.83に切断分離する。Referring to FIG. 1(g), the n-1nP wafer 1 is cut and separated into chips 81, 82, and 83 while being integrated with the Si wafer 3.
切断分離後のSiウェハ3はそのままn電極71゜72
、73として使用する。The Si wafer 3 after cutting and separation is directly connected to the n-electrode 71°72
, 73.
かくして、複数の受光素子チップを得ることができた。In this way, a plurality of light receiving element chips could be obtained.
上の実施例で接着材をAuGe/AuSn/Auと言う
構成にしたが、380°Cまで昇温加熱を行えばAuG
eだけでも接着が可能である。ウェハプロセスを50°
C以下で行なえる場合は、エポキシやレジスト等の有機
性接着材を使用することができる。In the above example, the adhesive material was made of AuGe/AuSn/Au, but if heated to 380°C, AuG
Adhesion is possible with only e. 50° wafer process
If it can be done at C or less, an organic adhesive such as epoxy or resist can be used.
また、半導体ウェハ1を接着する基板3はSiウェハに
限らず、 GaAs基板2基板2板英基板ミナ基板等も
用いることもできる。Further, the substrate 3 to which the semiconductor wafer 1 is bonded is not limited to a Si wafer, but may also be a GaAs substrate, two substrates, an English substrate, a Mina substrate, or the like.
さらに、素子形成完了後チップに分割する際。Furthermore, when dividing into chips after completion of element formation.
半導体ウェハ1と基板3を一体化したまま切断分離して
もよいし、加熱処理或いは薬品処理によって半導体ウェ
ハ1と基板3との接着をはずしてからチップに切断分離
してもよい。The semiconductor wafer 1 and the substrate 3 may be cut and separated while being integrated, or the semiconductor wafer 1 and the substrate 3 may be separated from each other by heat treatment or chemical treatment and then cut and separated into chips.
以上説明した様に1本発明によれば、半導体ウェハ、特
に化合物半導体ウェハの素子形成から素子形成後のチッ
プへの分割に至る工程における破損や欠けを防止するこ
とができる。As explained above, according to the present invention, it is possible to prevent damage or chipping of a semiconductor wafer, especially a compound semiconductor wafer, in the steps from forming elements to dividing the semiconductor wafer into chips after forming the elements.
第1図(a)乃至(g)は本発明の実施例で。
製造工程を示す断面図
である。図において。
1は半導体ウェハであってn−1nPウエハ2はp−1
nP層
3は基板であってSiウェハ。
41は接着材であってAuGe。
42は接着材であってAu
43は接着材であってAuSn。
5はレジストマスク。
61乃至63はp電極。
71乃至73はn電極。
81乃至83ばチップ
(aン
(Q)
(ε)
訃す
111′ グDン3(’f/)7)FIGS. 1(a) to 1(g) show examples of the present invention. It is a sectional view showing a manufacturing process. In fig. 1 is a semiconductor wafer and n-1nP wafer 2 is p-1
The nP layer 3 is a substrate and is a Si wafer. 41 is an adhesive material, which is AuGe. 42 is an adhesive material of Au, and 43 is an adhesive material of AuSn. 5 is a resist mask. 61 to 63 are p electrodes. 71 to 73 are n electrodes. 81 to 83 ba tip (aan (Q) (ε) death 111' guDun3 ('f/)7)
Claims (1)
その主面より広い面を持つ固定サイズの基板(3)上に
接着材(41乃至43)を用いて接着し、その接着がは
ずれない温度で該半導体ウェハ(1)に処理を施して素
子形成を完了させた後、該半導体ウェハ(1)を該基板
(3)と一体化したまま或いは該基板(3)からはずし
てチップ(81乃至83)に切断分離することを特徴と
する半導体装置の製造方法。A plurality of types of semiconductor wafers (1) having different sizes are bonded onto a fixed size substrate (3) having a surface wider than the main surface thereof using adhesives (41 to 43), and the bonding is performed at a temperature that will not cause the bond to come off. After processing the semiconductor wafer (1) to complete device formation, the semiconductor wafer (1) is integrated with the substrate (3) or removed from the substrate (3) to form chips (81 to 83). ) A method for manufacturing a semiconductor device, the method comprising cutting and separating the semiconductor device into two parts.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1028851A JPH02208954A (en) | 1989-02-08 | 1989-02-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1028851A JPH02208954A (en) | 1989-02-08 | 1989-02-08 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02208954A true JPH02208954A (en) | 1990-08-20 |
Family
ID=12259883
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1028851A Pending JPH02208954A (en) | 1989-02-08 | 1989-02-08 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02208954A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150118024A (en) * | 2014-04-11 | 2015-10-21 | 가부시기가이샤 디스코 | Machining method of laminated substrate |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6081831A (en) * | 1983-10-12 | 1985-05-09 | Sanyo Electric Co Ltd | Forming process of protecting film on minute chip |
-
1989
- 1989-02-08 JP JP1028851A patent/JPH02208954A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6081831A (en) * | 1983-10-12 | 1985-05-09 | Sanyo Electric Co Ltd | Forming process of protecting film on minute chip |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150118024A (en) * | 2014-04-11 | 2015-10-21 | 가부시기가이샤 디스코 | Machining method of laminated substrate |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980407 |