US7114042B2 - Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment - Google Patents

Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment Download PDF

Info

Publication number
US7114042B2
US7114042B2 US10/443,727 US44372703A US7114042B2 US 7114042 B2 US7114042 B2 US 7114042B2 US 44372703 A US44372703 A US 44372703A US 7114042 B2 US7114042 B2 US 7114042B2
Authority
US
United States
Prior art keywords
data
processor unit
memory access
command
direct memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US10/443,727
Other languages
English (en)
Other versions
US20040236914A1 (en
Inventor
Michael Norman Day
Charles Ray Johns
James Allan Kahle
Peichum Peter Liu
Thuong Quang Truong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JOHNS, CHARLES RAY, DAY, MICHAEL NORMAN, KAHLE, JAMES ALLAN, TROUNG, THUONG QUANG, LIU, PEICHUM PETER
Priority to US10/443,727 priority Critical patent/US7114042B2/en
Priority to KR1020040027540A priority patent/KR100641988B1/ko
Priority to TW093112936A priority patent/TWI269180B/zh
Priority to JP2004148226A priority patent/JP3974597B2/ja
Priority to CNB2004100447825A priority patent/CN1273899C/zh
Publication of US20040236914A1 publication Critical patent/US20040236914A1/en
Priority to HK05103951A priority patent/HK1070719A1/xx
Priority to US11/468,317 priority patent/US7814281B2/en
Publication of US7114042B2 publication Critical patent/US7114042B2/en
Application granted granted Critical
Priority to JP2006334314A priority patent/JP4730742B2/ja
Adjusted expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47G—HOUSEHOLD OR TABLE EQUIPMENT
    • A47G19/00—Table service
    • A47G19/22—Drinking vessels or saucers used for table service
    • A47G19/2205—Drinking glasses or vessels
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D85/00—Containers, packaging elements or packages, specially adapted for particular articles or materials
    • B65D85/70—Containers, packaging elements or packages, specially adapted for particular articles or materials for materials not otherwise provided for
    • B65D85/804—Disposable containers or packages with contents which are mixed, infused or dissolved in situ, i.e. without having been previously removed from the package
    • B65D85/808—Disposable containers or packages with contents which are mixed, infused or dissolved in situ, i.e. without having been previously removed from the package for immersion in the liquid to release part or all of their contents, e.g. tea bags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip

Definitions

  • the invention relates generally to atomic update of memory and, more particularly, to employment of atomic updates using direct memory access commands with attached processor units.
  • atomic read/modify/write capabilities are frequently provided in order to control the synchronization and access to memory shared by programs executing on multiple MPUs.
  • “Atomic” commands can generally be defined as commands which allow data in memory to be read, modified and written as if the sequence were a single operation with respect to other units potentially accessing that data area. This is traditionally done by a hardware sequence that either locks out other unit access to the memory area, until the entire sequence is done, or uses a more primitive load with reservation and conditional store technique. Generally, this is done to ensure that an area of memory is completely updated and consistent before being read or written to by another MPU or I/O unit with access to the memory—that is, the atomic command or update sequence is “finished” with that memory area.
  • Atomic commands frequently take the form of special instructions, such as “compare and swap,” “test and set,” “fetch and no-op,” “fetch and store,” and so on.
  • An alternative technique is to provide a more fundamental “load and reserve” and “store conditional” instruction pair in an MPU which provides the capability to implement the atomic operation sequences in software. These techniques can work well in a symmetric multiprocessor system consisting of homogeneous MPUs.
  • the MPUs are arranged in a conventional shared memory style.
  • Specialized processors, attached processor units (APUs) have their own private instruction and data memory which have indirect access to the shared memory through a block move ordered by a direct memory access (DMA) engine.
  • DMA direct memory access
  • MPUs and APUs employing DMA engines accessing shared memory, as peers, there exists a need to extend an atomic update mechanism to the DMA engines. This is generally done in order to provide a facility to coordinate access to data in the shared memory.
  • DMA engine that can be employed by APUs to copy data between APU local storage and shared system memory while participating as a peer with other MPUs and APU/DMA engines in atomic updates of shared memory.
  • the present invention provides atomic update primitives for an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA.
  • At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.
  • FIG. 1 schematically depicts a system map of multiple busses coupled to a system memory, a DMA engine, an atomic facility and a local store;
  • FIG. 2 illustrates a method of employing DMA get lockline with reservation and put lockline conditional into and out of a cache and local store
  • FIG. 3 illustrates a method of employing DMA lockline put unconditional.
  • a processing unit may be a sole processor of computations in a device.
  • the PU is typically referred to as an MPU (main processing unit).
  • the processing unit may also be one of many processing units that share the computational load according to some methodology or algorithm developed for a given computational device.
  • all references to processors shall use the term MPU whether the MPU is the sole computational element in the device or whether the MPU is sharing the computational element with other MPUs.
  • FIG. 1 disclosed is a system 100 that allows for an APU 110 to participate more autonomously as a peer in a multiprocessor environment. This is performed through the employment of the APU 110 having indirect access to a system memory 170 through block mode employment of a DMA engine 115 .
  • the APU 110 employs atomic read/modify/write sequences by gaining access and locking reservation granules of the shared memory 170 using a “load and reserve” (getllar) lock line command and the “conditional store” (putllc) or “unconditional store” (putllu) lock line commands.
  • getllar load and reserve
  • putllc conditional store
  • putllu unconditional store
  • the system 100 comprises one or more MPU complexes 193 coupled to the bus interface controller (BIC) 150 , as well as one or more APU complexes 192 coupled to the BIC 150 .
  • the BIC 150 is coupled to a memory controller 160 , which is in turn coupled to the system/shared memory 170 .
  • At least one APU/DMA complex 192 and at least one MPU unit complexes 193 , having one or more MPUs 180 comprise the computational capability of the system.
  • the APU complex 192 comprises the APU 110 coupled to a local store 105 .
  • the APU 110 is coupled to a DMA queue 120 through a control bus.
  • the DMA queue 120 is coupled to a DMA engine.
  • the DMA engine 115 is coupled to an atomic facility 130 .
  • the atomic facility 130 comprises a reservation station (RS) 135 and an atomic cache 137 .
  • the atomic cache 137 can be a level two (L2) cache.
  • the atomic facility 130 is coupled to a BIC 150 through a control bus and a snoop bus.
  • the MPU complex 193 comprises one or more MPUs 180 coupled to an L2 cache 187 which is coupled to the BIC 150 .
  • the BIC 150 is coupled to a memory controller 160 , which is in turn coupled to the system/shared memory 170 .
  • a plurality of APU complexes 192 are employed in the system 100 , but without the employment of MPU complexes 193 , to support atomic update sequences between the APUs 110 via DMA commands.
  • other units that support atomic update sequences via DMA commands are within the scope of the present invention.
  • the APU 110 for such reasons as synchronization, employs atomic operations through the use of getllar, putllc, and putllu lock line DMA commands.
  • the DMA commands are issued by the DMA engine 115 at the bequest of the APU 110 , after being appropriately sorted by the DMA queue 120 .
  • the lockline DMA commands are forwarded to the front of the DMA queue 120 for immediate execution since acquiring locks and releasing locks are typically synchronous with respect to the program executing in the APU 110 .
  • the RS 135 is set by the issuance of the DMA command getllar.
  • the data of a selected memory address in the system memory 170 , at the command of the DMA engine 115 is conveyed to the local store 105 for processing.
  • this data transfer can be a cache line, 128 bytes.
  • This data can sometimes be found in the atomic cache 137 (if a previously issued getllar was used to access this data).
  • a request is made to the BIC 150 for the data, and the data retrieved from the system memory 170 or a cache associated with another attached unit (MPU or APU, respectively) is copied into local store 105 and also copied into the atomic cache 137 .
  • MPU or APU another attached unit
  • the APU 110 program waits for getllar command completion by reading the command completion status from the DMA queue 120 via the control bus 103 .
  • the control bus 103 generally comprises a plurality of channels, wherein each channel carries predefined information. The getllar command is reported as “complete” once the reservation is set in RS 135 and the data copied to local store 105 .
  • the APU 110 program typically compares the data in local store 130 via local store bus 107 with an expected result, for example a value indicating that the lock was taken, or lock was free, and either reissues the getllar command via control bus 101 to DMA queue 120 if the value was not the expected result (such as a value designating lock taken).
  • an expected result for example a value indicating that the lock was taken, or lock was free
  • the APU 110 program modifies the data in local store via local store bus 107 (to designate lock taken) and issues the putllc command via control bus 103 to DMA queue 120 to attempt to either “atomically” update the data in the atomic cache 137 , or, alternatively, to ensure that the data it has in local store 105 is the latest copy from system memory 170 or another unit's cache of system memory.
  • a “kill” type snoop of the atomic cache 137 for an address that falls within the reservation granule address stored in the reservation station 135 is received by the atomic facility 130 from the BIC 150 , the reservation previously set by the execution of the getllar command is reset in reservation station 135 .
  • the kill type snoop command is typically received when other units attached to the BIC 150 attempt to modify (write) data that can be contained in atomic cache 137 .
  • the DMA engine 115 marks the putllc command with “reservation lost” status in the DMA queue 120 , and does not copy the data from local store 105 to atomic cache 137 or to the system memory 170 . If the reservation in reservation station 135 still exists for the reservation granule addressed by the putllc command, then the atomic facility 130 sends a kill type snoop command through the BIC 150 to other units, resetting any reservations the other units (APUs or MPUs) might have made in their atomic facilities for the same reservation granule. This is because the atomic facility 130 has finished processing this update of data before the other processors (MPUs, APUs) attached to BIC 150 had finished their processing, and this updated data becomes the data that should therefore be further employed by other processors.
  • the DMA engine 115 copies the data from local store 105 to atomic cache 137 and the reservation is reset in reservation station 135 .
  • the DMA engine 115 then sets “Succeeded” status for the putllc command in the DMA queue 120 .
  • the APU 110 program uses the control bus 103 to wait for and read completion status of the putllc command from DMA queue 120 to determine if the status is “Succeeded” or “Reservation lost.” If “Succeeded,” the atomic operation is complete, if “Reservation lost,” the entire sequence starting with the issuance of the getllar command must be retried by the APU 110 program.
  • the APU 110 issues a putllu command to release the “lock.”
  • the putllu command is generally employed to unconditionally transfer the data from the APU 110 local store to the atomic cache 137 . If the cache line is marked as present and exclusive in the atomic cache 137 , the DMA engine 115 transfers data from the APU 110 local store to the atomic cache 137 .
  • the atomic facility issues a “declaim” snoop command which invalidates cache lines in other unit's caches having a copy of this data.
  • the line is marked “exclusive” in this cache 137 , and the DMA engine 115 transfers data from the APU 110 local store to the atomic cache 137 .
  • the atomic facility 130 determines whether the line is present in some other unit's cache by issuing a snoop request through BIC 150 .
  • the data is transferred from the other unit's cache to the atomic cache associated with the system 100 and the cache line containing the data is invalidated in the cache from which the data has been transferred. If the data is not present in another unit's cache, the memory controller 160 will supply the data from the shared memory 170 . Either way, the cache line in the atomic cache containing the data is delineated as “exclusive.” Then, the DMA engine 115 transfers data from the local store 105 to the atomic cache 137 .
  • the APU 110 will issue in a loop the getllar command until the APU 110 gets a match for what it is comparing, which can be a value indicating a lock free.
  • the “swap” is attempted. That is, the value is changed, in some cases to a value indicating “lock taken.”
  • the putllc is then issued to “atomically swap the value,” in some cases swap the old value of lock free with the new value of lock taken.
  • the APU 110 “owns” the resource, in other words has either read or read/write privileges, and performs the further operations on the “locked” object.
  • the APU 110 is finished, it “releases the lock,” or in other words changes the value from “lock taken” to a value of “lock free.” It does so by using the putllu command.
  • atomic cache 137 plays a role in terms of atomic update performance. By their very nature, atomic updates of the same data can be frequently concurrently attempted by multiple APU complexes (APU/DMA Units) 192 , MPU complexes 193 attached to BIC 150 . Because atomic cache 137 can have the most up to date data associated with the lock line, when other caches are to be updated, it could be updated with the information from another atomic cache 137 and not necessarily from the system memory 170 . In this embodiment, cache to cache transfers between multiple units can occur on the same integrated circuit chip, and can be substantially faster than system memory to cache transfers which generally occur between two separate integrated circuit chips.
  • APU complexes APU/DMA Units
  • the system 100 saves time by caching the results of DMA transfers of data used for synchronization in the atomic cache 137 , but not caching all data transferred from the system memory 170 , such as those memory transfers not of a synchronization nature.
  • This saves significant chip real estate, in that the atomic cache 137 can be smaller than a cache that is employed to cache all DMA transfers of data between system memory and local store.
  • the time required to retrieve specified data from the atomic cache 137 has been reduced, as the retrieval granule can be predefined to match a cache line size and alignment.
  • Non-lockline DMA commands can have varying transfer sizes and alignments.
  • cache lines (128 bytes times 4) are reserved for data accessed using the lock line commands in the atomic cache 137 , and this is the basic unit of cache to cache, cache to local store, system memory to cache, and so on, memory transfer.
  • this is the basic unit of cache to cache, cache to local store, system memory to cache, and so on, memory transfer.
  • other reservation granule sizes can also be employed.
  • the APUs themselves can provide the necessary synchronization and mutual exclusion directly through employment of the “lock line” commands.
  • Method 200 can employ specific commands and parameters to determine which of the atomic commands has been issued, and whether an error condition has resulted in an improper invocation or execution of a command.
  • the getllar command is issued by the APU 110 .
  • the APU 110 issues the atomic DMA command “getllar” onto its coupled control bus to be conveyed to the DMA queue 120 .
  • the getllar command comprises three parameters.
  • a first parameter is the local store address (LSA) to which the retrieved data is eventually to be sent in the local store 105 .
  • a second parameter is the effective address high (EAH) which is the high address of the data in system memory to be copied from.
  • the third parameter is the effective address low (EAL) which is the low address of the data in system memory to be copied from.
  • the EAH and EAL parameters define the location in shared memory involved in the atomic update sequence.
  • step 205 the getllar command is placed to the front of the queue. This command is placed on the DMA queue 120 . This command and associated parameters is written through a series of “write to channel” commands.
  • the DMA engine orders a transfer of data from either the system memory 170 or an L2 cache 187 or atomic cache 137 to the local store 105 .
  • the BIC 150 then implements this data request. The BIC 150 first requests the selected data from any of the MPU complex(es) 193 L2 cache 187 , and/or APU complex(es) 192 atomic cache 137 , via a snoop request. If the requested data is not found in any of the caches, the BIC 150 then requests the data from the system memory 170 .
  • step 220 as the data is transferred from either the L2 cache 187 or the system memory 170 , as appropriate, a copy of the transferred data is stored in the atomic cache 137 and the DMA engine transfers the data from the atomic cache 137 to local store 105 .
  • step 225 a reservation is set up by the DMA engine 115 to the RS 135 with an address designating the reservation granule location involved in the getllar command.
  • step 227 the APU 110 waits for the completion notification that the getllar command is completed.
  • step 230 the APU 110 processes the data that was placed in its local store 105 .
  • step 235 after processing and modifying the lock line data in local store, the APU 110 issues a putllc command.
  • step 240 the atomic facility 130 determines if reservation station 130 still has a reservation for the lock line reservation granule previously set by the getllar command. If there is no reservation, then the putllc command status is set to “failed” in step 242 , and is forwarded to step 290 .
  • step 265 the DMA engine 115 transfers the data from the local store 105 to the atomic cache 137 .
  • step 270 the reservation station for this cache line is reset within the reservation station 135 .
  • step 280 the status of the putllc command is stored as a “success” in the DMA queue 120 .
  • step 290 the APU program reads the lock line status for the completion or non-completion of the putllc command.
  • step 295 if the putllc command is a failure, the entire sequence is re-executed beginning with step 205 , and another getllar command issues. However, if the putllc command is a success, then the atomic update sequence of FIG. 2 ends in step 297 .
  • FIG. 3 disclosed is a method 300 for issuing a putllu command.
  • the putllu command is used for releasing a software lock previously acquired by the atomic update sequence of FIG. 2 .
  • step 305 the APU 110 issues a putllu command into the DMA queue.
  • step 310 the DMZ4 engine 115 processes the putllu command, and requests a write of 128 bytes to the atomic cache 137 .
  • step 315 the atomic cache 137 reads its directory to determine if the line is present in the atomic cache 137 and is in an exclusive state.
  • step 320 the atomic cache 137 determines whether the cache line is present in the associated atomic cache 137 , and whether it is in an exclusive state.
  • the atomic cache 137 requests the BIC 150 to obtain the data with exclusive access.
  • “Modified, Exclusive, Shared, and Invalid” (MESI) cache control protocol can be employed, other forms of cache control protocols are within the scope of the present invention.
  • the atomic facility 130 orders the DMA engine 115 to begin to transfer from the local store 105 to the atomic cache 137 data.
  • the atomic facility 130 orders the DMA engine 115 to begin to transfer from the local store 105 to the atomic cache 137 data.
  • having the transfer of atomic data transfers in the atomic cache 137 allows for much faster processing to the local store 105 over a data bus from the atomic cache 137 than would otherwise be present between a transfer from the local store 105 to the system/shared memory 170 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
US10/443,727 2003-05-22 2003-05-22 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment Expired - Fee Related US7114042B2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US10/443,727 US7114042B2 (en) 2003-05-22 2003-05-22 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment
KR1020040027540A KR100641988B1 (ko) 2003-05-22 2004-04-21 비대칭형 단일 칩 이종 멀티프로세서 컴퓨터 시스템, 공유 메모리의 직접 메모리 액세스를 아토믹 업데이트하는 방법, 및 아토믹 업데이트 장치
TW093112936A TWI269180B (en) 2003-05-22 2004-05-07 Asymmetric single-chip heterogeneous multiprocessor computer system and method of providing atomic update primitives for use therein
CNB2004100447825A CN1273899C (zh) 2003-05-22 2004-05-18 在非对称异构多处理器环境中提供原子更新原语的方法
JP2004148226A JP3974597B2 (ja) 2003-05-22 2004-05-18 非対称型異種マルチプロセッサ環境でアトミック更新プリミティブを提供するための方法
HK05103951A HK1070719A1 (en) 2003-05-22 2005-05-11 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment
US11/468,317 US7814281B2 (en) 2003-05-22 2006-08-30 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment
JP2006334314A JP4730742B2 (ja) 2003-05-22 2006-12-12 共有メモリの直接メモリ・アクセスのアトミック更新のための装置、及びその方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/443,727 US7114042B2 (en) 2003-05-22 2003-05-22 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/468,317 Division US7814281B2 (en) 2003-05-22 2006-08-30 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment

Publications (2)

Publication Number Publication Date
US20040236914A1 US20040236914A1 (en) 2004-11-25
US7114042B2 true US7114042B2 (en) 2006-09-26

Family

ID=33450499

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/443,727 Expired - Fee Related US7114042B2 (en) 2003-05-22 2003-05-22 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment
US11/468,317 Expired - Fee Related US7814281B2 (en) 2003-05-22 2006-08-30 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/468,317 Expired - Fee Related US7814281B2 (en) 2003-05-22 2006-08-30 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment

Country Status (6)

Country Link
US (2) US7114042B2 (ko)
JP (2) JP3974597B2 (ko)
KR (1) KR100641988B1 (ko)
CN (1) CN1273899C (ko)
HK (1) HK1070719A1 (ko)
TW (1) TWI269180B (ko)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050216610A1 (en) * 2004-03-25 2005-09-29 International Business Machines Corporation Method to provide cache management commands for a DMA controller
US20080005443A1 (en) * 2006-06-28 2008-01-03 Hidenori Matsuzaki Computer system and data pre-fetching method
US8412862B2 (en) 2008-12-18 2013-04-02 International Business Machines Corporation Direct memory access transfer efficiency
US10185673B2 (en) 2015-11-12 2019-01-22 Samsung Electronics Co., Ltd. Multi-processor system including memory shared by multi-processor and method thereof

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7233998B2 (en) * 2001-03-22 2007-06-19 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
US7549145B2 (en) 2003-09-25 2009-06-16 International Business Machines Corporation Processor dedicated code handling in a multi-processor environment
US7389508B2 (en) 2003-09-25 2008-06-17 International Business Machines Corporation System and method for grouping processors and assigning shared memory space to a group in heterogeneous computer environment
US20050071828A1 (en) * 2003-09-25 2005-03-31 International Business Machines Corporation System and method for compiling source code for multi-processor environments
US7496917B2 (en) * 2003-09-25 2009-02-24 International Business Machines Corporation Virtual devices using a pluarlity of processors
US7415703B2 (en) * 2003-09-25 2008-08-19 International Business Machines Corporation Loading software on a plurality of processors
US7516456B2 (en) * 2003-09-25 2009-04-07 International Business Machines Corporation Asymmetric heterogeneous multi-threaded operating system
US7478390B2 (en) * 2003-09-25 2009-01-13 International Business Machines Corporation Task queue management of virtual devices using a plurality of processors
US7444632B2 (en) 2003-09-25 2008-10-28 International Business Machines Corporation Balancing computational load across a plurality of processors
US7523157B2 (en) * 2003-09-25 2009-04-21 International Business Machines Corporation Managing a plurality of processors as devices
US7774750B2 (en) * 2005-07-19 2010-08-10 Microsoft Corporation Common concurrency runtime
US7509463B2 (en) * 2005-12-01 2009-03-24 Sony Computer Entertainment, Inc. Cell processor atomic compare and swap using dedicated synergistic processor element
US7624237B2 (en) * 2006-05-03 2009-11-24 International Business Machines Corporation Compare, swap and store facility with no external serialization
US9274859B2 (en) 2006-05-25 2016-03-01 Nvidia Corporation Multi processor and multi thread safe message queue with hardware assistance
GB2443277B (en) * 2006-10-24 2011-05-18 Advanced Risc Mach Ltd Performing diagnostics operations upon an asymmetric multiprocessor apparatus
US8024521B2 (en) * 2007-03-13 2011-09-20 Sony Computer Entertainment Inc. Atomic operation on non-standard sized data using external cache
US8266391B2 (en) * 2007-06-19 2012-09-11 SanDisk Technologies, Inc. Method for writing data of an atomic transaction to a memory device
US20090077322A1 (en) * 2007-09-19 2009-03-19 Charles Ray Johns System and Method for Getllar Hit Cache Line Data Forward Via Data-Only Transfer Protocol Through BEB Bus
US8275963B2 (en) * 2008-02-01 2012-09-25 International Business Machines Corporation Asynchronous memory move across physical nodes with dual-sided communication
US8015380B2 (en) * 2008-02-01 2011-09-06 International Business Machines Corporation Launching multiple concurrent memory moves via a fully asynchronoous memory mover
US8356151B2 (en) * 2008-02-01 2013-01-15 International Business Machines Corporation Reporting of partially performed memory move
US7941627B2 (en) * 2008-02-01 2011-05-10 International Business Machines Corporation Specialized memory move barrier operations
US8327101B2 (en) * 2008-02-01 2012-12-04 International Business Machines Corporation Cache management during asynchronous memory move operations
US8095758B2 (en) * 2008-02-01 2012-01-10 International Business Machines Corporation Fully asynchronous memory mover
US8245004B2 (en) * 2008-02-01 2012-08-14 International Business Machines Corporation Mechanisms for communicating with an asynchronous memory mover to perform AMM operations
JP5151559B2 (ja) * 2008-02-29 2013-02-27 富士通株式会社 プログラム実行システム
US20090248919A1 (en) * 2008-03-25 2009-10-01 Jerzy Szwagrzyk Method for external fifo acceleration
US20090254712A1 (en) * 2008-04-02 2009-10-08 Naveen Cherukuri Adaptive cache organization for chip multiprocessors
CN101950282B (zh) * 2010-08-30 2012-05-23 中国科学院计算技术研究所 一种多处理器系统及其同步引擎
US8341316B2 (en) * 2010-11-17 2012-12-25 Advanced Micro Devices, Inc. Method and apparatus for controlling a translation lookaside buffer
US9280348B2 (en) 2012-03-28 2016-03-08 International Business Machines Corporation Decode time instruction optimization for load reserve and store conditional sequences
EP2862068B1 (en) 2012-06-15 2022-07-06 Intel Corporation Reordered speculative instruction sequences with a disambiguation-free out of order load store queue
KR101996351B1 (ko) 2012-06-15 2019-07-05 인텔 코포레이션 통합된 구조를 갖는 동적 디스패치 윈도우를 가지는 가상 load store 큐
KR101826399B1 (ko) 2012-06-15 2018-02-06 인텔 코포레이션 Load store 재정렬 및 최적화를 구현하는 명령어 정의
KR101996462B1 (ko) 2012-06-15 2019-07-04 인텔 코포레이션 명확화 없는 비순차 load store 큐
KR101667167B1 (ko) 2012-06-15 2016-10-17 소프트 머신즈, 인크. Load store 재정렬 및 최적화로부터 생기는 투기적 포워딩 예측 착오/오류로부터의 복원을 구현하는 방법 및 시스템
EP2862063B1 (en) * 2012-06-15 2022-09-14 Intel Corporation A lock-based and synch-based method for out of order loads in a memory consistency model using shared memory resources
US10320861B2 (en) 2015-09-30 2019-06-11 Google Llc System and method for automatic meeting note creation and sharing using a user's context and physical proximity
CN105354153B (zh) * 2015-11-23 2018-04-06 浙江大学城市学院 一种紧耦合异构多处理器数据交换缓存的实现方法
US9652385B1 (en) * 2015-11-27 2017-05-16 Arm Limited Apparatus and method for handling atomic update operations
CN109324838B (zh) * 2018-08-31 2022-05-10 深圳市元征科技股份有限公司 单片机程序的执行方法、执行装置及终端
US11119781B2 (en) 2018-12-11 2021-09-14 International Business Machines Corporation Synchronized access to data in shared memory by protecting the load target address of a fronting load
US20230116945A1 (en) * 2020-04-03 2023-04-20 Mobileye Vision Technologies Ltd. A multi-part compare and exchange operation
US11106608B1 (en) * 2020-06-22 2021-08-31 International Business Machines Corporation Synchronizing access to shared memory by extending protection for a target address of a store-conditional request

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5727172A (en) * 1995-05-01 1998-03-10 Motorola, Inc. Method and apparatus for performing atomic accesses in a data processing system
KR0135927B1 (ko) 1994-11-21 1998-06-15 양승택 다중 프로세서 시스템에서 아토믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치
US5822588A (en) * 1995-06-09 1998-10-13 Sun Microsystem, Inc. System and method for checking the use of synchronization locks in a multi-threaded target program
WO1999023559A1 (en) 1997-11-05 1999-05-14 Unisys Corporation Split lock operation to provide exclusive access to memory during non-atomic operations
KR20000006264A (ko) 1998-06-19 2000-01-25 케네쓰 올센 확률적큐로크
US6493741B1 (en) * 1999-10-01 2002-12-10 Compaq Information Technologies Group, L.P. Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2045789A1 (en) 1990-06-29 1991-12-30 Richard Lee Sites Granularity hint for translation buffer in high performance processor
JPH08287022A (ja) 1995-03-31 1996-11-01 Internatl Business Mach Corp <Ibm> マルチプロセッサ・システム及びその排他的制御方法
US5794068A (en) * 1996-03-18 1998-08-11 Advanced Micro Devices, Inc. CPU with DSP having function preprocessor that converts instruction sequences intended to perform DSP function into DSP function identifier
US5887134A (en) * 1997-06-30 1999-03-23 Sun Microsystems System and method for preserving message order while employing both programmed I/O and DMA operations
US6098156A (en) * 1997-07-22 2000-08-01 International Business Machines Corporation Method and system for rapid line ownership transfer for multiprocessor updates
US6728839B1 (en) * 1998-10-28 2004-04-27 Cisco Technology, Inc. Attribute based memory pre-fetching technique
US6347347B1 (en) * 1999-07-15 2002-02-12 3Com Corporation Multicast direct memory access storing selected ones of data segments into a first-in-first-out buffer and a memory simultaneously when enabled by a processor
JP3853114B2 (ja) * 1999-07-30 2006-12-06 松下電器産業株式会社 インターフェースの設計方法
US6496905B1 (en) 1999-10-01 2002-12-17 Hitachi, Ltd. Write buffer with burst capability
US6691178B1 (en) * 2000-02-22 2004-02-10 Stmicroelectronics, Inc. Fencepost descriptor caching mechanism and method therefor
JP2002163239A (ja) 2000-11-22 2002-06-07 Toshiba Corp マルチプロセッサシステムおよびその制御方法
EP1413098A2 (en) * 2001-07-02 2004-04-28 GlobeSpan Virata, Inc. Communications system using rings architecture
US7266587B2 (en) * 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
US7185150B1 (en) * 2002-09-20 2007-02-27 University Of Notre Dame Du Lac Architectures for self-contained, mobile, memory programming

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0135927B1 (ko) 1994-11-21 1998-06-15 양승택 다중 프로세서 시스템에서 아토믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치
US5727172A (en) * 1995-05-01 1998-03-10 Motorola, Inc. Method and apparatus for performing atomic accesses in a data processing system
US5822588A (en) * 1995-06-09 1998-10-13 Sun Microsystem, Inc. System and method for checking the use of synchronization locks in a multi-threaded target program
WO1999023559A1 (en) 1997-11-05 1999-05-14 Unisys Corporation Split lock operation to provide exclusive access to memory during non-atomic operations
KR20010031689A (ko) 1997-11-05 2001-04-16 보베테 죤스 비-원자 연산동안 메모리에 배타적 접근을 제공하는분리된 잠금연산방법
KR20000006264A (ko) 1998-06-19 2000-01-25 케네쓰 올센 확률적큐로크
US6578033B1 (en) 1998-06-19 2003-06-10 Sun Microsystems, Inc. System and method for accessing a shared computer resource using a lock featuring different spin speeds corresponding to multiple states
US6493741B1 (en) * 1999-10-01 2002-12-10 Compaq Information Technologies Group, L.P. Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050216610A1 (en) * 2004-03-25 2005-09-29 International Business Machines Corporation Method to provide cache management commands for a DMA controller
US7657667B2 (en) 2004-03-25 2010-02-02 International Business Machines Corporation Method to provide cache management commands for a DMA controller
US20080005443A1 (en) * 2006-06-28 2008-01-03 Hidenori Matsuzaki Computer system and data pre-fetching method
US7606961B2 (en) * 2006-06-28 2009-10-20 Kabushiki Kaisha Toshiba Computer system and data pre-fetching method
US8412862B2 (en) 2008-12-18 2013-04-02 International Business Machines Corporation Direct memory access transfer efficiency
US10185673B2 (en) 2015-11-12 2019-01-22 Samsung Electronics Co., Ltd. Multi-processor system including memory shared by multi-processor and method thereof
US10482042B2 (en) 2015-11-12 2019-11-19 Samsung Electronics Co., Ltd. Multi-processor system including memory shared by multi-processor and method thereof
US10949364B2 (en) 2015-11-12 2021-03-16 Samsung Electronics Co., Ltd. Multi-processor system including memory shared by multi-processor and method thereof

Also Published As

Publication number Publication date
HK1070719A1 (en) 2005-06-24
CN1273899C (zh) 2006-09-06
US7814281B2 (en) 2010-10-12
CN1573715A (zh) 2005-02-02
TW200511023A (en) 2005-03-16
KR100641988B1 (ko) 2006-11-06
JP4730742B2 (ja) 2011-07-20
KR20040100884A (ko) 2004-12-02
TWI269180B (en) 2006-12-21
JP2007122741A (ja) 2007-05-17
US20070016733A1 (en) 2007-01-18
JP3974597B2 (ja) 2007-09-12
US20040236914A1 (en) 2004-11-25
JP2004348734A (ja) 2004-12-09

Similar Documents

Publication Publication Date Title
US7114042B2 (en) Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment
US9405595B2 (en) Synchronizing multiple threads efficiently
US6625698B2 (en) Method and apparatus for controlling memory storage locks based on cache line ownership
US7620954B2 (en) Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors
JP4981041B2 (ja) キャッシュする方法、装置及びシステム
JP2001522091A (ja) メモリ最適化状態
US20120110303A1 (en) Method for Process Synchronization of Embedded Applications in Multi-Core Systems
JP2008503821A (ja) 小容量キャッシュシステムにおけるアトミック予約ライン上のライトバックを無効化する方法およびシステム
US7743217B2 (en) Cache consistency in a multiprocessor system with shared memory
US7080213B2 (en) System and method for reducing shared memory write overhead in multiprocessor systems
JP3550092B2 (ja) キャッシュ装置及び制御方法
JP2020506483A (ja) コンペアアンドスワップトランザクション
JP3814521B2 (ja) データ処理方法および装置
US9367461B2 (en) Ordering constraint management within coherent memory systems
JP3093609B2 (ja) キャッシュメモリの記憶一致制御装置及び方法
US7073004B2 (en) Method and data processing system for microprocessor communication in a cluster-based multi-processor network
US20220317927A1 (en) Adaptive memory consistency in disaggregated datacenters
CN116680229A (zh) 一种分布式共享内存协议的操作方法
CN116685958A (zh) 一种访问数据的方法和装置
JPH04163658A (ja) システムバス制御方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DAY, MICHAEL NORMAN;JOHNS, CHARLES RAY;KAHLE, JAMES ALLAN;AND OTHERS;REEL/FRAME:014107/0383;SIGNING DATES FROM 20030424 TO 20030515

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 8

SULP Surcharge for late payment

Year of fee payment: 7

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.)

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20180926