US6931259B2 - Integrated circuit architecture for programmable wireless device - Google Patents

Integrated circuit architecture for programmable wireless device Download PDF

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Publication number
US6931259B2
US6931259B2 US09/969,941 US96994101A US6931259B2 US 6931259 B2 US6931259 B2 US 6931259B2 US 96994101 A US96994101 A US 96994101A US 6931259 B2 US6931259 B2 US 6931259B2
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pda
bus
wireless
high speed
microprocessor
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US20030064747A1 (en
Inventor
Laura E Simmons
James Daren Bledsoe
Daniel I Croft
Patrick A. McKinley
Gregory Frank Carlson
Ignacio Jose Perez
Paul Anthony Chenard
Raymond Jensen Hasler
Shelly Rose Reasoner
Todd Alan McClelland
Thomas P. Bruch
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Avago Technologies International Sales Pte Ltd
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Agilent Technologies Inc
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Priority to EP02013510A priority patent/EP1300987B1/en
Priority to DE60206000T priority patent/DE60206000T2/de
Priority to JP2002289742A priority patent/JP4392160B2/ja
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/72—Mobile telephones; Cordless telephones, i.e. devices for establishing wireless links to base stations without route selection
    • H04M1/724—User interfaces specially adapted for cordless or mobile telephones
    • H04M1/72403—User interfaces specially adapted for cordless or mobile telephones with means for local support of applications that increase the functionality
    • H04M1/72409—User interfaces specially adapted for cordless or mobile telephones with means for local support of applications that increase the functionality by interfacing with external accessories
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02—Terminal devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02—Terminal devices
    • H04W88/04—Terminal devices adapted for relaying to or from another terminal or user

Definitions

  • the first operations to benefit from reprogrammable software are operations in the baseband.
  • the software that performs the baseband coding and decoding is reprogrammable.
  • Wireless devices that morph through different “personalities” on the fly would be a boon to their users. But at the same time they create policy problems, as new technologies that cross boundaries often do. Historically, the FCC authorizes each piece of equipment for a type of use and specific channel. How should the regulators license mobile phones and base stations that can readily be changed after they're in use? How free should third parties be to load new software into your phone? How will it be possible to distinguish legitimate upgrades of the network from rogues trying subvert it?
  • the present invention is an integrated system on a chip that combines wireless, graphics, and multimedia.
  • the graphics and multimedia features may be programmed by the end user while restricting programmability of the wireless features.
  • the system includes a wireless section bidirectionally communicating with a high speed wireless bus.
  • a personal data assistant (PDA) section bidirectionally communicating with a high speed PDA bus.
  • a mail box electrically connected to the high speed wireless buss and the high speed PDA bus.
  • the entire system is preferably integrated on a unitary substrate.
  • the wireless section includes a baseband processor connected to the high speed wireless bus.
  • a general wireless microprocessor connects to the high speed wireless bus.
  • a wireless memory controller and a low speed wireless bus bidirectionally communicates to the high speed wireless bus.
  • a wireless peripheral bidirectionally communicates to the low speed wireless bus.
  • the PDA section includes a multimedia microprocessor and a PDA microprocessor connected to the high speed PDA bus.
  • a PDA memory controller and a low speed PDA bus bidirectionally communicates to the high speed PDA bus.
  • At least one PDA peripheral bidirectionally communicates to the low speed PDA bus.
  • An optional high multi-media bus may be connected to the PDA memory controller.
  • a high speed graphics bus connects to the PDA peripheral and the PDA memory controller.
  • FIG. 1 is top level functional block diagram of the present invention.
  • FIG. 2 illustrates a functional block diagram of the wireless section shown in FIG. 1 .
  • FIG. 3 illustrates a functional block diagram of the PDA section shown in FIG. 1 .
  • FIG. 4 illustrates at alternate embodiment of the present invention.
  • FIG. 5 illustrates an alternate embodiment of the general system shown in FIG. 1 .
  • a main problem associated with prior art integrated user programmable and cellular platform is the opportunity for a user application to bring down the cellular network if it corrupts the memory region.
  • the present invention has two major subsystems: a user-programmable sub-system, containing the multi-media and personal digital assistant (PDA) functions, and a protected wireless subsystem. Access to the wireless subsystem from the user-programmable sub-system is not supported. From the user's point of view, the wireless subsystem is a black box that cannot be programmed. Control information is passed to from the user-programmable subsystem to the wireless subsystem via a mailbox. The control data in the mailbox must correspond to a predefined set of operations or it will be rejected by the wireless subsystem. Thus, the end user can influence the wireless subsystem without having direct access to it.
  • FIG. 1 is top level functional block diagram of the present invention.
  • a system 10 includes a wireless section 12 in bi-directional communication with a high speed wireless bus 14 .
  • a personal digital assistant (PDA) section 16 bidirectionally communicates with a high speed PDA bus 18 .
  • a mail box 20 electrically connects the high speed wireless bus 14 and the high speed PDA bus 18 .
  • the entire system 10 is preferably integrated onto a unitary substrate (not shown). Throughout the entire system, it is preferable that the busses be 32 bits wide.
  • Communication between subsystems is accomplished via an interrupt driven mailbox system.
  • the user-programmable subsystem wishes to assign a task to the protected wireless subsystem, it places the task into the mailbox, along with any required information and pointers, and signals an interrupt to the general wireless processor that it has a message waiting. The processor then reads its mailbox and performs the task.
  • a high-speed multi-layer bus system that allows the appropriate interconnects and necessary bandwidth between subsystems to support the various functions of the chip.
  • Each subsystem is connected to its own layer but each layer is not directly connected to each other. Instead, communication between layers is facilitated by peripherals that interface onto multiple subsystem layers.
  • the memory controllers are connected to the PDA and optional multi-media layers. This allows a high degree of concurrency and bandwidth availability since multiple transactions can be occurring simultaneously.
  • a multi-media processor can be transferring data from synchronous memory to an advanced audio Codec while the PDA processor is fetching code from static memory. Neither transfer affects the bandwidth of the other.
  • the multi-layer bus allows the interconnects to be rerouted as needed by the system.
  • the static memory controller can be attached to the PDA processor's bus in one scenario and the multi-media processor's bus in another, depending upon the particular path that data needs to flow on.
  • FIG. 2 illustrates a functional block diagram of the wireless section 12 shown in FIG. 1 .
  • the high speed wireless bus 14 connects to a baseband processor 22 and a general purpose wireless microprocessor 24 .
  • a low speed wireless bus 26 bidirectionally connects to the high speed wireless bus 14 .
  • At least one wireless peripheral 28 bidirectionally connects to the low speed wireless bus 26 .
  • a wireless memory controller 30 bidirectionally communicates with the high speed wireless bus.
  • the baseband processor 22 is preferably a digital signal processor (DSP).
  • DSP digital signal processor
  • a DSP allows for more efficient code.
  • the general purpose wireless microprocessor is preferably a CISC or RISC-based microprocessor.
  • the wireless peripheral 28 communication may include a 3G (UMTS), CDMA-2000, GSM, GPRS, GPS, Bluetooth, 802.11, IS-95, or IS-136.
  • the general purpose wireless microprocessor 24 is responsible for executing the layer 2 and above software for all of the wireless functions, and booting and providing task dispatching to the baseband microprocessor.
  • the baseband processor 22 is responsible for running all of the algorithms necessary to provide a layer 1 cellular solution. Neither processor is programmable by the end-user for security purposes.
  • FIG. 3 illustrates a functional block diagram of the PDA section 16 shown in FIG. 1 .
  • the high speed PDA bus 18 is connected to a multimedia microprocessor 32 and a PDA microprocessor 34 .
  • a low speed PDA bus 36 bidirectionally connects to the high speed PDA bus 18 .
  • At least one PDA peripheral 38 bidirectionally connects to the low speed PDA bus 36 and the DMA controller 40 .
  • a PDA memory controller 42 bidirectionally communicates with the high speed PDA bus 18 .
  • the multimedia microprocessor 32 is preferably a digital signal processor (DSP).
  • DSP digital signal processor
  • the PDA microprocessor 34 is preferably a CISC or RISC-based microprocessor.
  • the PDA peripheral 36 may be any I/O device that can be used on a portable computing device or connected to a serial port, e.g. a Universal Serial Bus, secure data I/O, infra-red, Audio Codec, Touchscreen controller, Digital Camera Interface, a LCD controller, pulse width modulators, or a memory stick.
  • the PDA processor 34 is responsible for running the main operating system and associated user applications, controlling the PDA peripheral blocks, and for providing task dispatching to the multi-media processor and the wireless system.
  • the system includes a high speed multi-media bus 44 and a high speed graphics bus 46 .
  • the high speed PDA bus 18 bidirectionally communicates with the DMA controller 40 , PDA memory controller 42 , PDA processor 34 , and low speed PDA bus 36 .
  • the high speed multi-media bus 44 bidirectionally communicates with the PDA memory controller 42 and multimedia microprocessor 32 within the PDA section.
  • the high speed graphics bus 46 communicates with the LCD controller 48 and the PDA memory controller 42 . Throughout the entire system, it is preferable that the busses be 32 bits wide.
  • the multi-media processor 32 is responsible for running user programmed multi-media related algorithms such as MPEG-3 decoding and performing the voice en/decoding functions required for the cellular portion of the wireless subsystem. This allows some of the functionality to be off-loaded from the other processors in the architecture and increases the amount of the parallel processing power available in the system.
  • FIG. 5 illustrates an alternate embodiment 10 ′ of the general system shown in FIG. 1 .
  • the memory controllers 30 , 42 for the wireless and PDA sections are separate modules on the same substrate.
  • the logic controller 52 logically separates the two memory control sections to prevent inadvertent access of the wireless portion of the memory controller.

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  • Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Transceivers (AREA)
  • Logic Circuits (AREA)
US09/969,941 2001-10-02 2001-10-02 Integrated circuit architecture for programmable wireless device Expired - Lifetime US6931259B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US09/969,941 US6931259B2 (en) 2001-10-02 2001-10-02 Integrated circuit architecture for programmable wireless device
EP02013510A EP1300987B1 (en) 2001-10-02 2002-06-17 An integrated circuit architecture for programmable wireless devices
DE60206000T DE60206000T2 (de) 2001-10-02 2002-06-17 Eine intregrierte Schaltungsarchitektur für programmierbare drahtlose Geräte
JP2002289742A JP4392160B2 (ja) 2001-10-02 2002-10-02 プログラマブルな無線装置用の集積回路構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/969,941 US6931259B2 (en) 2001-10-02 2001-10-02 Integrated circuit architecture for programmable wireless device

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US20030064747A1 US20030064747A1 (en) 2003-04-03
US6931259B2 true US6931259B2 (en) 2005-08-16

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US (1) US6931259B2 (enrdf_load_stackoverflow)
EP (1) EP1300987B1 (enrdf_load_stackoverflow)
JP (1) JP4392160B2 (enrdf_load_stackoverflow)
DE (1) DE60206000T2 (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050212106A1 (en) * 2004-03-24 2005-09-29 Youngwoo Kwon Multilayer integrated circuit for RF communication and method for assembly thereof
US7106339B1 (en) * 2003-04-09 2006-09-12 Intel Corporation System with local unified memory architecture and method

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US7585316B2 (en) * 2004-05-21 2009-09-08 Warsaw Orthopedic, Inc. Interspinous spacer
JP2006157580A (ja) * 2004-11-30 2006-06-15 Ricoh Co Ltd 画像処理装置、画像形成装置、画像処理方法、コンピュータプログラム及び記録媒体
JP4437464B2 (ja) 2005-06-01 2010-03-24 株式会社ルネサステクノロジ 半導体装置及びデータ処理システム
JP4480661B2 (ja) * 2005-10-28 2010-06-16 株式会社ルネサステクノロジ 半導体集積回路装置
US8351855B2 (en) 2010-01-27 2013-01-08 Broadcom Corporation Proximity coupling without Ohmic contact and applications thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5634080A (en) * 1992-06-29 1997-05-27 Elonex Ip Holdings, Ltd. Hand-held portable computer having an electroluminescent flat-panel display with pixel elements at right angles to the plane of the display and an excitation direction parallel to the plane of the display
US5797089A (en) 1995-09-07 1998-08-18 Telefonaktiebolaget Lm Ericsson (Publ) Personal communications terminal having switches which independently energize a mobile telephone and a personal digital assistant
US5943421A (en) 1995-09-11 1999-08-24 Norand Corporation Processor having compression and encryption circuitry
US6334046B1 (en) 1997-12-29 2001-12-25 Telefonaktiebolaget Lm Ericsson (Publ) Information management system
US6424369B1 (en) * 1997-10-06 2002-07-23 Edwin L. Adair Hand-held computers incorporating reduced area imaging devices
US6455915B1 (en) * 2000-05-30 2002-09-24 Programmable Silicon Solutions Integrated inductive circuits

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5634080A (en) * 1992-06-29 1997-05-27 Elonex Ip Holdings, Ltd. Hand-held portable computer having an electroluminescent flat-panel display with pixel elements at right angles to the plane of the display and an excitation direction parallel to the plane of the display
US5797089A (en) 1995-09-07 1998-08-18 Telefonaktiebolaget Lm Ericsson (Publ) Personal communications terminal having switches which independently energize a mobile telephone and a personal digital assistant
US5943421A (en) 1995-09-11 1999-08-24 Norand Corporation Processor having compression and encryption circuitry
US6424369B1 (en) * 1997-10-06 2002-07-23 Edwin L. Adair Hand-held computers incorporating reduced area imaging devices
US6334046B1 (en) 1997-12-29 2001-12-25 Telefonaktiebolaget Lm Ericsson (Publ) Information management system
US6455915B1 (en) * 2000-05-30 2002-09-24 Programmable Silicon Solutions Integrated inductive circuits

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7106339B1 (en) * 2003-04-09 2006-09-12 Intel Corporation System with local unified memory architecture and method
US20050212106A1 (en) * 2004-03-24 2005-09-29 Youngwoo Kwon Multilayer integrated circuit for RF communication and method for assembly thereof
US20050212078A1 (en) * 2004-03-24 2005-09-29 Youngwoo Kwon Integrated circuit module package and assembly method thereof
US7132747B2 (en) * 2004-03-24 2006-11-07 Youngwoo Kwon Multilayer integrated circuit for RF communication and method for assembly thereof
US20070170583A1 (en) * 2004-03-24 2007-07-26 Youngwoo Kwon Multilayer integrated circuit for RF communication and method for assembly thereof
US7638364B2 (en) 2004-03-24 2009-12-29 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Multilayer integrated circuit for RF communication and method for assembly thereof
US8067824B2 (en) 2004-03-24 2011-11-29 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Integrated circuit module package and assembly method thereof

Also Published As

Publication number Publication date
EP1300987A2 (en) 2003-04-09
DE60206000D1 (de) 2005-10-13
EP1300987B1 (en) 2005-09-07
DE60206000T2 (de) 2006-06-29
EP1300987A3 (en) 2004-03-17
US20030064747A1 (en) 2003-04-03
JP2003244009A (ja) 2003-08-29
JP4392160B2 (ja) 2009-12-24

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