US6852617B2 - Semiconductor device fabrication method - Google Patents
Semiconductor device fabrication method Download PDFInfo
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- US6852617B2 US6852617B2 US10/771,393 US77139304A US6852617B2 US 6852617 B2 US6852617 B2 US 6852617B2 US 77139304 A US77139304 A US 77139304A US 6852617 B2 US6852617 B2 US 6852617B2
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Definitions
- the present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a semiconductor device that affords a highly reliable connection to an external substrate.
- CSP Chip Size Package
- WCSP Wafer Level Chip Size Package
- electrodes are formed on a semiconductor chip on which an integrated circuit is already formed.
- An insulation film is formed on the semiconductor chip so that the top faces (upper surfaces) of the electrodes are exposed.
- the insulation film has a plurality of openings and the top faces of the electrodes are exposed by these openings.
- Wiring and terminals known as posts are formed on the insulation film. Normally, this wiring is known as rewiring or relocated wiring, and one end of the wiring is connected to the electrodes via the openings in the insulation film, while the other end is connected to the posts.
- the top side of the semiconductor device is sealed by means of a sealing material such as resin so that the top faces of the posts are exposed, and an external terminal such as a solder ball is formed on the top face of each of the exposed posts.
- This WCSP structure packaging is undertaken in a wafer state. Wafers are cut and divided up after being sealed, whereby many CSP-structure semiconductor chips are produced.
- each external terminal can be dispersed at the side and top face of the associated post, whereby the possibility of a concentration of stress at the join between the top face of the post and the associated external terminal can be reduced-and hence the reliability of the connection between the semiconductor device and the external substrate can be raised.
- An object of the present invention is to provide a semiconductor device fabrication method that makes it possible to form an external terminal on the side and top face of each post without carrying out a step of removing the sealing layer by means of a laser.
- a semiconductor device fabrication method that includes preparing a semiconductor substrate having a plurality of terminals formed on a main surface of the semiconductor substrate, and forming a first metal electrode on a side face of each terminal.
- the fabrication method also includes forming a sealing layer on the main surface of the semiconductor substrate so as to cover the terminals and the first metal electrodes.
- the fabrication method also includes exposing a top face of each terminal and a top face of each first metal electrode by polishing a surface of the sealing layer.
- the fabrication method also includes forming a second metal electrode on the exposed top face of each terminal and on the exposed top face of each first metal electrode.
- the fabrication method also includes producing an “alloy” of each first metal electrode and associated second metal electrode by heating the first and second metal electrodes. This “alloy” becomes an external terminal.
- the external terminal can be formed on the side and top faces of each post within a short time, and the reliability of the connection between the semiconductor device and the external substrate is increased.
- a semiconductor device fabrication method that includes preparing a semiconductor substrate having a plurality of terminals formed on a main surface of the semiconductor substrate, and covering a side face of each terminal with a dummy layer.
- the fabrication method also includes forming a sealing layer on the main surface of the semiconductor substrate so as to cover the terminals and the dummy layers.
- the fabrication method also includes exposing a top face of each terminal and a top face of each dummy layer by polishing a surface of the sealing layer.
- the fabrication method also includes exposing the side face of each terminal by removing the dummy layer.
- the fabrication method also includes forming a conductor on the exposed surface of each terminal. The conductor is used as an external terminal.
- Provision of the external terminal on the side and top faces of the post i.e., terminal
- Provision of the external terminal on the side and top faces of the post can be implemented within a short time, and the reliability of the connection between the semiconductor device and the external substrate is increased.
- FIG. 1 is a cross-sectional view showing the step of preparing a semiconductor substrate on which a plurality of terminals is formed, according to a first embodiment of the present invention
- FIG. 2 is a cross-sectional view that shows the step of forming a first metal electrode on each terminal, according to the first embodiment
- FIG. 3 is a cross-sectional view that shows the step of immersing the terminals in a molten metal bath, according to the first embodiment
- FIG. 4 is a cross-sectional view that shows the step of forming a sealing layer on the main surface of the semiconductor substrate, according to the first embodiment
- FIG. 5 is a cross-sectional view that shows the step of exposing the terminals and the first metal electrodes by polishing the surface of the sealing layer, according to the first embodiment
- FIG. 6 is a cross-sectional view that shows the step of forming a second metal electrode on each first metal electrode and on each terminal, according to the first embodiment
- FIG. 7 is a cross-sectional view that shows the step of forming a dummy layer on each terminal, according to a second embodiment of the present invention.
- FIG. 8 is a cross-sectional view that shows the step of immersing the terminals in a resin bath, according to the second embodiment
- FIG. 9 is a cross-sectional view that shows the step of forming a sealing layer on the main surface of the semiconductor substrate, according to the second embodiment.
- FIG. 10 is a cross-sectional view that shows the step of exposing the terminals and the dummy layers by polishing the surface of the sealing layer, according to the second embodiment
- FIG. 11 is a cross-sectional view that shows the step of removing the dummy layers, according to the second embodiment
- FIG. 12 is a cross-sectional view that shows the step of forming an external terminal on each of the terminals, according to the second embodiment
- FIG. 13 is a cross-sectional view that shows the step of forming a first insulation film on the main surface of the semiconductor substrate, according to a third embodiment of the present invention.
- FIG. 14 is a cross-sectional view that shows the step of immersing the terminals in a metal bath or a resin bath, according to the third embodiment
- FIG. 15 is a cross-sectional view that shows the step of forming the first metal electrodes or the dummy layers on the terminals, according to the third embodiment.
- FIG. 16 is a cross-sectional view that shows the step of laminating sealing layers, according to a modified third embodiment.
- FIGS. 1 to 6 illustrate the semiconductor device fabrication method according to the first embodiment of the present invention.
- terminal group 200 is formed on the main surface of a semiconductor substrate 100 .
- the semiconductor substrate 100 is a substrate that includes a semiconductor wafer 110 , electrodes 120 , an insulation film 130 , and wiring 140 formed on the main surface of the semiconductor wafer 110 .
- the electrodes 120 made of Al (aluminum) or the like are formed on the semiconductor wafer 110 made of Si (silicon) or the like.
- the semiconductor wafer 110 has an integrated circuit (not shown) formed on the main surface thereof.
- the electrodes 120 are electrically connected to the integrated circuit.
- a protective film 131 such as a nitride film (SiN (silicon nitride) film, for example) is formed on the semiconductor wafer 110 such that the top face of each electrode 120 is exposed.
- the insulation film 130 made from polyimide or the like is formed on the protective film 131 such that the top face of each electrode 120 is still exposed.
- the protective film 131 is formed with a thickness of approximately 1 ⁇ m by means of CVD (Chemical Vapor Deposition) or similar.
- the source gases for the CVD are silane and ammonia, for example.
- the insulation film 130 is formed with a thickness of approximately 2 to 10 ⁇ m by spin coating and heat-processing a varnish that is produced by dissolving polyimide or a precursor thereof in a solvent, for example.
- the wiring 140 made of Cu (copper) or similar and the terminals 200 known as “posts” and made of Cu or the like are formed on the insulation film 130 .
- the wiring 140 is formed by metal vapor deposition through sputtering, photolithography, plating, or other methods.
- the terminals 200 are provided by forming a resist layer up to the height of the terminals 200 and then performing photolithography, plating or other methods.
- the terminal group 200 electrically connects the wiring 140 to the external terminals that are connected to an external substrate and so forth.
- Each terminal 200 includes a first face 210 that is in contact with the main surface of the semiconductor substrate 100 , an opposite face (second face) 220 that is parallel to the first face 210 , and a side face (lateral wall) 230 extending between the first face 210 and the second face 220 .
- the interval between each tow adjacent terminals 200 is approximately 150 ⁇ m to 400 ⁇ m, and the height of the terminal 200 is approximately 100 ⁇ m.
- the terminal 200 has a cylindrical shape and the diameter of the terminal 200 is approximately 150 ⁇ m to 400 ⁇ m.
- One end of the wiring 140 is connected to the electrodes 120 , while the other end of the wiring 140 is connected to the terminals 200 .
- the point at which the semiconductor device is electrically connected to the external substrate or similar can be set in an arbitrary position because the wiring 140 is provided in this embodiment.
- this arbitrary placement of the connecting point between the semiconductor device and external substrate is known as relocation, and hence the wiring 140 is called the relocation wiring or rewiring.
- a metal electrode 310 that is made of solder or similar is formed on the side face 230 of each terminal 200 as shown in FIG. 2 .
- the metal electrode 310 is formed so as to surround the side 230 of each of the terminals 200 by immersing the terminals 200 in a molten metal bath 400 that contains a molten metal 410 such as molten solder.
- the adjacent metal electrodes 310 that are formed on the adjacent terminals 200 are spaced apart at a predetermined interval.
- the film thickness t of the metal electrode 310 is preferably at least 10 ⁇ m in order to obtain sufficient strength with respect to the supposed external stress.
- the film thickness t of the metal electrode 310 can be controlled to a desired value by adjusting the time interval during which the terminals 200 are immersed in the molten metal bath 400 , the temperature of the molten metal 410 , and/or other factors.
- the main surface of the semiconductor substrate 100 and the liquid surface 411 of the molten metal 410 face each other and are parallel to each other. It should be noted that when the terminals 200 are immersed in the metal bath 400 , the metal 410 may stick to the second faces 220 of the terminals 200 .
- the metal electrodes 310 can be simultaneously formed over the respective terminals 200 provided on the semiconductor substrate 100 , and the metal electrodes 310 can be formed on the terminals 200 without a marked increase in the manufacturing steps.
- the terminals 200 are immersed in the metal bath 400 such that the main surface of the semiconductor substrate 100 and the liquid surface 411 of the molten metal 410 are spaced apart at a predetermined interval.
- the possibility that the molten metal 410 will stick to the wiring 140 formed on the semiconductor substrate 100 can be diminished.
- the adhesion of the metal electrodes 310 with a sealing layer 600 that is formed so as to cover the terminals 200 in a subsequent step is lower than the adhesion of the terminals 200 with the sealing layer 600 (e.g., when the material of the metal electrodes 310 is solder and the material of the terminals 200 is Cu), the sides 230 of the terminals 200 must be exposed over a predetermined range in order to increase the adhesion with the sealing layer 600 . For this reason, when the terminals 200 are immersed in the metal bath 400 , the main surface of the semiconductor substrate 100 and the liquid surface of the molten metal 410 are preferably at least 20 ⁇ m apart.
- the sealing layer 600 that is made of epoxy resin or the like is formed on the main surface of the semiconductor substrate 100 such that the terminals 200 and the metal electrodes 310 are covered by the sealing layer 600 , as shown in FIG. 4 .
- the main surface of the semiconductor substrate 100 and the sides of the terminals 200 can be protected from moisture and so forth.
- the sealing layer 600 is formed by supplying resin to the semiconductor substrate 100 that is disposed in a mold and then applying pressure. At such time, because the semiconductor substrate 100 is disposed such that the top faces of the terminals 200 (i.e., the second faces 220 ) are spaced apart from the mold, the resin is also supplied between the second faces 220 and the mold, and the sealing layer 600 is formed so as to cover the second faces 220 .
- the terminals 200 and the mold are not in contact with one another, so that the possibility that the terminals 200 are damaged as a result of the terminals 200 being pressed by the mold is reduced.
- an oxide film is formed on the surfaces of the terminals 200 made of Cu before the sealing layer 600 is formed.
- the oxide film is a copper oxide film, for example, and is formed by subjecting the terminals 200 to a heat treatment in air or in an oxygen atmosphere.
- the adhesion between the terminals 200 and the sealing layer 600 can be enhanced.
- This enhancement primarily relies upon the hydrogen bond between the oxide film and the resin.
- the top faces of the terminals 200 and the top faces of the metal electrodes 310 are exposed by polishing the surface of the sealing layer 600 .
- the top face of the semiconductor device is made smooth and the respective height of the terminals 200 is afforded a predetermined value.
- the top faces of the terminals 200 , the top faces of the metal electrodes 310 and the top face of the sealing layer 600 become substantially planar with each other as a result of this polishing.
- the height d of the polished terminal 200 is preferably at least 40 ⁇ m in order to alleviate the influences of the stress that is generated as a result of the difference between the thermal expansion rate of the semiconductor substrate 100 and the thermal expansion rate of the external substrate.
- the height h of the metal electrode 310 is preferably at least 10 ⁇ m in order to obtain sufficient strength with respect to the supposed external stress.
- the terminals 200 are preferably immersed to a depth, which is incremented by an additional amount, in the above-mentioned step of immersing the terminals 200 in the metal bath 400 .
- the “additional amount” is added because each metal electrode 310 is made shorter by the smoothing polishing process. Therefore, the terminals 200 are preferably immersed to a depth of at least 10 ⁇ m plus some additional distance.
- a metal electrode 320 made of solder or the like is formed on the top face of each terminal 200 and the top face of the associated metal electrode 310 which are exposed by polishing.
- An “alloy” of the metal electrode 310 and the metal electrode 320 is produced by heating these electrodes 310 and 320 .
- “alloy” denotes a state where the metal electrode 310 and the metal electrode 320 are melted by means of a heat treatment so as to blend with each other.
- the metal electrode 310 and the metal electrode 320 are integrated by being melted.
- the metal electrode 310 and metal electrode 320 may be made of the same or a different material, as long as the materials can be integrated by being melted by means of a heat treatment.
- the present embodiment can be implemented without performing a new, additional heating step.
- an external terminal 300 that links and covers the top face and side of the terminal 200 is formed.
- each external terminal 300 is dispersed, not only to the join between the top face of the terminal 200 and the associated external terminal 300 , but also to the join between the side 230 of the terminal 200 and the associated external terminal 300 . Therefore, the possibility of a concentration of stress at the join between the top face of the terminal 200 and the external terminal 300 and hence the occurrence of cracks and so forth is reduced, and the reliability of the connection between the semiconductor device and external substrate can be increased.
- the external terminal 300 is formed so as to cover the side 230 of the terminal 200 , and the external terminal 300 is suspended on the terminal 200 when the stress acts in the transverse direction of the semiconductor device.
- the semiconductor device is mounted in a portable device such as a cellular phone, large stress often acts from the transverse direction of the semiconductor device due to the collisions and vibrations that occur when the portable device is carried around.
- the present embodiment can improve the reliability of the connection between the semiconductor device and the external substrate and consequently improve the reliability of the semiconductor device.
- the material of the metal electrode 310 is solder and the material of the metal electrode 320 is also solder, and the metal electrode 310 and metal electrode 320 melt and are joined as a result of the heat produced when the metal electrode 320 is mounted on the terminal 200 .
- the temperature of the heat applied at this time is about 210 to 260° C.
- the external terminal 300 made of solder (i.e., the solder ball) that connects the associated terminal 200 and the external substrate, is formed so as to cover the top face and side of the associated terminal 200 .
- the sealed semiconductor substrate 100 is cut by means of a diamond blade or the like to render separate semiconductor chips.
- the metal electrode 310 constituting part of the external terminal 300 is formed on the side 230 of each terminal 200 before the sealing layer 600 is formed.
- the step in which the side 230 of each terminal 200 is exposed via the sealing layer by removing part of the sealing layer 600 by means of a laser in order to form the external terminal 300 on the side 230 of the terminal 200 is not performed.
- the external terminal 300 can be formed on the top face and the side 230 of each terminal 200 in this embodiment, and therefore the production efficiency can be raised by shortening the package fabrication time in this embodiment.
- FIGS. 7 to 12 are a series of cross-sectional views that illustrate the semiconductor device fabrication method according to the second embodiment of the present invention.
- the semiconductor device fabrication method of this embodiment involves, first, forming a dummy layer 700 made of a resin or the like on the side 230 of each of the terminals 200 that are formed on the semiconductor substrate 100 .
- the dummy layer 700 controls the sealing of the side 230 of the terminal 200 by the sealing layer 600 .
- the dummy layer 700 is resistant to the heat of the sealing step and is soluble in organic solvents, alkaline solvents or the like.
- a photoresist or similar can be used as the material of the dummy layer 700 .
- polyimide or similar can be used as the material of the dummy layer 700 .
- the dummy layer 700 is formed so as to surround the side (lateral wall) 230 of the terminal 200 .
- the adjacent dummy layers 700 formed on the adjacent terminals 200 are spaced apart at predetermined intervals.
- the dummy layers 700 are formed by immersing the terminals 200 in a resin bath 800 that contains a molten resin 810 .
- the dummy layer 700 is formed with a film thickness that is at least 10 ⁇ m.
- the film thickness of the dummy layer 700 can be controlled by adjusting the viscosity of the molten resin 810 .
- the main surface of the semiconductor substrate 100 and the liquid surface 811 of the molten resin 810 face each other and are parallel to each other.
- the dummy layers 700 can be simultaneously created on the terminals 200 formed on the semiconductor substrate 100 .
- the dummy layers 700 can be formed on the terminals 200 without significantly increasing the manufacturing steps.
- the terminals 200 are immersed in the resin bath 800 such that the main surface of the semiconductor substrate 100 is spaced from the liquid surface 811 of the molten resin 810 at a predetermined interval.
- the main surface of the semiconductor substrate 100 and the liquid surface 811 are preferably spaced apart by at least 20 ⁇ m.
- the terminals 200 are lifted up from the resin bath 800 and the dummy layers 700 formed on the sides 230 of the terminals 200 are cured by means of a heat treatment.
- the sealing layer 600 that is made of an epoxy resin or the like is formed on the main surface of the semiconductor substrate 100 so as to cover the terminals 200 and the dummy layers 700 .
- the top faces of the terminals 200 and the top faces of the dummy layers 700 are exposed by polishing the surface of the sealing layer 600 .
- each polished terminal 200 is preferably at least 40 ⁇ m in order to reduce the effects of the stress generated as a result of the difference between the thermal expansion rate of the semiconductor substrate 100 and the thermal expansion rate of the external substrate.
- the dummy layer 700 is formed so that the height h′ of the dummy layer 700 is at least 10 ⁇ m.
- FIG. 11 is an enlarged cross-sectional view of one of the terminals 200 .
- the dummy layers 700 are removed by supplying a chemical 710 , such as an organic solvent or alkaline solvent, to the dummy layers 700 to dissolve the dummy layers 700 .
- a chemical 710 such as an organic solvent or alkaline solvent
- the supplying of the chemical 710 is performed by applying the chemical 710 to the main surface of the semiconductor device, that is, to the top face of the sealing layer 600 exposed by polishing and to the top faces of the dummy layers 700 .
- the sealing layer 600 is an epoxy resin that does not easily dissolve in an organic solvent or an alkaline solvent or the like, and hence the possibility of the sealing layer 600 being dissolved by the chemical 710 is low.
- the respective sides of the terminals 200 can be simultaneously exposed, simply by means of the step of applying the chemical 710 to the main surface of the semiconductor device.
- the external terminal 300 which is made of a conductor, is formed on the surface of the each exposed terminal 200 , that is, on the top face and side 230 of the terminal 200 .
- a solder ball is used for the external terminal 300 .
- the external terminal 300 is formed so as to connect and cover the top face and the side 230 of the associated terminal 200 .
- the stress acting on the external terminal 300 is dispersed not only to the join between the top face of the associated terminal 200 and the external terminal 300 , but also to the join between the side 230 of that terminal 200 and the external terminal 300 . Therefore, the possibility of a concentration of stress at the join between the top face of the terminal 200 and associated external terminal 300 and the occurrence of cracks and so forth at this join is reduced. Hence, the reliability of the connection between the semiconductor device and the external substrate can be increased.
- connection reliability i.e., strength
- the connection reliability is greatly improved when the stress from the transverse direction of the semiconductor device is concerned.
- the external terminal 300 is formed so as to cover the side 230 of the associated terminal 200 , and the external terminal 300 is suspended on the associated terminal 200 when the stress acts in the transverse direction of the semiconductor device.
- a semiconductor device is mounted in a portable device such as a cellular phone, stress often acts from the transverse direction of the semiconductor device due to the collisions and vibrations that occur when the portable device is carried around.
- the present embodiment can improve the reliability of the connection between the semiconductor device and the external substrate, and improve the reliability of the semiconductor device.
- the dummy layers 700 are formed so as to cover the sides 230 of the terminals 200 before the sealing layer 600 is formed, and the sides 230 of the terminals 200 are exposed by removing the dummy layers 700 after the sealing layer 600 is formed.
- the step in which the sides 230 of the terminals 200 are exposed via the sealing layer by removing part of the sealing layer 600 by means of a laser is not performed. Without such step, the external terminal 300 can be formed on the top face and the side 230 of each terminal 200 in this embodiment. Thus, the production efficiency can be raised by shortening the package fabrication time.
- the third embodiment is a modification to the semiconductor device fabrication methods of the first and second embodiments. Specifically, the third embodiment provides preferred control on the interval between the metal electrode 310 or dummy layer 700 , and the main surface of the semiconductor substrate 100 .
- FIGS. 13 to 15 are a series of cross-sectional views to explain how a semiconductor device is fabricated in this embodiment.
- an insulation film 500 such as a solder resist is first formed by means of spin coating or a high accuracy printing method or similar on the main surface of the semiconductor substrate 100 such that the terminals 200 are exposed at a predetermined height.
- the terminals 200 are immersed in the molten metal bath 400 or the molten resin bath 800 .
- the whole surface of the terminals 200 is immersed in the metal bath 400 or the resin bath 800 .
- the metal electrodes 310 or dummy layers 700 are respectively formed on the sides 230 of the terminals 200 exposed via the insulation film 500 .
- the terminals 200 When the terminals 200 are immersed in the metal bath 400 or in the resin bath 800 , the main surface of the semiconductor substrate 100 is protected by the insulation film 500 . There is therefore a reduced possibility of the molten metal 410 or resin 810 sticking to the main surface of the semiconductor substrate 100 .
- the interval between the main surface of the semiconductor substrate 100 , and the metal electrode 310 or dummy layer 700 formed on the terminal 200 can be set at a desired distance by controlling the thickness of the insulation film 500 .
- the interval between the main surface of the semiconductor substrate 100 , and the metal electrode 310 or dummy layer 700 is preferably 20 ⁇ m or more. Therefore, the insulation film 500 is formed with a film thickness at least 20 ⁇ m in the third embodiment.
- the insulation film 500 is removed and the sealing layer 600 is formed on the main surface of the semiconductor substrate 100 .
- a sealing layer 601 that is made of resin or similar may be used for the insulation film 500 in the third embodiment.
- the sealing layer 601 is not removed. Rather, as shown in FIG. 16 , a sealing layer 600 ′ is formed on the top face of the sealing layer 601 .
- the material of the sealing layer 601 is a low elasticity resin (polyimide, for example) with a flexural modulus E of 0.5 to 4 GPa at normal temperature
- the material of the sealing layer 600 ′ is a high elasticity resin (epoxy resin, for example) with a flexural modulus E of about 9 to 21 GPa at normal temperature.
- the stresses acting on the terminals 200 can be more suitably absorbed by the sealing layer 601 and the sealing layer 600 ′.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (26)
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JP2003-158380 | 2003-03-06 | ||
JP2003158380A JP3721175B2 (en) | 2003-06-03 | 2003-06-03 | Manufacturing method of semiconductor device |
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US20040175914A1 US20040175914A1 (en) | 2004-09-09 |
US6852617B2 true US6852617B2 (en) | 2005-02-08 |
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US7468545B2 (en) * | 2005-05-06 | 2008-12-23 | Megica Corporation | Post passivation structure for a semiconductor device and packaging process for same |
US7582556B2 (en) | 2005-06-24 | 2009-09-01 | Megica Corporation | Circuitry component and method for forming the same |
JP2007214502A (en) * | 2006-02-13 | 2007-08-23 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
JP4121543B1 (en) | 2007-06-18 | 2008-07-23 | 新光電気工業株式会社 | Electronic equipment |
DE102008054054A1 (en) * | 2008-10-31 | 2010-05-12 | Advanced Micro Devices, Inc., Sunnyvale | Semiconductor device having a structure for reduced strain of metal columns |
WO2010049087A2 (en) * | 2008-10-31 | 2010-05-06 | Advanced Micro Devices, Inc. | A semiconductor device including a reduced stress configuration for metal pillars |
US9196559B2 (en) * | 2013-03-08 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Directly sawing wafers covered with liquid molding compound |
WO2023100517A1 (en) * | 2021-12-01 | 2023-06-08 | 株式会社村田製作所 | Circuit module |
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US5895231A (en) * | 1996-10-29 | 1999-04-20 | Lg Semicon Co., Ltd. | External terminal fabrication method for semiconductor device package |
JP2000353766A (en) | 1999-04-06 | 2000-12-19 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
US20010008309A1 (en) * | 2000-01-13 | 2001-07-19 | Takahiro Iijima | Interconnection substrate having metal columns covered by a resin film, and manufacturing method thereof |
US6329251B1 (en) * | 2000-08-10 | 2001-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd | Microelectronic fabrication method employing self-aligned selectively deposited silicon layer |
US6501169B1 (en) * | 1999-11-29 | 2002-12-31 | Casio Computer Co., Ltd. | Semiconductor device which prevents leakage of noise generated in a circuit element forming area and which shields against external electromagnetic noise |
US20030096495A1 (en) * | 1999-01-27 | 2003-05-22 | Shinko Electric Industries Co., Ltd. | Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device |
US6770971B2 (en) * | 2002-06-14 | 2004-08-03 | Casio Computer Co., Ltd. | Semiconductor device and method of fabricating the same |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4526651B2 (en) * | 1999-08-12 | 2010-08-18 | 富士通セミコンダクター株式会社 | Semiconductor device |
JP2002134545A (en) * | 2000-10-26 | 2002-05-10 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit chip, board and their manufacturing method |
-
2003
- 2003-06-03 JP JP2003158380A patent/JP3721175B2/en not_active Expired - Lifetime
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2004
- 2004-02-05 US US10/771,393 patent/US6852617B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5895231A (en) * | 1996-10-29 | 1999-04-20 | Lg Semicon Co., Ltd. | External terminal fabrication method for semiconductor device package |
US20030096495A1 (en) * | 1999-01-27 | 2003-05-22 | Shinko Electric Industries Co., Ltd. | Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device |
JP2000353766A (en) | 1999-04-06 | 2000-12-19 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
US6501169B1 (en) * | 1999-11-29 | 2002-12-31 | Casio Computer Co., Ltd. | Semiconductor device which prevents leakage of noise generated in a circuit element forming area and which shields against external electromagnetic noise |
US20010008309A1 (en) * | 2000-01-13 | 2001-07-19 | Takahiro Iijima | Interconnection substrate having metal columns covered by a resin film, and manufacturing method thereof |
US6329251B1 (en) * | 2000-08-10 | 2001-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd | Microelectronic fabrication method employing self-aligned selectively deposited silicon layer |
US6770971B2 (en) * | 2002-06-14 | 2004-08-03 | Casio Computer Co., Ltd. | Semiconductor device and method of fabricating the same |
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US20040175914A1 (en) | 2004-09-09 |
JP3721175B2 (en) | 2005-11-30 |
JP2004363250A (en) | 2004-12-24 |
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