JP2007214502A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2007214502A
JP2007214502A JP2006035320A JP2006035320A JP2007214502A JP 2007214502 A JP2007214502 A JP 2007214502A JP 2006035320 A JP2006035320 A JP 2006035320A JP 2006035320 A JP2006035320 A JP 2006035320A JP 2007214502 A JP2007214502 A JP 2007214502A
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semiconductor wafer
semiconductor
back surface
grinding
wafer
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Yasuo Tanaka
康雄 田中
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Priority to JP2006035320A priority Critical patent/JP2007214502A/en
Priority to US11/643,712 priority patent/US20070190908A1/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for inhibiting warping of a semiconductor wafer, in a process for grinding a rear surface of the semiconductor wafer in a manufacturing method for a semiconductor device. <P>SOLUTION: The manufacturing method for a semiconductor device comprises a process for grinding the rear surface of the semiconductor wafer wherein a sealing layer is formed on a circuit-forming surface side of the semiconductor substrate. When the rear surface of the semiconductor wafer is ground, the diameter of the semiconductor wafer is sucked on the circuit-forming surface side in its range of 99-100.5%. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、複数の回路素子を半導体ウェハの状態で形成し、最後に個片分割して形成するＷＣＳＰ（Ｗａｆｅｒ ｌｅｖｅｌ Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）型等の小型の半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a small-sized semiconductor device such as a WCSP (Wafer Level Chip Size Package) type in which a plurality of circuit elements are formed in the state of a semiconductor wafer and finally divided into individual pieces.

近年、電子機器に対する小型化や薄型化の要求が高まってきており、その配線基板に搭載されるコンデンサや抵抗等の受動部品の厚さが２００μｍ程度にまで薄型化されるに伴い、能動部品として機能するメモリやＣＰＵ等の半導体装置を同等の厚さに薄型化することに対する期待が高まってきている。
一般に、ＷＣＳＰ型の半導体装置は、シリコン等からなる半導体基板の回路形成面側を樹脂からなる封止層で封止した構造が用いられるが、物性値（主に熱膨張係数）が異なる異種材料が張り合わされた状態であるので半導体基板側が凸面となる反りが生じやすく、半導体ウェハの半導体基板の裏面を研削して半導体ウェハを薄くすると反りが更に大きくなって製造が困難になるという問題がある。 In recent years, there has been an increasing demand for miniaturization and thinning of electronic devices. As the thickness of passive components such as capacitors and resistors mounted on the wiring board has been reduced to about 200 μm, as active components. There is an increasing expectation for reducing the thickness of a functioning semiconductor device such as a memory or CPU to an equivalent thickness.
In general, a WCSP type semiconductor device has a structure in which a circuit forming surface side of a semiconductor substrate made of silicon or the like is sealed with a sealing layer made of resin, but different materials having different physical property values (mainly thermal expansion coefficients). Since the semiconductor substrate side is in a state of being bonded together, there is a problem that warpage in which the semiconductor substrate side becomes a convex surface is likely to occur, and if the semiconductor wafer is ground and the semiconductor wafer is thinned to make the semiconductor wafer thinner, the warpage becomes larger and manufacturing becomes difficult. .

半導体装置の薄型化のための半導体ウェハの裏面の研削工程において、半導体ウェハの回路形成面に保護テープを貼付し、裏面研削装置の吸着ステージに保護テープを介して半導体ウェハを固定し、裏面研削後に保護テープを貼付したまま次工程に搬送して、半導体ウェハの反りを矯正しながら半導体装置を製造しているものがある（例えば、特許文献１参照。）。   In the grinding process of the backside of the semiconductor wafer for thinning the semiconductor device, a protective tape is applied to the circuit forming surface of the semiconductor wafer, the semiconductor wafer is fixed to the suction stage of the backside grinding device via the protective tape, and the backside grinding is performed. Some semiconductor devices are manufactured while being transferred to the next process with a protective tape attached, and correcting the warpage of the semiconductor wafer (see, for example, Patent Document 1).

また、半導体ウェハの裏面の研削工程において、半導体ウェハの回路形成面に保護テープを貼付し、粗研削装置の吸着ステージに保護テープを介して半導体ウェハを真空吸着により固定し、裏面の粗研削後に吸着ステージ上に真空吸着された半導体ウェハを半導体ウェハの外形と同じ大きさの吸着パッドに吸着保持し、その後に吸着ステージによる吸着を解除して仕上げ研削装置へ搬送し、仕上げ研削装置の吸着ステージに半導体ウェハの平坦性を保ったまま吸着させ、仕上げ研削後の半導体ウェハの反りの減少を図っているものもある（例えば、特許文献２参照。）。
特開２００４−２５９７１３号公報（第８頁段落００３３−第９頁段落００３８） 特開平８−３３９９８３号公報（第３頁段落００１７−段落００２２、第２図） Also, in the grinding process of the back surface of the semiconductor wafer, a protective tape is applied to the circuit forming surface of the semiconductor wafer, and the semiconductor wafer is fixed to the suction stage of the rough grinding device by vacuum suction, and after the rough grinding of the back surface The semiconductor wafer vacuum-sucked on the suction stage is sucked and held on a suction pad that is the same size as the outer shape of the semiconductor wafer, and then the suction by the suction stage is released and transported to the finish grinding machine. Some semiconductor wafers are attracted while maintaining the flatness of the semiconductor wafer to reduce the warpage of the semiconductor wafer after finish grinding (see, for example, Patent Document 2).
JP 2004-259713 A (paragraph 0033 on page 8, paragraph 0038 on page 9) JP-A-8-339983 (page 3, paragraph 0017-paragraph 0022, FIG. 2)

上述した特許文献１および特許文献２の技術は、封止層が形成されていない半導体ウェハの反りを矯正しながら半導体ウェハの裏面を研削して薄型化された半導体装置を製造する技術である。
しかしながら、異種材料を張り合わせて形成された半導体ウェハの反りは、上記のように主にシリコン等の半導体基板と樹脂からなる封止層の熱膨張差に起因して生ずるものであるので、反りを矯正する手段を解除した後は、半導体ウェハに過大な反りが残留する虞があるという問題がある。 The techniques of Patent Document 1 and Patent Document 2 described above are techniques for manufacturing a thinned semiconductor device by grinding the back surface of a semiconductor wafer while correcting warpage of the semiconductor wafer on which a sealing layer is not formed.
However, the warpage of the semiconductor wafer formed by bonding different materials is mainly caused by the difference in thermal expansion between the semiconductor substrate such as silicon and the sealing layer made of resin as described above. After releasing the correcting means, there is a problem that excessive warpage may remain in the semiconductor wafer.

このため、発明者は、半導体ウェハの裏面の研削工程における研削条件等に着目し、半導体ウェハの反りを抑制する手段を実験的に研究した結果、以下に示す知見を得た。
１）半導体ウェハの反りは、半導体ウェハの周縁部に欠け、例えば１００μｍを超える欠けが多数生じると、その欠けによる凹凸が半導体ウェハの周縁部の反りに対する拘束力を弱め、反りが助長される。 For this reason, the inventor paid attention to grinding conditions in the grinding process of the back surface of the semiconductor wafer and experimentally studied means for suppressing warpage of the semiconductor wafer, and as a result, obtained the following knowledge.
1) The warpage of the semiconductor wafer is chipped at the peripheral portion of the semiconductor wafer, for example, when a large number of chips exceeding 100 μm are generated, the unevenness caused by the chip weakens the restraining force against the warpage of the peripheral portion of the semiconductor wafer, and the warpage is promoted.

２）半導体ウェハの反りは、半導体ウェハの裏面の研削後の面粗度に依存し、粗度が粗いと、それによる凹凸が半導体ウェハの裏面の反りに対する拘束力を弱め、反りが助長される。
３）半導体ウェハの反りは、半導体ウェハに張り合わせる封止層の常温における曲げ弾性率に依存し、半導体基板の厚さに関わらず、その適値が存在する。 2) The warpage of the semiconductor wafer depends on the surface roughness after grinding of the back surface of the semiconductor wafer. If the roughness is rough, the unevenness weakens the restraining force against the warpage of the back surface of the semiconductor wafer, and the warpage is promoted. .
3) The warp of the semiconductor wafer depends on the bending elastic modulus of the sealing layer bonded to the semiconductor wafer at room temperature, and there is an appropriate value regardless of the thickness of the semiconductor substrate.

本発明は、上記の知見に基づいてなされたもので、半導体装置の製造方法における半導体ウェハの裏面研削工程において、半導体ウェハの反りを抑制する手段を提供することを目的とする。   The present invention has been made based on the above knowledge, and an object of the present invention is to provide means for suppressing warpage of a semiconductor wafer in a back grinding process of the semiconductor wafer in a method for manufacturing a semiconductor device.

本発明は、上記課題を解決するために、半導体基板の回路形成面側に封止層を形成した半導体ウェハの裏面を研削する工程を含む半導体装置の製造方法であって、前記半導体ウェハの裏面を研削するときに、前記回路形成面側の、前記半導体ウェハの直径の９９％以上、１００．５％以下の範囲を吸着することを特徴とする。   In order to solve the above-described problems, the present invention provides a method for manufacturing a semiconductor device including a step of grinding a back surface of a semiconductor wafer having a sealing layer formed on a circuit forming surface side of a semiconductor substrate, the back surface of the semiconductor wafer being When grinding, a range of 99% or more and 100.5% or less of the diameter of the semiconductor wafer on the circuit forming surface side is adsorbed.

これにより、本発明は、裏面研削時の半導体ウェハの周縁部のバタつきを防止することができ、半導体ウェハの周縁部の欠けを防止して、半導体ウェハの反りを抑制することができるという効果が得られる。   As a result, the present invention can prevent the peripheral edge of the semiconductor wafer from fluttering during back grinding, prevent the peripheral edge of the semiconductor wafer from being chipped, and suppress the warpage of the semiconductor wafer. Is obtained.

以下に、図面を参照して本発明による半導体装置の製造方法の実施例について説明する。   Embodiments of a semiconductor device manufacturing method according to the present invention will be described below with reference to the drawings.

図１、図２は実施例の半導体装置の製造方法を示す説明図、図３は実施例の工程Ｐ８における裏面研削装置を示す説明図である。
図１は、半導体装置の製造方法を、半導体ウェハに形成される電極パッドとこれに再配線等を介して接続するポスト電極との近傍を示す部分断面図で示したものである。
図１、図２において、１は半導体ウェハであり、本実施例ではＷＣＳＰ型の半導体装置を複数同時に製造するための８インチの円盤状の半導体ウェハである。 1 and 2 are explanatory views showing a method for manufacturing a semiconductor device of an embodiment, and FIG. 3 is an explanatory view showing a back surface grinding apparatus in step P8 of the embodiment.
FIG. 1 is a partial cross-sectional view showing a semiconductor device manufacturing method in the vicinity of an electrode pad formed on a semiconductor wafer and a post electrode connected to the electrode pad via a rewiring or the like.
1 and 2, reference numeral 1 denotes a semiconductor wafer. In this embodiment, reference numeral 1 denotes an 8-inch disk-shaped semiconductor wafer for simultaneously manufacturing a plurality of WCSP type semiconductor devices.

２は半導体ウェハ１の半導体基板であり、０．５〜１ｍｍ程度の厚さのシリコンからなるバルク基板であって、そのおもて面には図示しない半導体素子を配線で接続した複数の回路素子が形成されている（この回路素子が形成される半導体基板２のおもて面を回路形成面３という。）。
４は絶縁層であり、半導体基板２の回路形成面３上に２酸化珪素（ＳｉＯ２）等の絶縁材料で形成され、半導体基板２の各回路素子の上部には図示しないコンタクトホールが形成されている。 Reference numeral 2 denotes a semiconductor substrate of the semiconductor wafer 1, which is a bulk substrate made of silicon having a thickness of about 0.5 to 1 mm, and a plurality of circuit elements in which semiconductor elements (not shown) are connected to the front surface by wiring. (The front surface of the semiconductor substrate 2 on which the circuit element is formed is referred to as a circuit forming surface 3).
An insulating layer 4 is formed of an insulating material such as silicon dioxide (SiO 2 ) on the circuit formation surface 3 of the semiconductor substrate 2, and contact holes (not shown) are formed above the circuit elements of the semiconductor substrate 2. ing.

５は電極パッドであり、絶縁層４上にアルミニウム（Ａｌ）やチタン（Ｔｉ）等の導電材料で形成された導電層を所定の形状にエッチングして形成された電極であって、絶縁層４のコンタクトホールに埋め込まれた導電体を介して回路素子の所定の部位と電気的に接続している。
６は表面保護膜であり、窒化珪素（Ｓｉ３Ｎ４）等の絶縁材料で形成された絶縁層４上および電極パッド５の縁部を覆う保護膜である。 Reference numeral 5 denotes an electrode pad, which is an electrode formed by etching a conductive layer formed of a conductive material such as aluminum (Al) or titanium (Ti) on the insulating layer 4 into a predetermined shape. It is electrically connected to a predetermined part of the circuit element through a conductor buried in the contact hole.
A surface protective film 6 is a protective film that covers the insulating layer 4 formed of an insulating material such as silicon nitride (Si 3 N 4 ) and the edge of the electrode pad 5.

７は層間絶縁膜であり、表面保護膜６上にポリイミド等の絶縁材料で形成され、電極パッド５上の部位をエッチングにより除去して電極パッド５に到るスルーホール８が形成されている。
９は金属薄膜層としての下地金属層であり、半導体ウェハ１のおもて面側の全面にチタン（Ｔｉ）、窒化チタン（ＴｉＮ）、銅（Ｃｕ）等の導電材料を複数積層して形成され、層間絶縁膜７上およびスルーホール８の内面と電極パッド５上を覆っている。 Reference numeral 7 denotes an interlayer insulating film, which is formed of an insulating material such as polyimide on the surface protection film 6, and a through hole 8 reaching the electrode pad 5 is formed by removing a portion on the electrode pad 5 by etching.
9 is a base metal layer as a metal thin film layer, which is formed by laminating a plurality of conductive materials such as titanium (Ti), titanium nitride (TiN), copper (Cu) on the entire front surface side of the semiconductor wafer 1. Then, the interlayer insulating film 7 and the inner surface of the through hole 8 and the electrode pad 5 are covered.

１０は再配線であり、銅等の導電材で形成された電極パッド５上からその電極パッド５に接続するポスト電極１１を形成する領域（電極形成領域１２という。）上に到る配線パターンであって、下地金属層９を介して電極パッド５と電気的に接続しており、半導体基板２上を電極パッド５からポスト電極１１まで延在してポスト電極１１と電極パッド５とを電気的に接続する機能を有している。   Reference numeral 10 denotes a rewiring, which is a wiring pattern extending from an electrode pad 5 formed of a conductive material such as copper to a region (referred to as an electrode formation region 12) where a post electrode 11 connected to the electrode pad 5 is formed. Thus, the electrode pad 5 is electrically connected through the base metal layer 9, and the post electrode 11 and the electrode pad 5 are electrically connected to the semiconductor substrate 2 extending from the electrode pad 5 to the post electrode 11. It has a function to connect to.

ポスト電極１１は、再配線１０上の電極形成領域１２に再配線１０と同一の材料で形成された１００μｍ程度の高さを有する円柱状突起である。
１３はバンプ電極であり、ポスト電極１１のポスト端面１１ａ上に半田等で形成された半球状の電極であって、図示しない実装基板の配線端子と接合され、半導体装置の外部端子として機能する。これにより半導体基板２に形成された回路素子は、電極パッド５、下地金属層９、再配線１０、ポスト電極１１およびバンプ電極１３を介して外部装置と接続される。 The post electrode 11 is a cylindrical protrusion having a height of about 100 μm and formed in the electrode forming region 12 on the rewiring 10 with the same material as the rewiring 10.
Reference numeral 13 denotes a bump electrode, which is a hemispherical electrode formed on the post end surface 11a of the post electrode 11 with solder or the like, and is joined to a wiring terminal of a mounting board (not shown) and functions as an external terminal of the semiconductor device. Thereby, the circuit element formed on the semiconductor substrate 2 is connected to an external device through the electrode pad 5, the base metal layer 9, the rewiring 10, the post electrode 11, and the bump electrode 13.

１５は封止層であり、半導体ウェハ１のおもて面側に注入された熱硬化性のエポキシ樹脂等の封止樹脂を加熱硬化させて形成された絶縁性を有する１００μｍ程度の厚さの層であって、外部の湿度等から半導体装置を保護する機能を有している。
１７は保護テープであり、樹脂テープの片面にバンプ電極１３の凹凸を吸収することができる柔軟性を有し、紫外線の照射により軟化する特性を有する粘着層が形成された片面粘着テープであって、半導体基板２の回路形成面３の反対側の面、つまり半導体ウェハ１の裏面１ａを研削する際に、半導体ウェハ１のおもて面側を保護する機能を有している。 Reference numeral 15 denotes a sealing layer, which has a thickness of about 100 μm and has an insulating property formed by heat-curing a sealing resin such as a thermosetting epoxy resin injected into the front surface side of the semiconductor wafer 1. The layer has a function of protecting the semiconductor device from external humidity or the like.
Reference numeral 17 denotes a protective tape, which is a single-sided adhesive tape having a flexibility capable of absorbing irregularities of the bump electrode 13 on one side of a resin tape, and an adhesive layer having a property of being softened by ultraviolet irradiation. When the surface opposite to the circuit formation surface 3 of the semiconductor substrate 2, that is, the back surface 1a of the semiconductor wafer 1 is ground, the front surface side of the semiconductor wafer 1 is protected.

１８はレジストマスクであり、フォトリソグラフィにより半導体ウェハ１のおもて面に塗布されたレジストを露光し、その後に現像処理して形成されるマスク部材である。
図３において、２０は裏面研削装置である。
２１は吸着ステージであり、半導体ウェハ１の裏面１ａを研削する際に、保護テープ１７を介して半導体ウェハ１のおもて面側を吸着保持し、半導体ウェハ１を回転させる回転台であって、その中心部には半導体ウェハ１を吸着する負圧が供給される負圧室２２が形成されている。 Reference numeral 18 denotes a resist mask, which is a mask member formed by exposing a resist applied to the front surface of the semiconductor wafer 1 by photolithography and then developing the resist.
In FIG. 3, 20 is a back surface grinding apparatus.
Reference numeral 21 denotes a suction stage, which is a turntable for sucking and holding the front surface side of the semiconductor wafer 1 via the protective tape 17 and rotating the semiconductor wafer 1 when grinding the back surface 1a of the semiconductor wafer 1. A negative pressure chamber 22 to which a negative pressure for adsorbing the semiconductor wafer 1 is supplied is formed at the center thereof.

２３は吸着板であり、多孔質のセラミックス等で形成された半導体ウェハ１と同等の直径の吸着面２３ａを有する円盤状部材であって、負圧室２２の吸着ステージ２１の上面側の開口部に、その上面が吸着ステージ２１の上面と面一になるように取付けられている。
２５はグラインダであり、ダイヤモンド等の硬質の砥粒と無機質のフィラ等の充填材とを樹脂や金属等のバインダで固め、これを焼成して形成されたリング状の砥石２６を備えており、高速で回転して半導体ウェハ１の裏面１ａを研削する。また、砥石２６の研削面２６ａは半導体ウェハ１の中心を通る位置に配置されている。 Reference numeral 23 denotes an adsorption plate, which is a disk-shaped member having an adsorption surface 23a having the same diameter as that of the semiconductor wafer 1 formed of porous ceramics, and is an opening on the upper surface side of the adsorption stage 21 of the negative pressure chamber 22 The upper surface of the suction stage 21 is flush with the upper surface of the suction stage 21.
Reference numeral 25 denotes a grinder, which includes a ring-shaped grindstone 26 formed by hardening hard abrasive grains such as diamond and a filler such as an inorganic filler with a binder such as a resin or metal, and firing this. The back surface 1a of the semiconductor wafer 1 is ground by rotating at high speed. Further, the grinding surface 26 a of the grindstone 26 is disposed at a position passing through the center of the semiconductor wafer 1.

上記のように、本実施例の裏面研削装置２０は、通常の裏面研削装置（Ｄｉｓｃｏ社製 型番ＤＦＧ−８４１等）の吸着面が８インチ（規格寸法φ２００±０．２ｍｍ）の半導体ウェハ１の場合にφ１８６ｍｍであるのに対して、吸着面２３ａの直径がφ２００程度に形成されており、半導体ウェハ１のほぼ全面を吸着できるように形成されている。
以下に、図１、図２にＰで示す工程に従って、本実施例の半導体装置の製造方法について説明する。 As described above, the back surface grinding apparatus 20 of the present embodiment is a semiconductor wafer 1 having a suction surface of a normal back surface grinding apparatus (model number DFG-841, manufactured by Disco Corporation) of 8 inches (standard size φ200 ± 0.2 mm). In this case, the diameter of the suction surface 23a is formed to about φ200, whereas the diameter of the suction surface 23a is formed so as to be able to suck almost the entire surface of the semiconductor wafer 1.
A method for manufacturing the semiconductor device of this example will be described below in accordance with the process indicated by P in FIGS.

Ｐ１（図１）、半導体ウェハ１の半導体基板２の回路形成面３に、図示しない複数の回路素子を形成し、ＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法等により各回路素子の上部に図示しないコンタクトホールを設けた絶縁層４を形成した後に、絶縁層４上にスパッタ法により導電層を形成し、これを所定の形状にエッチングして回路素子の所定の部位と電気的に接続する電極パッド５を形成する。   P1 (FIG. 1), a plurality of circuit elements (not shown) are formed on the circuit formation surface 3 of the semiconductor substrate 2 of the semiconductor wafer 1, and contact holes (not shown) are formed above the circuit elements by CVD (Chemical Vapor Deposition) method or the like. After the provided insulating layer 4 is formed, a conductive layer is formed on the insulating layer 4 by sputtering, and this is etched into a predetermined shape to form an electrode pad 5 that is electrically connected to a predetermined portion of the circuit element. To do.

電極パッド５の形成後に、電極パッド５上と絶縁層４上にＣＶＤ法により窒化珪素からなる表面保護膜６を形成し、表面保護膜６の表層をエッチングして電極パッド５を露出させ、この表面保護膜６上および電極パッド５上に層間絶縁膜７を形成して電極パッド５の部位をエッチングにより除去し、層間絶縁膜７に電極パッド５に到るスルーホール８を形成する。   After the formation of the electrode pad 5, a surface protective film 6 made of silicon nitride is formed on the electrode pad 5 and the insulating layer 4 by a CVD method, and the surface layer of the surface protective film 6 is etched to expose the electrode pad 5. An interlayer insulating film 7 is formed on the surface protective film 6 and the electrode pad 5, and a portion of the electrode pad 5 is removed by etching, and a through hole 8 reaching the electrode pad 5 is formed in the interlayer insulating film 7.

Ｐ２（図１）、半導体ウェハ１のおもて面側にスパッタ法により層間絶縁膜７上および電極パッド５上を覆う複数層からなる下地金属層９を形成し、フォトリソグラフィにより下地金属層９の電極パッド５上から電極形成領域１２上に到る再配線１０の形成領域を除く領域にレジストマスク１８を形成し、露出している下地金属層９上に導電材を電気メッキ法により電着させ、電極パッド５上から電極形成領域１２上に到る再配線１０を形成する。   P2 (FIG. 1), a base metal layer 9 composed of a plurality of layers covering the interlayer insulating film 7 and the electrode pad 5 is formed on the front surface side of the semiconductor wafer 1 by sputtering, and the base metal layer 9 is formed by photolithography. A resist mask 18 is formed in a region excluding the formation region of the rewiring 10 extending from the electrode pad 5 to the electrode formation region 12, and a conductive material is electrodeposited on the exposed base metal layer 9 by electroplating. Then, the rewiring 10 extending from the electrode pad 5 to the electrode formation region 12 is formed.

Ｐ３（図１）、剥離剤を用いて工程Ｐ２で形成したレジストマスク１８を除去し、フォトリソグラフィにより半導体ウェハ１のおもて面側の再配線１０上の電極形成領域１２を除く領域にレジストマスク１８を形成し、露出している再配線１０上に導電材を電気メッキ法により電着させ、ポスト電極１１を形成する。
Ｐ４（図１）、剥離剤を用いて工程Ｐ３で形成したレジストマスク１８を除去し、再配線１０およびポスト電極１１を除く領域の下地金属層９をウェットマエッチングにより除去する。 P3 (FIG. 1), the resist mask 18 formed in the process P2 is removed using a release agent, and a resist is formed in a region other than the electrode formation region 12 on the rewiring 10 on the front surface side of the semiconductor wafer 1 by photolithography. A mask 18 is formed, and a conductive material is electrodeposited on the exposed rewiring 10 by electroplating to form a post electrode 11.
P4 (FIG. 1), the resist mask 18 formed in the step P3 is removed using a release agent, and the base metal layer 9 in the region excluding the rewiring 10 and the post electrode 11 is removed by wet etching.

Ｐ５（図２）、半導体ウェハ１を図示しない封止金型に収納し、封止金型の半導体ウェハ１のおもて面側の空間に封止樹脂を注入し、これを加熱硬化させて封止層１５を形成する。
この場合に、半導体ウェハ１のおもて面側の周縁部１ｂは、封止樹脂の漏れや裏面１ａへの回り込みを防止するために封止金型に押さえ込まれているので、半導体ウェハ１のおもて面側の周縁部１ｂには２ｍｍ程度（半導体ウェハ１との直径比で４％程度）の封止層１５が形成されていない部位が残り、そこに段差部が形成される。 P5 (FIG. 2), the semiconductor wafer 1 is stored in a sealing mold (not shown), a sealing resin is injected into the space on the front surface side of the semiconductor wafer 1 of the sealing mold, and this is heated and cured. The sealing layer 15 is formed.
In this case, the peripheral portion 1b on the front surface side of the semiconductor wafer 1 is pressed into the sealing mold in order to prevent leakage of the sealing resin and wraparound to the back surface 1a. A portion where the sealing layer 15 of about 2 mm (about 4% in diameter ratio with respect to the semiconductor wafer 1) is not formed is left on the peripheral portion 1b on the front surface side, and a step portion is formed there.

Ｐ６（図２）、封止金型から半導体ウェハ１を取出し、封止層１５のおもて面側を研削してポスト電極１１のポスト端面１１ａを封止層１５のおもて面に露出させ、封止層１５のおもて面とポスト端面１１ａとをほぼ同一平面に位置させて、１００μｍ程度の厚さの封止層１５を形成する。
Ｐ７（図２）、封止層１５のおもて面側に露出しているポスト端面１１ａにスクリーン印刷法等により半田を印刷し、その後に熱処理により半田を溶融させてポスト端面１１ａ上に半球形状に突出するバンプ電極１３を形成する。 P6 (FIG. 2), the semiconductor wafer 1 is taken out from the sealing mold, the front surface side of the sealing layer 15 is ground, and the post end surface 11a of the post electrode 11 is exposed to the front surface of the sealing layer 15. Then, the sealing layer 15 having a thickness of about 100 μm is formed by positioning the front surface of the sealing layer 15 and the post end surface 11a on substantially the same plane.
P7 (FIG. 2), solder is printed on the post end surface 11a exposed on the front surface side of the sealing layer 15 by a screen printing method or the like, and then the solder is melted by heat treatment to form a hemisphere on the post end surface 11a. A bump electrode 13 protruding in a shape is formed.

Ｐ８（図２）、バンプ電極１３を形成した半導体ウェハ１のおもて面側に、保護テープ１７の粘着層を密着させて貼付した後に、保護テープ１７を半導体ウェハ１と同等の直径に切断し、おもて面側に保護テープ１７を貼付した半導体ウェハ１を反転させ、保護テープ１７のテープ面を図３に示す裏面研削装置２０の吸着ステージ２１の吸着版２の吸着面２３ａ上に載置し、図示しない真空ポンプ等の負圧供給源から負圧を負圧室２２へ供給して吸着面２３ａに半導体ウェハ１のおもて面側の全面を吸着保持する。   P8 (FIG. 2), after sticking the adhesive layer of the protective tape 17 on the front surface side of the semiconductor wafer 1 on which the bump electrode 13 is formed, the protective tape 17 is cut to the same diameter as the semiconductor wafer 1 Then, the semiconductor wafer 1 having the protective tape 17 affixed to the front surface side is reversed, and the tape surface of the protective tape 17 is placed on the suction surface 23a of the suction plate 2 of the suction stage 21 of the back surface grinding apparatus 20 shown in FIG. Then, a negative pressure is supplied from a negative pressure supply source such as a vacuum pump (not shown) to the negative pressure chamber 22 to hold the entire surface of the semiconductor wafer 1 on the suction surface 23a by suction.

そして、吸着ステージ２１とグラインダ２５を回転させて半導体ウェハ１の半導体基板２の裏面１ａを研削し、５０〜３００μｍ程度のシリコン厚さ（本実施例では１９０μｍ）の半導体基板２を形成する。
Ｐ９（図２）、裏面１ａの研削を終えた半導体ウェハ１の保護テープ１７に紫外線を照射して粘着層を反応硬化させ、半導体ウェハ１から保護テープ１７を引き剥がし、半導体ウェハ１のおもて面側に弾性を有する分割用テープ２８に貼り付け、分割用のブレード２９により半導体ウェハ１のおもて面２に予め設けられた分割線に沿って縦横に切断して複数の個片に分割する。 Then, the suction stage 21 and the grinder 25 are rotated to grind the back surface 1a of the semiconductor substrate 2 of the semiconductor wafer 1 to form the semiconductor substrate 2 having a silicon thickness of about 50 to 300 μm (190 μm in this embodiment).
P9 (FIG. 2), the protective tape 17 of the semiconductor wafer 1 that has been ground on the back surface 1a is irradiated with ultraviolet rays to cure the adhesive layer, and the protective tape 17 is peeled off from the semiconductor wafer 1. Affixed to the dividing tape 28 having elasticity on the surface side, and cut into a plurality of pieces by dividing vertically and horizontally along a dividing line provided in advance on the front surface 2 of the semiconductor wafer 1 by a dividing blade 29. To divide.

Ｐ１０（図２）、この分割された個片、すなわち個片に分割された半導体ウェハ１であるＷＣＳＰ型の半導体装置３０は、分割用テープ２８の弾性を利用して押し広げられた個々の間隔を利用してロボットアーム等により個別にチップトレイ等に移し変えられる。
このようにして、厚さが０．５ｍｍ以下（本実施例では０．２５ｍｍ程度）の薄型化された小型のＷＣＳＰ型の半導体装置３０が製造される。 P10 (FIG. 2), the divided pieces, that is, the WCSP type semiconductor device 30 which is the semiconductor wafer 1 divided into pieces, are separated by using the elasticity of the dividing tape 28. Can be individually transferred to a chip tray or the like by a robot arm or the like.
In this way, a thin WCSP type semiconductor device 30 with a thickness of 0.5 mm or less (about 0.25 mm in this embodiment) is manufactured.

この製造工程において、半導体ウェハ１の反りを抑制するためには、上記したように、半導体ウェハ１の半導体基板２の周縁部１ｂに欠けが多数生じるのを防止することが重要である。
この欠けは、通常の吸着ステージ２１では吸着面積が小さいために、剛性が低くなっている封止層１５の周囲の段差部が、工程Ｐ８における半導体ウェハ１の裏面研削時にバタついて半導体基板２の周縁部１ｂに欠けを生じさせることが主な原因と考えられる。 In this manufacturing process, in order to suppress the warpage of the semiconductor wafer 1, it is important to prevent a large number of chips from occurring in the peripheral portion 1b of the semiconductor substrate 2 of the semiconductor wafer 1 as described above.
This chipping has a small suction area in the normal suction stage 21, so that the stepped portion around the sealing layer 15 having low rigidity flutters when the back surface of the semiconductor wafer 1 is ground in the process P <b> 8. The main cause is considered to be a chip in the peripheral edge 1b.

図４は、吸着面積の多寡が、半導体ウェハ１の反りに与える影響を評価した評価結果である。
図４の横軸は半導体ウェハ１の直径（ウェハ直径）に対する吸着面２３ａの直径の比（ウェハ直径比という。単位：パーセント）を示し、縦軸は半導体ウェハ１のウェハ反り量を示す。 FIG. 4 shows an evaluation result of evaluating the influence of the amount of the adsorption area on the warp of the semiconductor wafer 1.
4 indicates the ratio of the diameter of the suction surface 23a to the diameter of the semiconductor wafer 1 (wafer diameter) (referred to as wafer diameter ratio; unit: percent), and the vertical axis indicates the amount of wafer warpage of the semiconductor wafer 1.

評価に用いた半導体ウェハ１は、半導体基板２の厚さ１９０μｍ、封止層１５の厚さ９０μｍ、ウェハ直径２００ｍｍの半導体ウェハである。
図４から明らかに、ウェハ直径比が９７％を超えると反りが減少し始め、ウェハ直径比が９９％以上、１００．５％以下の範囲で反りが減少した状態で安定し、ウェハ直径比が１００．５％を超えると反りが急激に増加することが判る。 The semiconductor wafer 1 used for evaluation is a semiconductor wafer having a thickness of the semiconductor substrate 2 of 190 μm, a thickness of the sealing layer 15 of 90 μm, and a wafer diameter of 200 mm.
As is apparent from FIG. 4, when the wafer diameter ratio exceeds 97%, the warpage starts to decrease, and when the wafer diameter ratio is in the range of 99% or more and 100.5% or less, the warp is reduced and the wafer diameter ratio is stable. It can be seen that the warpage sharply increases when it exceeds 100.5%.

つまり、半導体ウェハ１の裏面研削時の吸着面２３ａの直径は、ウェハ直径の９９％以上、１００．５％以下の範囲にすることが望ましい。ウェハ直径比が９９％未満の時は吸着面積が少なくなって半導体ウェハ１の周縁部１ｂにバタつきが生じ、ウェハ直径比が１００．５％を超えると、吸着板２３の吸着面２３ａの半導体ウェハ１に覆われていない部分が増加し、負圧が逃げて負圧による吸着力が減少し、結果として半導体ウェハ１の周縁部１ｂにバタつきが生じるからである。   That is, it is desirable that the diameter of the suction surface 23a when grinding the back surface of the semiconductor wafer 1 is in the range of 99% to 100.5% of the wafer diameter. When the wafer diameter ratio is less than 99%, the suction area decreases and the peripheral edge 1b of the semiconductor wafer 1 flutters. When the wafer diameter ratio exceeds 100.5%, the semiconductor on the suction surface 23a of the suction plate 23 This is because the portion not covered with the wafer 1 increases, the negative pressure escapes and the adsorption force due to the negative pressure decreases, and as a result, the peripheral edge 1b of the semiconductor wafer 1 is fluttered.

このように、吸着面２３ａの直径をウェハ直径の９９％以上、１００．５％以下の範囲として半導体ウェハ１のおもて面側を吸着すれば、半導体ウェハの周縁部の欠けによる半導体ウェハ１の反りに対する拘束力が低下することはなく、半導体ウェハ１の反りを抑制することができる他、周縁部の欠けに起因する半導体ウェハ１の割れを防止することができる。   Thus, if the front surface side of the semiconductor wafer 1 is sucked with the diameter of the suction surface 23a in the range of 99% or more and 100.5% or less of the wafer diameter, the semiconductor wafer 1 due to chipping of the peripheral portion of the semiconductor wafer 1 In addition to suppressing the warping of the semiconductor wafer 1, it is possible to prevent cracking of the semiconductor wafer 1 due to the chipping of the peripheral edge portion.

また、半導体ウェハ１の反りを抑制するためには、半導体ウェハ１の裏面１ｂの研削後の面粗度を向上させることが重要である。
図５は、半導体ウェハ１の裏面１ｂの面粗度の大小が、反りに与える影響を評価した評価結果である。
図５の横軸は半導体ウェハ１の半導体基板２の裏面１ｂの研削後の面粗度（裏面粗度）を算術平均粗さＲａで示し、縦軸は半導体ウェハ１のウェハ反り量を示す。 Further, in order to suppress the warpage of the semiconductor wafer 1, it is important to improve the surface roughness after grinding of the back surface 1 b of the semiconductor wafer 1.
FIG. 5 shows an evaluation result of evaluating the influence of the surface roughness of the back surface 1b of the semiconductor wafer 1 on the warpage.
The horizontal axis of FIG. 5 indicates the surface roughness (back surface roughness) after grinding of the back surface 1 b of the semiconductor substrate 2 of the semiconductor wafer 1 by the arithmetic average roughness Ra, and the vertical axis indicates the amount of wafer warpage of the semiconductor wafer 1.

評価に用いた半導体ウェハ１は、半導体基板２の厚さ１９０μｍ、封止層１５の厚さ９０μｍ、ウェハ直径２００ｍｍの半導体ウェハである。
なお、図５に示すＥ点は工程Ｐ８の裏面研削を＃８０００、Ｆ点は＃５０００、Ｇ点は＃２０００の砥石２６で研削したものである。
図５から明らかに、半導体ウェハ１の裏面研削後の裏面粗度を向上させれば、半導体ウェハ１の反りが減少することが判る。 The semiconductor wafer 1 used for evaluation is a semiconductor wafer having a thickness of the semiconductor substrate 2 of 190 μm, a thickness of the sealing layer 15 of 90 μm, and a wafer diameter of 200 mm.
In addition, the E point shown in FIG. 5 is what grind | polished the back surface grinding | polishing of process P8 with # 8000, F point with # 5000, and G point with # 2000 grindstone 26.
As is apparent from FIG. 5, if the back surface roughness after the back surface grinding of the semiconductor wafer 1 is improved, the warpage of the semiconductor wafer 1 is reduced.

この場合に、半導体ウェハ１の搬送時のチャック性、半導体ウェハ１のマガジン等への収納時の安定性を考慮すれば、裏面粗度をＲａ＝５ｎｍ以下にすることが望ましい。半導体ウェハ１に、裏面粗度がＲａ＝５ｎｍを超える面粗度に相当する反りが生ずると、半導体ウェハ１の搬送時のチャック性が低下して落下により破損する場合がある他、マガジン等への収納時の姿勢が不安定になり半導体ウェハ１にクラックが生じやすくなるからである。   In this case, the back surface roughness is desirably Ra = 5 nm or less in consideration of the chucking property when the semiconductor wafer 1 is transported and the stability when the semiconductor wafer 1 is stored in a magazine or the like. If the semiconductor wafer 1 is warped corresponding to a surface roughness with a back surface roughness exceeding Ra = 5 nm, the chucking property at the time of transporting the semiconductor wafer 1 may be deteriorated and may be damaged due to dropping, or to a magazine or the like. This is because the posture at the time of storage becomes unstable and the semiconductor wafer 1 is likely to crack.

なお、裏面粗度の下限はＲａ＝１ｎｍ以上にするとよい。裏面粗度をＲａ＝１ｎｍ未満にすると、半導体基板２の回路素子が形成される活性領域における不要な金属不純物を集める役割を果たすゲッタリングサイトがなくなり、半導体装置３０の電気特性が低下する虞があるからである。
このように、半導体ウェハ１の裏面研削後の裏面粗度をＲａ＝５ｎｍ以下にすれば、裏面１ａの凹凸が減少して半導体ウェハの裏面の反りに対する拘束力を高めることができ、半導体ウェハ１の反りを抑制することができる。 The lower limit of the back surface roughness is preferably Ra = 1 nm or more. When the back surface roughness is less than Ra = 1 nm, there is no gettering site for collecting unnecessary metal impurities in the active region where the circuit elements of the semiconductor substrate 2 are formed, and the electrical characteristics of the semiconductor device 30 may be deteriorated. Because there is.
As described above, when the back surface roughness after the back surface grinding of the semiconductor wafer 1 is set to Ra = 5 nm or less, the unevenness of the back surface 1a is reduced, and the restraining force against the warp of the back surface of the semiconductor wafer can be increased. Can be suppressed.

更に、半導体ウェハ１の反りを抑制するためには、半導体ウェハ１に張り合わせる封止層１５の曲げ弾性率に着目することが重要である。
図６は、半導体ウェハ１の封止層１５に用いる樹脂の曲げ弾性率が反りに与える影響を評価した評価結果である。
図６の横軸は封止層１５に用いる樹脂の常温時の曲げ弾性率を示し、縦軸は半導体ウェハ１のウェハ反り量を示す。 Furthermore, in order to suppress the warp of the semiconductor wafer 1, it is important to pay attention to the bending elastic modulus of the sealing layer 15 bonded to the semiconductor wafer 1.
FIG. 6 shows the evaluation results of evaluating the influence of the bending elastic modulus of the resin used for the sealing layer 15 of the semiconductor wafer 1 on the warpage.
The horizontal axis of FIG. 6 indicates the bending elastic modulus at normal temperature of the resin used for the sealing layer 15, and the vertical axis indicates the amount of warpage of the semiconductor wafer 1.

評価に用いた半導体ウェハ１は、半導体基板２の厚さ９０μｍ、封止層１５の厚さ９０μｍ、ウェハ直径２００ｍｍの半導体ウェハである。
図６から明らかに、半導体ウェハ１の反りは、封止層１５に用いる樹脂の常温時の曲げ弾性率が１４ＧＰａを最小として、その両側で増加することが判る。
なお、半導体基板２の厚さを他の厚さとしても、図６と同様の評価結果が得られることは、実験的に確認されている。 The semiconductor wafer 1 used for the evaluation is a semiconductor wafer having a thickness of the semiconductor substrate 2 of 90 μm, a thickness of the sealing layer 15 of 90 μm, and a wafer diameter of 200 mm.
As is apparent from FIG. 6, it can be seen that the warpage of the semiconductor wafer 1 increases on both sides of the resin used for the sealing layer 15 with a bending elastic modulus at normal temperature of 14 GPa.
It has been experimentally confirmed that the same evaluation results as in FIG. 6 can be obtained even if the thickness of the semiconductor substrate 2 is another thickness.

また、封止層１５の曲げ弾性率は、完成後の半導体装置３０の抗折強度にも影響を与えるので、抗折強度に対する考慮をする必要がある。
図７は、封止層１５に用いる樹脂の曲げ弾性率が、完成後の半導体装置３０の抗折強度に与える影響を評価した評価結果である。
図７の横軸は半導体ウェハ１に用いた封止層１５の樹脂の常温時の曲げ弾性率を示し、縦軸は完成後の半導体装置３０の曲げ破壊応力を示す。 Moreover, since the bending elastic modulus of the sealing layer 15 also affects the bending strength of the completed semiconductor device 30, it is necessary to consider the bending strength.
FIG. 7 shows the evaluation results of evaluating the influence of the bending elastic modulus of the resin used for the sealing layer 15 on the bending strength of the semiconductor device 30 after completion.
The horizontal axis of FIG. 7 shows the bending elastic modulus at normal temperature of the resin of the sealing layer 15 used for the semiconductor wafer 1, and the vertical axis shows the bending fracture stress of the semiconductor device 30 after completion.

図７から明らかに、完成後の半導体装置３０の抗折強度は、封止層１５に用いる樹脂の常温時の曲げ弾性率が１８ＧＰａを最大として、その両側で低下することが判る。
この相反する特性を考慮して半導体ウェハ１の反りを抑制するためには、封止層１５の樹脂の常温時の曲げ弾性率を１２ＧＰａ以上、１８ＧＰａ以下の範囲とすることが望ましい。曲げ弾性率を１２ＧＰａ未満にすると半導体ウェハ１の反りとしては適当な範囲が存在するが半導体装置３０の抗折強度が低くなり過ぎ、１８ＧＰａを超えると半導体装置３０の抗折強度としては適当な範囲が存在するが半導体ウェハ１の反りが大きくなり過ぎるからである。 As can be seen from FIG. 7, the bending strength of the completed semiconductor device 30 decreases at both sides of the bending elastic modulus of the resin used for the sealing layer 15 at the normal temperature of 18 GPa.
In order to suppress warping of the semiconductor wafer 1 in consideration of the contradictory characteristics, it is desirable that the bending elastic modulus of the resin of the sealing layer 15 at room temperature is in a range of 12 GPa or more and 18 GPa or less. If the flexural modulus is less than 12 GPa, there is an appropriate range for the warp of the semiconductor wafer 1, but the bending strength of the semiconductor device 30 becomes too low, and if it exceeds 18 GPa, the bending strength of the semiconductor device 30 is appropriate. This is because the warp of the semiconductor wafer 1 becomes too large.

上記の範囲の曲げ弾性率を有する封止樹脂は、樹脂材料に含有させるフィラの量を変更することにより形成することができる。例えば、熱硬化性のエポキシ樹脂にシリカフィラを８０〜８５重量パーセント含有させることで、上記の範囲の曲げ弾性率を有する封止層１５を形成することができる。
このように、封止層１５の樹脂の常温時の曲げ弾性率を１２ＧＰａ以上、１８ＧＰａ以下の範囲にすれば、半導体装置３０の抗折強度を確保しながら半導体ウェハ１の反りを抑制することができる。 The sealing resin having a bending elastic modulus in the above range can be formed by changing the amount of filler contained in the resin material. For example, the sealing layer 15 having a bending elastic modulus in the above range can be formed by containing 80 to 85 weight percent of silica filler in a thermosetting epoxy resin.
Thus, if the bending elastic modulus at normal temperature of the resin of the sealing layer 15 is in the range of 12 GPa or more and 18 GPa or less, the warp of the semiconductor wafer 1 can be suppressed while ensuring the bending strength of the semiconductor device 30. it can.

以上説明したように、本実施例では、半導体基板の回路形成面側に封止層を形成した半導体ウェハの裏面を研削する工程において、半導体ウェハの裏面を研削するときに、回路形成面側を半導体ウェハの直径の９９％以上、１００．５％以下の範囲を吸着する吸着面を有する吸着ステージに吸着するようにしたことによって、裏面研削時の半導体ウェハの周縁部のバタつきを防止することができ、半導体ウェハの周縁部の欠けを防止して、半導体ウェハの反りを抑制することができる。   As described above, in this embodiment, in the step of grinding the back surface of the semiconductor wafer in which the sealing layer is formed on the circuit formation surface side of the semiconductor substrate, when the back surface of the semiconductor wafer is ground, the circuit formation surface side is Preventing the peripheral edge of the semiconductor wafer from fluttering during backside grinding by adsorbing it to an adsorption stage having an adsorption surface that adsorbs a range of 99% to 100.5% of the diameter of the semiconductor wafer. It is possible to prevent the peripheral edge of the semiconductor wafer from being chipped and to suppress warping of the semiconductor wafer.

また、半導体基板の回路形成面側に封止層を形成した半導体ウェハの裏面を研削する工程において、半導体ウェハの裏面の研削後の面粗度をＲａ＝５ｎｍ以下としたことによって、半導体ウェハの裏面の凹凸を減少させて半導体ウェハの裏面の反りに対する拘束力を高めることができ、半導体ウェハの反りを抑制することができる。
更に、半導体基板の回路形成面側に封止層を形成した半導体ウェハの裏面を研削する工程において、封止層を、常温の曲げ弾性率が、１２ＧＰａ以上、１８ＧＰａ以下の樹脂材料で形成するようにしたことによって、完成後の半導体装置の抗折強度を確保しながら半導体ウェハの反りを抑制することができる。 Further, in the step of grinding the back surface of the semiconductor wafer in which the sealing layer is formed on the circuit forming surface side of the semiconductor substrate, the surface roughness after grinding of the back surface of the semiconductor wafer is set to Ra = 5 nm or less. The concavity and convexity of the back surface of the semiconductor wafer can be increased by reducing the irregularities on the back surface, and the warpage of the semiconductor wafer can be suppressed.
Further, in the step of grinding the back surface of the semiconductor wafer having the sealing layer formed on the circuit forming surface side of the semiconductor substrate, the sealing layer is formed of a resin material having a bending elastic modulus at room temperature of 12 GPa or more and 18 GPa or less. By doing so, the warp of the semiconductor wafer can be suppressed while ensuring the bending strength of the completed semiconductor device.

更に、上記により製造された半導体装置は、配線基板に搭載される受動部品とほぼ同等の厚さを有する半導体装置とすることができ、配線基板間の設置間隔等を低減して電子機器の薄型化に貢献することができる。
なお、本実施例においては、半導体ウェハの半導体基板は、シリコンからなるバルク基板であるとして説明したが、半導体ウェハは前記に限らず、封止層を形成したＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔｏｒ）構造の半導体ウェハやＳＯＳ（Ｓｉｌｉｃｏｎ Ｏｎ Ｓａｐｐｈｉｒｅ）構造の半導体ウェハ等であっても、本発明を適用すれば上記と同様の効果を得ることができる。 Furthermore, the semiconductor device manufactured as described above can be a semiconductor device having a thickness substantially equal to that of the passive component mounted on the wiring board, and the installation interval between the wiring boards can be reduced to reduce the thickness of the electronic device. Can contribute.
In the present embodiment, the semiconductor substrate of the semiconductor wafer is described as being a bulk substrate made of silicon. However, the semiconductor wafer is not limited to the above, and an SOI (Silicon On Insulator) structure semiconductor in which a sealing layer is formed. Even if it is a wafer or a semiconductor wafer having an SOS (Silicon On Sapphire) structure, the same effects as described above can be obtained by applying the present invention.

実施例の半導体装置の製造方法を示す説明図Explanatory drawing which shows the manufacturing method of the semiconductor device of an Example 実施例の半導体装置の製造方法を示す説明図Explanatory drawing which shows the manufacturing method of the semiconductor device of an Example 実施例の工程Ｐ８における裏面研削装置を示す説明図Explanatory drawing which shows the back surface grinding apparatus in process P8 of an Example. 吸着面積が半導体ウェハの反りに与える影響を示すグラフGraph showing the effect of adsorption area on the warpage of a semiconductor wafer 裏面粗度が半導体ウェハの反りに与える影響を示すグラフGraph showing the effect of back surface roughness on semiconductor wafer warpage 封止層の曲げ弾性率が半導体ウェハの反りに与える影響を示すグラフThe graph which shows the influence which the bending elastic modulus of a sealing layer has on the curvature of a semiconductor wafer 封止層の曲げ弾性率が半導体装置の抗折強度に与える影響を示すグラフThe graph which shows the influence which the bending elastic modulus of the sealing layer has on the bending strength of a semiconductor device

符号の説明Explanation of symbols

１ 半導体ウェハ
１ａ 裏面
２ 半導体基板
３ 回路形成面
４ 絶縁層
５ 電極パッド
６ 表面保護膜
７ 層間絶縁膜
８ スルーホール
９ 下地金属層
１０ 再配線
１１ ポスト電極
１１ａ ポスト端面
１２ 電極形成領域
１３ バンプ電極
１５ 封止層
１７ 保護テープ
１８ レジストマスク
２０ 裏面研削装置
２１ 吸着ステージ
２２ 負圧室
２３ 吸着板
２３ａ 吸着面
２５ グラインダ
２６ 砥石
２６ａ 研削面
２８ 分割用テープ
２９ ブレード
３０ 半導体装置 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a Back surface 2 Semiconductor substrate 3 Circuit formation surface 4 Insulation layer 5 Electrode pad 6 Surface protective film 7 Interlayer insulation film 8 Through hole 9 Underlayer metal layer 10 Rewiring 11 Post electrode 11a Post end surface 12 Electrode formation region 13 Bump electrode 15 Sealing layer 17 Protective tape 18 Resist mask 20 Back surface grinding device 21 Suction stage 22 Negative pressure chamber 23 Suction plate 23a Suction surface 25 Grinder 26 Grinding stone 26a Grinding surface 28 Dividing tape 29 Blade 30 Semiconductor device

Claims (3)

半導体基板の回路形成面側に封止層を形成した半導体ウェハの裏面を研削する工程を含む半導体装置の製造方法であって、
前記半導体ウェハの裏面を研削するときに、前記回路形成面側の、前記半導体ウェハの直径の９９％以上、１００．５％以下の範囲を吸着することを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device comprising a step of grinding a back surface of a semiconductor wafer in which a sealing layer is formed on a circuit forming surface side of a semiconductor substrate,
A method of manufacturing a semiconductor device, comprising: adhering a range of 99% or more and 100.5% or less of the diameter of the semiconductor wafer on the circuit forming surface side when the back surface of the semiconductor wafer is ground. 半導体基板の回路形成面側に封止層を形成した半導体ウェハの裏面を研削する工程を含む半導体装置の製造方法であって、
前記半導体ウェハの裏面の研削後の面粗度が、Ｒａ＝５ｎｍ以下であることを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device comprising a step of grinding a back surface of a semiconductor wafer in which a sealing layer is formed on a circuit forming surface side of a semiconductor substrate,
A method of manufacturing a semiconductor device, wherein the roughness of the back surface of the semiconductor wafer after grinding is Ra = 5 nm or less. 半導体基板の回路形成面側に封止層を形成した半導体ウェハの裏面を研削する工程を含む半導体装置の製造方法であって、
前記封止層を、常温の曲げ弾性率が、１２ＧＰａ以上、１８ＧＰａ以下の樹脂材料で形成したことを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device comprising a step of grinding a back surface of a semiconductor wafer in which a sealing layer is formed on a circuit forming surface side of a semiconductor substrate,
A method of manufacturing a semiconductor device, wherein the sealing layer is formed of a resin material having a bending elastic modulus at room temperature of 12 GPa or more and 18 GPa or less.
JP2006035320A 2006-02-13 2006-02-13 Semiconductor device and its manufacturing method Pending JP2007214502A (en)

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