US6545725B1 - Apparatus for identifying standard and non-standard video signals - Google Patents
Apparatus for identifying standard and non-standard video signals Download PDFInfo
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- US6545725B1 US6545725B1 US09/553,153 US55315300A US6545725B1 US 6545725 B1 US6545725 B1 US 6545725B1 US 55315300 A US55315300 A US 55315300A US 6545725 B1 US6545725 B1 US 6545725B1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/642—Multi-standard receivers
Definitions
- the present invention relates to a standard and non-standard video signal identifying apparatus for determining whether a composite video signal input to a television receiver or the like is a standard signal or a non-standard signal.
- the above-mentioned standard signal refers to a television signal in which the frequency of the color subcarrier signal is strictly managed so as to be exactly an integral multiple of the frequency of the vertical synchronizing signal like a broadcast wave (composite video signal) from a broadcasting station.
- the non-standard signal refers to a television signal in which the frequency of the color subcarrier signal is a non-integral multiple of the frequencies of the vertical synchronizing signal and the horizontal synchronizing signal like a playback video signal (composite video signal) output from a digital video tape recorder, a digital video camera, a digital still camera or other video apparatuses.
- the frequency of the color subcarrier signal is strictly managed so as to be exactly an integral multiple of the frequency of the vertical synchronizing signal. Therefore, television receivers are configured as described below in order to effectively use the relationship between the color subcarrier frequency and the vertical frequency and that the vertical synchronizing signal can be precisely played back even when the electric field is weak or when a disturbance occurs due to ghosts. That is, one burst signal is extracted from an input video signal, a clock of a frequency of a ⁇ f SC (a is an integer not less than 1, and f SC is the color subcarrier frequency) is generated based on a color burst signal, and the clock is divided, thereby playing back the vertical synchronizing signal.
- a ⁇ f SC a is an integer not less than 1
- f SC is the color subcarrier frequency
- V count ( a ⁇ f SC /f H ) ⁇ ( N /2).
- Vcount is the number of clocks of one field section
- f H is the horizontal frequency
- N is the number of scanning lines of one frame.
- V count ( a ⁇ f SC /f H ) ⁇ ( N /2).
- vertical playback is performed by separating the vertical synchronizing signal from the video signal by a synchronizing separator circuit.
- a processing such as Y/C separation using a frame comb filter or inter-field interpolation is used to enhance the image quality.
- the Y/C separation in the case of standard signals in which the color subcarrier frequency is exactly an integral multiple of the vertical frequency, the luminance signal and the color signal can be precisely separated by the frame comb filter, so that the effect of enhancing the image quality is expected.
- the luminance signal and the color signal cannot be separated precisely, so that the above-mentioned image quality enhancing processing rather degrades the image quality. Therefore, it is desirable that the image quality enhancing processing be performed only in the case of standard signals and be not performed in the case of non-standard signals.
- FIG. 7 is a block diagram showing a concrete example of the conventional standard and non-standard video signal identifying apparatus in the case of generation of the vertical synchronizing signal of an NTSC television receiver.
- a reset circuit comprising an AND gate 401 outputs a reset signal when an external reset signal supplied from a microcomputer comes in or when an external vertical synchronizing signal separated by a synchronizing separator circuit (not shown) comes in.
- the reset signal is input to a reset terminal R of a vertical counter 402 .
- a clock of a frequency of a ⁇ f SC generated by a clock generating circuit 403 is input to a clock terminal CLK.
- the clock generating circuit 403 generates the clock of a frequency of a ⁇ f SC based on a color burst signal extracted from the video signal.
- the vertical counter 402 counts the number of clocks of one field section after the reset signal is input.
- a load hold flip-flop 404 which receives the output of the vertical counter 402 as the input signal and uses the external vertical synchronizing signal as the load hold pulse, latches the value that the vertical counter 402 indicates when the external vertical synchronizing signal comes in, and outputs the latched value. That is, the output of the load hold flip-flop 404 represents the clock count of one field section defined by the external vertical synchronizing signal.
- a field clock count setting register 405 a value corresponding to the clock count of one field section of a standard signal is set.
- a subtracter 406 subtracts the value set in the field clock count setting register 405 from the output of the load hold flip-flop 404 .
- the output value of the subtracter 406 corresponds to the shift of the clock count value of one field section defined by the external vertical synchronizing signal from the clock count value corresponding to the standard signal.
- the output of the subtracter 406 is converted into an absolute value by an absolute value circuit 407 and the absolute value of the shift is output.
- a threshold value setting register 408 a threshold value for identifying standard and non-standard signals is set.
- a comparator 409 compares the output of the absolute value circuit 407 with the threshold value set in the threshold value setting register 408 . When the output of the absolute value circuit 407 is not more than the threshold value, the input video signal is determined to be a standard signal, and when the output exceeds the threshold value, the input video signal is determined to be a non-standard signal.
- the input video signal is determined to be a standard signal when the clock count Vcount of one field section satisfies the following relationship:
- M is the threshold value for identifying standard and non-standard signals.
- the input video signal is determined to be a non-standard signal.
- a non-standard signal such as the output of a digital still camera in which the clock count is shifted by one clock (clock frequency a ⁇ f SC ) in n field sections although the shift of the clock count of one field section is smaller than one clock and Vcount satisfies the above-mentioned relationship in the unit of one field is erroneously determined to be a standard signal.
- an object of the present invention is to provide an apparatus for identifying standard and non-standard video signals with which even a non-standard signal having only a slight shift and being conventionally erroneously determined to be a standard signal in the unit of one field can be determined to be a non-standard signal.
- An apparatus for identifying standard and non-standard video signals comprises clock generating means, clock counting means, resetting means, count value holding means, first determining means, subtracting means, selecting means, and second determining means.
- the clock generating means has the function of generating a clock of a frequency of a ⁇ f SC (a is an integer not less than 1, and f SC is a color carrier frequency) based on a color burst signal extracted from a video signal.
- the clock counting means whose maximum output value is a value corresponding to the number of clocks generated by the clock generating means in one field section of a standard signal has the function of counting the number of clocks generated by the clock generating means and repetitively changing an output value thereof from zero to the maximum output value.
- the resetting means has the function of resetting a count value of the clock counting means to zero in response to input of an external reset signal and canceling the reset of the count value of the clock counting means in response to an external vertical synchronizing signal separated from the video signal and input after the input of the external reset signal.
- the count value holding means has the function of holding the count value of the clock counting means in response to the input of the external vertical synchronizing signal.
- the first determining means has the function of comparing an output value of the count value holding means with a first threshold value to thereby determine whether the output value of the count value holding means is zero or a value in the vicinity thereof, or the maximum output value of the clock counting means or a value in the vicinity thereof.
- the subtracting means has the function of obtaining a difference between the output value of the count value holding means and the maximum output value of the clock counting means.
- the selecting means has the function of, based on a result of the determination by the first determining means, selecting the output value of the count value holding means when the output value of the count value holding means is zero or a value in the vicinity thereof, and selecting the output value of the subtracting means when the output value of the count value holding means is the maximum output value of the clock counting means or a value in the vicinity thereof.
- the second determining means has the function of determining that the video signal is a non-standard signal when an absolute value of an output value of the selecting means is higher than a second threshold value.
- the clock count of the clock counting means returns to zero every time its output reaches the maximum output value, that is, every time the number of clocks is counted to the value corresponding to the clock count of one field section of the standard signal, and the clock counting means is not dependent on the incoming external vertical synchronizing signal.
- the shift of the clock count of one field section is accumulated over a multiplicity of fields, so that even a signal in which the shift is not less than one clock in the unit of n fields although the shift is smaller than one clock and the relationship as the standard signal is satisfied in the unit of one field like the output of a digital still camera can be determined to be a non-standard signal.
- the clock counting means comprises, for example, a counter for counting the number of clocks generated by the clock generating means, a field clock count setting register for setting a value corresponding to the number of clocks output by the clock generating means in one field section of the standard signal, and a decode circuit for outputting a coincidence signal when a count value of the counter coincides with the set value of the field clock count setting register, and supplying the coincidence signal to a reset terminal of the counter.
- the clock counting means in a system using a signal being a constant multiple a of the color carrier frequency f SC as the system clock, only when the output of the vertical counter becomes the value corresponding to the clock count of the one field section of the standard signal which is the value set by the field clock count setting register, the vertical counter is reset so that its count value returns to zero, and is not dependent on the incoming external vertical synchronizing signal.
- the shift of the clock count of one field section is accumulated over a multiplicity of fields, so that even a signal in which the shift is not less than one clock in the unit of n fields although the shift is smaller than one clock and the relationship as the standard signal is satisfied in the unit of one field like the output of a digital still camera can be determined to be a non-standard signal.
- the threshold value is not limited thereto. It may be any value that is higher than the maximum value of values in the vicinity of zero estimated to be the output value of the count value holding means and is lower than the minimum value of values in the vicinity of the maximum output value in the case of a non-standard signal.
- the count value holding means comprises, for example, a load hold flip-flop receiving the external vertical synchronizing signal as a load hold input and receiving the clock generated by the clock generating circuit as a clock input.
- the resetting means comprises a set-reset flip-flop receiving the external reset signal as a set input, and receiving the external vertical synchronizing signal as a reset input.
- An apparatus for identifying standard and non-standard video signals comprises clock generating means, pulse thinning out means, clock counting means, count value holding means, n field clock count setting means, subtracting means, and determining means.
- the clock generating means has the function of generating a clock of a frequency of a ⁇ f SC (a is an integer not less than 1, and f SC is a color carrier frequency) based on a color burst signal extracted from a video signal.
- the pulse thinning out means has the function of thinning out an external vertical synchronizing signal separated from the video signal, and outputting the thinned out signal once every n fields (n is a plural number).
- the clock counting means has the function of counting the number of clocks generated by the clock generating means, and its count value is reset to 0 in response to an output pulse of the pulse thinning out means.
- the count value holding means has the function of holding an output value of the clock counting means in response to the output pulse of the pulse thinning out means.
- the n field clock count setting means has the function of setting a value corresponding to the number of clocks generated by the clock generating means in n field sections of a standard signal.
- the subtracting means has the function of obtaining a difference between an output value of the count value holding means and the set value of the n field clock count setting means.
- the determining means has the function of determining that the video signal is a non-standard signal when an absolute value of an output value of the subtracting means is higher than a predetermined threshold value.
- the clock counting means counts the number of clocks of n field sections
- the output value of the clock counting means produced immediately before the clock counting means is reset is held by the count value holding means
- the output value of the count value holding means is compared with the value corresponding to the clock count of n field sections of the standard signal set by the n field clock count setting means. Consequently, even a signal in which the shift is not less than one clock in the unit of n fields although the shift is smaller than one clock and the relationship as the standard signal is satisfied in the unit of one field can be determined to be a non-standard signal.
- An apparatus for identifying standard and non-standard video signals comprises clock generating means, burst extraction pulse generating means, burst extracting means, a band-pass filter, a latch pulse generating means, a holding means group, subtracting means, and determining means.
- the clock generating means has the function of generating a clock of a frequency of b ⁇ f H (b is a predetermined integer, and f H is a horizontal frequency) based on a horizontal synchronizing signal separated from a video signal. It is desirable that the integer b be not less than 500.
- the integer b be not less than 500.
- the horizontal frequency f H is 15.734264 kHz
- the burst frequency f SC is 3.579545 MHz.
- the color burst signal is latched (data-held) at a predetermined timing, defined by a clock, within the period of the color burst portion represented by the burst extraction pulse. That is, one clock section of a sine wave of 3.579545 MHz is latched. Therefore, it is necessary that the frequency of the clock be not less than 3.579545 MHz.
- b ⁇ f H 7.875 MHz
- the clock frequency is approximately twice the burst frequency. It is considered that the clock frequency is a value significant for comparing the held data after n fields.
- the burst extraction pulse generating means has the function of generating a burst extraction pulse corresponding to a period of a color burst portion of the video signal once every field based on the external horizontal synchronizing signal and an external vertical synchronizing signal separated from the video signal, and the clock.
- the burst extracting means has the function of extracting from the video signal a signal portion corresponding to an output period of the burst extraction pulse.
- the band-pass filter whose center frequency is a burst frequency has the function of passing therethrough a burst frequency component of an output signal of the burst extracting means.
- the latch pulse generating means has the function of generating, based on the burst extraction pulse and the clock, a latch pulse at a predetermined timing, defined by the clock, within the period of the color burst portion represented by the burst extraction pulse.
- the holding means group comprises a number, (n+1), (n is a plural number) of holding means connected in series.
- the holding means hold an output of the band-pass filter in response to the latch pulse and transmit the output to succeeding holding means.
- the subtracting means has the function of obtaining a difference between an output signal of the first holding means of the holding means group and an output signal of the (n+1) th holding means.
- the determining means has the function of determining that the video signal is a non-standard signal when an absolute value of an output value of the subtracting means is higher than a predetermined threshold value.
- the level of the color burst signal at a timing, defined by the clock, within the period of the burst extraction pulse is detected in two fields being n fields away from each other, and the difference between the levels in the two fields is compared with the threshold value. Therefore, there is hardly any shift of the phase of the color burst signal between two consecutive fields, so that there is hardly any difference in the level of the color burst signal. Consequently, even in a case where a non-standard signal is erroneously determined to be a standard signal, since the phase shift of the color burst signal is accumulated and the difference in the level of the color burst signal is consequently accumulated, the signal can be determined to be a non-standard signal.
- the latch pulse generating means generates a latch pulse, for example, at the center of the period of the color burst portion represented by the burst extraction pulse, the latch pulse may be generated at any timing other than the center that is defined by the clock of a frequency being a constant multiple b of the horizontal frequency f H .
- the holding means comprises a load hold flip-flop receiving the latch pulse as a load hold input and receiving the clock as a clock input.
- FIG. 1 is a block diagram of a standard and non-standard video signal identifying apparatus according to a first embodiment of the present invention
- FIG. 2 is a timing chart showing the signal levels of components of the standard and non-standard video signal identifying apparatus according to the first embodiment of the present invention
- FIG. 3 is a block diagram of a standard and non-standard video signal identifying apparatus according to a second embodiment of the present invention.
- FIG. 4 is a timing chart showing the signal levels of components of the standard and non-standard video signal identifying apparatus according to the second embodiment of the present invention.
- FIG. 5 is a block diagram of a standard and non-standard video signal identifying apparatus according to a third embodiment of the present invention.
- FIG. 6 is a timing chart showing the signal levels of components of the standard and non-standard video signal identifying apparatus according to the third embodiment of the present invention.
- FIG. 7 is a block diagram of the conventional standard and non-standard video signal identifying apparatus.
- FIG. 1 is a block diagram of a standard and non-standard video signal identifying apparatus according to a first embodiment of the present invention.
- a set-reset latch 100 comprises a set-reset flip-flop using an external reset signal S 1 as the set signal and using an external vertical synchronizing signal S 2 as the reset signal. While the set-reset latch 100 as resetting means has a Q output and an NQ output (the inversion of Q), in this embodiment, the NQ output is used and the Q output is not used.
- the external reset signal Si is supplied from a microcomputer (not shown).
- the external vertical synchronizing signal S 2 is the output of a synchronizing separator circuit (not shown) receiving a video signal as the input.
- a two-input AND gate 101 receives an NQ output signal S 3 of the set-reset latch 100 as one input signal.
- a clock generating circuit 102 as clock generating means generates a clock of a frequency of a ⁇ f SC which is a constant multiple a (a is an integer not less than 1) of a color carrier frequency f SC , based on a color burst signal extracted from a video signal.
- a field clock count setting register 103 sets a value corresponding to the clock count (a ⁇ f SC /f H ) ⁇ (N/2) (f H is the horizontal synchronizing frequency, and N is the number of scanning lines of one frame) of one field section of a standard signal.
- a decode circuit 104 decodes the value set by the field clock count setting register 103 .
- the output S 4 of the decode circuit 104 is input to the two-input AND gate 101 as the other input signal.
- a vertical counter 105 receives the output S 5 of the AND gate 101 as the reset input, and counts the number of clocks of the frequency of a ⁇ f SC generated by the clock generating circuit 102 .
- the output S 6 of the vertical counter 105 is input to the decode circuit 104 to be decoded. Specifically, when the output S 6 of the vertical counter 105 coincides with the value set by the field clock count setting register 103 , a coincidence signal is generated by the decode circuit 104 .
- the vertical counter 105 , the field clock count setting register 103 and the decode circuit 104 constitute a clock counting circuit 114 .
- the clock counting circuit 114 serves as clock counting means.
- the load hold flip-flop 106 as count value holding means receives the output S 6 of the vertical counter 105 as the input signal, receives the clock of a frequency of a ⁇ f SC generated by the clock generating circuit 102 as the clock input, and uses the external vertical synchronizing signal S 2 as the load hold pulse.
- a one-half circuit 113 receives the value set by the field clock count setting register 103 as the input, and outputs a value one-half the received value.
- a subtracter 111 as subtracting means subtracts the value set by the field clock count setting register 103 from the output S 7 of the load hold flip-flop 106 .
- a selector 112 as selecting means selects the output of the subtracter 111 or the output of the load hold flip-flop 106 in accordance with the result of the comparison by the comparator 110 , and outputs the selected one.
- An absolute value circuit 107 receives the output S 8 of the selector 112 as the input, and outputs the absolute value of the input value.
- a threshold value setting register 108 sets a threshold value for identifying standard and non-standard signals.
- a comparator 109 as second determining means compares the output S 9 of the absolute value circuit 107 with the threshold value set by the threshold value setting register 108 .
- FIG. 2 is a timing chart showing the signal levels of the components of FIG. 1 . Reference designations are given in correspondence with those of FIG. 1 .
- Reference designation Si represents the external reset signal.
- Reference designation S 2 represents the external vertical synchronizing signal synchronizing-separated from the video signal.
- Reference designation S 3 represents the NQ output signal of the set-reset latch 100 .
- Reference designation S 4 represents the output signal of the decode circuit 104 .
- Reference designation S 5 represents a counter reset signal output from the two-input AND gate 101 and input to the vertical counter 105 .
- Reference designation S 6 represents the output of the vertical counter 105 and shows a condition where the number of clocks of one field section is counted.
- Reference designation S 7 represents the output of the load hold flip-flop 106 and shows the output of the vertical counter 105 produced when the external vertical synchronizing signal S 2 comes in.
- the external reset signal S 1 is high under normal state and is low when a reset request is provided.
- the external reset signal S 1 is input to the set-reset latch 100 as the set signal.
- As the external vertical synchronizing signal S 2 a negative pulse comes once every field section.
- the external vertical synchronizing signal S 2 is input to the set-reset latch 100 as the reset signal. Therefore, the NQ output signal S 3 of the set-reset latch 100 is set to be low when the external reset signal S 1 is input (low-level input), and is reset to be high when the external vertical synchronizing signal S 2 comes in. That is, the NQ output signal S 3 is output as a low-level signal during the period from the provision of the reset request by the external reset signal S 1 to the first incoming of the external vertical synchronizing signal S 2 .
- the NQ output signal S 3 is input to the two-input AND gate 101 .
- the output signal S 5 of the two-input AND gate 101 is also low.
- the output signal S 5 is input to the vertical counter 105 as the counter reset signal. Therefore, the vertical counter 105 is reset by the NQ output signal S 3 becoming low, and the reset state is canceled by the NQ output signal S 3 recovering to high. Moreover, the vertical counter 105 is temporarily reset in response to the low-level coincidence signal from the decode circuit 104 .
- the output S 6 of the vertical counter 105 becomes 0 at the instant when a reset request is provided by the counter reset signal S 5 , and thereafter, the vertical counter 105 counts up to the vicinity of 910 ⁇ 525/2 which is the clock count of one field section.
- the vertical counter 105 In the field clock count setting register 103 , a value corresponding to the clock count (910 ⁇ 525/2) of one field section of the standard signal is set.
- the output signal S 4 of the decode circuit 104 becomes low when the output S 6 of the vertical counter 105 becomes the set value (910 ⁇ 525/2).
- the output signal S 4 of the decode circuit 104 is input to the two-input AND gate 101 , so that the output S 5 of the two-input AND gate 101 becomes low. Consequently, the vertical counter 105 is reset again. That is, by counting the number of clocks, the vertical counter 105 repetitively changes the output value thereof from 0 to 910 ⁇ 525/2 which is the clock count of one field section of the standard signal like 0, 1, 2, 3, . . .
- the vertical counter 105 can be considered as a scale-of-910 ⁇ 525/2 counter.
- the load hold flip-flop 106 receives the output S 6 of the vertical counter 105 as the input and uses the external vertical synchronizing signal S 2 as the load hold pulse. Therefore, it latches the output S 6 of the vertical counter 105 when the external vertical synchronizing signal S 2 comes in. Therefore, the output S 7 of the load hold flip-flop 106 represents the shift between the vertical synchronizing signal in the standard signal, and the external vertical synchronizing signal S 2 .
- the load hold flip-flop 106 continues outputting 0 as the output S 7 .
- the load hold flip-flop 106 When the clock count of one field section represented by the external vertical synchronizing signal S 2 ′ is higher than that of the standard signal by one clock, the load hold flip-flop 106 outputs 1 as the output S 7 ′ and when the c lock count is higher by two clocks, the load hold flip-flop 106 outputs 2 as the output S 7 ′.
- the vertical counter 105 is reset only when the output S 6 thereof becomes 910 ⁇ 525/2 which is the value set by the field clock count setting register 103 , and the counter reset S 5 is not dependent on the incoming external vertical synchronizing signal. Consequently, the shift of the clock count of one field section is accumulated over a multiplicity of fields. Therefore, even in the case of such a signal, after the counter reset S 5 is supplied, although the output S 7 of the first field is 0, 1 is output when n fields have passed, and 2 is output when 2 ⁇ n fields have passed.
- the load hold flip-flop 106 When the clock count of one field represented by the external vertical synchronizing signal S 2 ′′ is lower than that of the standard signal by one clock, the load hold flip-flop 106 outputs 910 ⁇ 525/2 ⁇ 1 as the output S 7 ′′, and when the clock count is lower by two clocks, the load hold flip-flop 106 outputs 910 ⁇ 525/2 ⁇ 2 as the output S 7 ′′.
- the output S 7 of the load hold flip-flop 106 is larger, a low-level signal is output as the control signal of the selector 112 , and when the output S 7 is smaller, a high-level signal is output as the control signal.
- the comparator 110 When the output S 7 of the load hold flip-flop 106 is 0, since the output S 7 is smaller than the value set by the field clock count setting register 103 , the comparator 110 outputs a high-level signal, and the selector 112 selects the output S 7 of the load hold flip-flop 106 .
- the subtracter 111 subtracts the clock count (910 ⁇ 525/2) of one field section of the standard signal set by the field clock count setting register 103 from the output S 7 of the load hold flip-flop 106 .
- the value of the shift is calculated by the subtracter 111 . That is, when the clock count of one field section represented by the external vertical synchronizing signal S 2 is lower than that of the standard signal by one clock, since the output S 7 of the load hold flip-flop 106 is 910 ⁇ 525/2 ⁇ 1, the output of the subtracter 111 is
- the selector 112 selects the output of the subtracter 111 when the control signal is low, and selects the output S 7 of the load hold flip-flop 106 when the control signal is high. That is, the output S 8 of the selector 112 expresses the shift of the external vertical synchronizing signal S 2 from the standard signal with a positive or negative value.
- the external vertical synchronizing signal S 2 is larger than the standard signal by one clock, 1 is output, and when the signal S 2 is smaller by one clock, ⁇ 1 is output.
- the positive or negative value representing the shift is converted into an absolute value by the absolute value circuit 107 , and is input to the comparator 109 .
- the comparator 109 compares the absolute value of the shift obtained by the absolute value circuit 107 with the threshold value set by the threshold value setting register 108 .
- the output of the comparator 109 is the result of the standard and non-standard signal identification.
- the absolute value of the shift is not more than the threshold value
- the output OUT of the comparator 109 becomes, for example, low and the video signal is determined to be a standard signal.
- the output OUT of the comparator 109 becomes, for example, high and the video signal is determined to be a non-standard signal.
- the threshold value is set at a given value such as 1 or 2 in the threshold value setting register 108 by input means such as a microcomputer or a switch.
- the vertical counter 105 in a system using a signal being a constant multiple a of the color carrier frequency f SC as the system clock, only when the output S 6 of the vertical counter 105 becomes the clock count of the one field section of the standard signal which is the value set by the field clock count setting register 103 , the vertical counter 105 is reset so that its count value returns to 0, and is not dependent on the incoming external vertical synchronizing signal S 2 . Therefore, the shift of the clock count of one field section is accumulated over a multiplicity of fields. Consequently, even a signal in which the shift is not less than one clock in the unit of n fields although the relationship as the standard signal is satisfied in the unit of one field like the output of a digital still camera can be determined to be a non-standard signal.
- FIG. 3 is a block diagram of a standard and non-standard video signal identifying apparatus according to a second embodiment of the present invention.
- a pulse generating circuit 200 as pulse thinning out means receives an external vertical synchronizing signal S 21 as the input, thins out the external vertical synchronizing signal S 21 , and outputs the thinned out signal once every n fields (n is a plural number).
- a two-output AND gate 201 receives the output S 22 of the pulse generating circuit 200 and an external reset signal as the inputs.
- the external reset signal is supplied from a microcomputer (not shown), and the external vertical synchronizing signal S 21 is the output of a synchronizing separator circuit (not shown) receiving a video signal as the input.
- n for example, 8 or 16 is considered.
- a clock generating circuit 202 as clock generating means generates a clock of a frequency of a ⁇ f SC (a is an integer not less than 1) which is a constant multiple a of the color carrier frequency f SC , based on a color burst signal extracted from the video signal.
- a vertical counter 203 as clock counting means receives the output of the two-input AND gate 201 as the reset input, and receives the clock of a frequency of a ⁇ f SC generated by the clock generating circuit 202 as the clock input.
- An n field clock count setting register 204 as n field clock count setting means sets the clock count of n field sections (a ⁇ f SC /f H ) ⁇ (N/2) ⁇ n (f H is the horizontal synchronizing frequency, and N is the number of scanning lines of one frame).
- a load hold flip-flop 209 as count value holding means holds the output S 23 of the vertical counter 203 with the output of the pulse generating circuit 200 as the load hold pulse.
- a subtracter 205 as subtracting means subtracts the value set by the n field clock count setting register 204 from the output of the load hold flip-flop 209 .
- An absolute value circuit 206 obtains the absolute value of the output of the subtracter 205 .
- a threshold value setting register 207 sets a threshold value for identifying standard and non-standard signals.
- a comparator 208 as determining means compares the output of the absolute value circuit 206 with the threshold value set by the threshold value setting register 207 .
- FIG. 4 is a timing chart showing the signal levels of the components of FIG. 3 .
- reference designation S 21 represents the external vertical synchronizing signal.
- Reference designation S 22 represents the output of the pulse generating circuit 200 outputting the external vertical synchronizing signal once every n fields.
- Reference numeral S 23 represents the output of the vertical counter 203 and shows that the number of clocks of n field sections is counted.
- the external vertical synchronizing signal S 21 comes in as a negative pulse once every field, and is input to the pulse generating circuit 200 .
- the pulse generating circuit 200 thins out the external vertical synchronizing signal S 21 input once every field, and outputs the thinned out signal once every n fields.
- the external reset signal is high under normal state and is low when a reset request is provided.
- the output S 22 of the pulse generating circuit 200 and the external reset signal are input to the two-input AND gate 201 , and a counter reset signal is output from the two-input AND gate 201 .
- the counter reset signal is a negative signal.
- the counter reset signal is output as a low-level signal when a reset request is provided by the external reset signal, and is output as a low-level signal once every n fields in response to the output S 22 of the pulse generating circuit 200 .
- the vertical counter 203 receives the clock of a frequency of a ⁇ f SC generated by the clock generating circuit 202 as the clock input, and receives the output of the two-input AND gate 201 as the counter reset signal. Therefore, when there is no reset request by the external reset signal, the vertical counter 203 is reset once every n fields, and counts the number of clocks of n field sections.
- the output S 23 of the vertical counter 203 becomes 0 at the instant when a reset request is provided by the counter reset signal, and the vertical counter 203 counts up to the vicinity of 910 ⁇ 525/2 ⁇ n which is the clock count of n fields. Then, by the output pulse of the pulse generating circuit 200 , the output S 23 of the vertical counter 203 produced immediately before the counter 203 is reset is latched by the load hold flip-flop 209 .
- n field clock count setting register 204 a value corresponding to the clock count (910 ⁇ 525/2 ⁇ n) of n field sections of the standard signal is set.
- the subtracter 205 subtracts the value set in the n field clock count setting register 204 from the output of the load hold flip-flop 209 . That is, the output of the subtracter 205 expresses the shift of the clock count of n field sections represented by the external vertical synchronizing signal S 21 from the standard signal.
- the output of the subtracter 205 when the clock count of n field sections represented by the incoming external vertical synchronizing signal is always the same as the clock count (910 ⁇ 525/2 ⁇ n) of n field sections of the standard signal, the output of the subtracter 205 always represents 0. When the clock count of n field sections represented by the incoming external vertical synchronizing signal is higher by one clock than the clock count (910 ⁇ 525/2 ⁇ n) of n field sections of the standard signal, the output of the subtracter 205 represents 1. When the clock count of n field sections represented by the incoming external vertical synchronizing signal is lower by one clock than the clock count (910 ⁇ 525/2 ⁇ n) of n field sections of the standard signal, the output of the subtracter 205 represents ⁇ 1.
- the output of the subtracter 205 representing the shift is converted into an absolute value by the absolute value circuit 206 , and is input to the comparator 208 .
- the comparator 208 compares the absolute value of the shift obtained by the absolute value circuit 206 with the threshold value set by the threshold value setting register 207 .
- the output of the comparator 208 is the result of the standard and non-standard signal identification.
- the absolute value of the shift is not more than the threshold value
- the output OUT of the comparator 208 becomes, for example, low and the video signal is determined to be a standard signal.
- the output OUT of the comparator 208 becomes, for example, high and the video signal is determined to be a non-standard signal.
- the threshold value is set at a given value such as 1 or 2 in the threshold value setting register 207 by input means such as a microcomputer or a switch.
- the vertical counter 203 counts the number of clocks of n field sections, and the clock count is compared with the clock count of n field sections of the standard signal set by the n field clock count setting register 204 . Consequently, even a signal in which the shift is one clock in the unit of n fields although the relationship as the standard signal is satisfied in the unit of one field can be determined to be a non-standard signal.
- FIG. 5 is a block diagram of a standard and non-standard video signal identifying apparatus according to a third embodiment of the present invention.
- a clock generating circuit 300 as clock generating means receives as the input an external horizontal synchronizing signal S 31 separated from a video signal, and generates a clock of a frequency of b ⁇ f H (b is, for example, an integer not less than 500) being a constant multiple b of the horizontal frequency f H .
- a burst extraction pulse generating circuit 301 as burst extraction pulse generating means receives the external horizontal synchronizing signal S 31 , an external vertical synchronizing signal S 32 and the clock of a frequency of b ⁇ f H as the inputs, and outputs only a color burst portion of the video signal as a high-level signal once every field.
- a burst extracting circuit 302 as burst extracting means receives the output S 34 of the burst extraction pulse generating circuit 301 , the video signal S 33 and the clock of a frequency of b ⁇ f H as the inputs.
- the integer b be not less than 500.
- the horizontal frequency f H is 15.734264 kHz
- the burst frequency f SC is 3.579545 MHz.
- the color burst signal is latched (data-held) at a predetermined timing, defined by a clock, within the period of the color burst portion represented by the burst extraction pulse. That is, one clock section of a sine wave of 3.579545 MHz is latched. Therefore, it is necessary that the frequency of the clock be not less than 3.579545 MHz.
- b ⁇ f H 7.875 MHz
- the video signal S 33 is a digital signal supplied from an input source such as a digital still camera, a VTR, a DVD or a tuner.
- the external horizontal synchronizing signal S 31 and the external vertical synchronizing signal S 32 are outputs of a synchronizing separator circuit (not shown) receiving the video signal 33 as the input.
- a band-pass filter 303 is a digital filter receiving the output of the burst extracting circuit 302 as the input and using the burst frequency as the center frequency.
- a V (vertical) latch pulse generating circuit 304 as latch pulse generating means receives the output S 34 of the burst extraction pulse generating circuit 301 and the clock of a frequency of b ⁇ f H as the inputs, and generates a pulse of a width of one clock at the center of the color burst portion represented by the output S 34 of the burst extraction pulse generating circuit 301 .
- the V latch pulse generating circuit 304 generates a pulse at the center of the color burst portion once every field (one vertical period).
- the pulse generated position is not limited to the center of the color burst portion, but the pulse may be generated at any position of the color burst portion that is defined by the clock of a frequency of b ⁇ f H .
- a load hold flip-flop group 305 as holding means comprises a number, (n+1), (n is a plural number) of load hold flip-flops connected in series.
- Each load hold flip-flop uses the output S 36 of the V latch pulse generating circuit 304 as the load hold pulse, and receives the clock generated by the clock generating circuit 300 as the clock input.
- the output S 35 of the band-pass filter 303 is supplied to the input of the first load hold flip-flop 305 A of a number, n, of flip-flops connected in series.
- a subtracter 306 as subtracting means receives as the inputs the output of the first load hold flip-flop 305 A of the number, n, of flip-flops of the load hold flip-flop group 305 connected in series, and the output of the (n+1)th load hold flip-flop 305 B, and obtains the difference between the two input signals.
- An absolute value circuit 307 receives the output of the subtracter 306 as the input.
- a threshold value setting register 308 sets a threshold value for identifying standard and non-standard signals.
- a comparator 309 as determining means compares the output of the absolute value circuit 307 with the threshold value set by the threshold value setting register 308 .
- FIG. 6 is a timing chart showing principal signal levels of components of FIG. 5 .
- Reference designation S 32 represents the external vertical synchronizing signal.
- Reference numeral S 33 represents the video signal.
- Reference numeral S 34 represents the output of the burst extraction pulse generating circuit 301 , that is, the burst extraction pulse only the color burst portion of which becomes high once every field.
- Reference numeral S 35 represents a burst signal extracted from the video signal S 33 once every field.
- Reference numeral S 36 represents the pulse of a width of one clock at a frequency of b ⁇ f H at the center of the burst extraction pulse S 34 .
- the external horizontal synchronizing signal S 31 is input to the clock generating circuit 300 , and is multiplied into a frequency of b ⁇ f H being a constant multiple b of the horizontal frequency f H .
- the external horizontal synchronizing signal S 31 , the external vertical synchronizing signal S 32 and the clock of a frequency of b ⁇ f H are input.
- the burst extraction pulse generating circuit 301 outputs once every field the burst extraction pulse S 34 only the color burst portion of the video signal of which is high.
- the burst extraction pulse generating circuit 301 comprises, for example, a vertical counter using the external vertical synchronizing signal S 32 as the reset pulse and using the external horizontal synchronizing signal S 31 as the count up pulse, and a horizontal counter using the external horizontal synchronizing signal S 31 as the reset pulse and using the clock of a frequency of b ⁇ f H as the count up pulse.
- the burst extraction pulse generating circuit 301 outputs a pulse when to which line of one field the burst extraction pulse S 34 is output is set by the microcomputer and the vertical counter reaches the set number of lines, and when the position in one line where the burst signal is multiplexed is set by the microcomputer and the horizontal counter reaches the set position.
- the burst extracting circuit 302 To the burst extracting circuit 302 , the video signal S 33 , the burst extraction pulse S 34 and the clock of a frequency of b ⁇ f H are input, and the color burst portion of the burst extraction pulse S 34 shown by the high-level section is extracted from the digital video signal S 33 . Then, only the burst signal S 35 is extracted at the band-pass filter 303 whose center frequency is the burst frequency.
- the V latch pulse generating circuit 304 To the V latch pulse generating circuit 304 , the burst extraction pulse S 34 and the clock of a frequency of b ⁇ f H are input, and the V latch pulse generating circuit 304 generates the V latch pulse S 36 with a width of one clock (frequency b ⁇ f H ), for example, at the center of the burst extraction pulse S 34 .
- Each of the load hold flip-flops of the load hold flip-flop group 305 uses the output S 36 of the V latch pulse generating circuit 304 as the load hold pulse, and receives as the clock input the clock of a frequency of b ⁇ f H multiplied by the clock generating circuit 300 .
- the burst signal S 35 from the band-pass filter 303 is supplied as the input signal.
- each load hold flip-flop represents the value of the burst signal at the center of the burst portion represented by the output S 36 of the V latch pulse generating circuit, and is output once every field.
- the output of the first load hold flip-flop 305 A represents the value at the center of the burst portion in the newest field.
- the output of the (n+1) th load hold flip-flop 305 B represents the value at the center of the burst portion in the field preceding the newest field by n fields.
- the subtracter 306 receives as the inputs the output of the first load hold flip-flop 305 A of the load hold flip-flop group 305 and the output of the (n+1) th load hold flip-flop 305 B, and obtains the difference therebetween, thereby outputting the shift of the burst signal in n fields.
- the positive or negative value representing the shift is converted into an absolute value by the absolute value circuit 307 , and is input to the comparator 309 .
- the comparator 309 compares the absolute value of the shift obtained by the absolute value circuit 307 with the threshold value set by the threshold value setting register 308 .
- the output of the comparator 309 is the result of the standard and non-standard signal identification.
- the output OUT of the comparator 309 becomes, for example, low and the video signal is determined to be a standard signal.
- the output OUT of the comparator 309 becomes, for example, high and the video signal is determined to be a non-standard signal.
- the threshold value is set at a given value in the threshold value setting register 308 by input means such as a microcomputer or a switch.
- the value at the center of the color burst is compared in two fields being n fields away from each other. Therefore, even in a case where a non-standard signal is erroneously determined to be a standard signal because the difference in the value at the center of the color burst is small when the comparison is made between two consecutive fields, the signal can be determined to be a non-standard signal because the shift of the value at the center of the color burst is accumulated in the unit of n fields.
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- Processing Of Color Television Signals (AREA)
- Synchronizing For Television (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP11-113837 | 1999-04-21 | ||
JP11383799 | 1999-04-21 |
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US6545725B1 true US6545725B1 (en) | 2003-04-08 |
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US09/553,153 Expired - Lifetime US6545725B1 (en) | 1999-04-21 | 2000-04-20 | Apparatus for identifying standard and non-standard video signals |
Country Status (5)
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US (1) | US6545725B1 (en) |
EP (1) | EP1047272A3 (en) |
KR (1) | KR100642083B1 (en) |
CN (3) | CN1126359C (en) |
MY (1) | MY118932A (en) |
Cited By (6)
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US20010013893A1 (en) * | 1999-12-23 | 2001-08-16 | Koppe Rudolf Pieter | Compatible camera system |
US20030107673A1 (en) * | 2001-12-12 | 2003-06-12 | Yasunori Sato | Video signal detecting circuit for adjusting SYNC signals with a mean difference of the number of pixels from a standard |
US20040119890A1 (en) * | 2002-12-20 | 2004-06-24 | Silicon Integrated Systems Corp. | Method for detecting video frame types with adaptive thresholds |
US20040207752A1 (en) * | 2003-04-15 | 2004-10-21 | Silicon Integrated Systems Corp. | Method for detecting video frame types with median filtering |
US20050052577A1 (en) * | 2003-09-10 | 2005-03-10 | Seth-Smith Nigel James | Video signal format detector and generator system and method |
US20070024749A1 (en) * | 2005-07-26 | 2007-02-01 | Samsung Electronics Co., Ltd. | Video processing apparatus and method |
Families Citing this family (2)
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JP3796751B2 (en) | 2002-05-02 | 2006-07-12 | ソニー株式会社 | Video signal processing apparatus and method, recording medium, and program |
JP5783101B2 (en) | 2012-03-22 | 2015-09-24 | 新日鐵住金株式会社 | Steel for nitriding |
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- 2000-04-19 EP EP00108545A patent/EP1047272A3/en not_active Withdrawn
- 2000-04-19 MY MYPI20001670A patent/MY118932A/en unknown
- 2000-04-20 US US09/553,153 patent/US6545725B1/en not_active Expired - Lifetime
- 2000-04-21 CN CN00108896A patent/CN1126359C/en not_active Expired - Fee Related
- 2000-04-21 CN CNB2005100844966A patent/CN100423540C/en not_active Expired - Fee Related
- 2000-04-21 KR KR1020000021263A patent/KR100642083B1/en not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
CN1245015C (en) | 2006-03-08 |
KR100642083B1 (en) | 2006-11-13 |
CN1271232A (en) | 2000-10-25 |
CN100423540C (en) | 2008-10-01 |
KR20000071769A (en) | 2000-11-25 |
EP1047272A3 (en) | 2008-07-30 |
CN1126359C (en) | 2003-10-29 |
CN1533154A (en) | 2004-09-29 |
EP1047272A2 (en) | 2000-10-25 |
CN1722777A (en) | 2006-01-18 |
MY118932A (en) | 2005-02-28 |
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