KR950005062B1 - Apparatus for eliminating frequency varying bit noise of a tv receiver - Google Patents

Abstract

The circuit automatically tracks the frequency of the beat noise in a television receiver, and eliminates the beat noise by varing the filtering frequency. The circuit comprises a frequency discriminator (11), connected between a video detector (4) and a video processor (5) to detect the beat frequency and provide a frequency variable filter (12) with the voltage relating to the beat frequency, the frequency variable filter (12) for converting the filtering frequency into the beat frequency, and a delay circuit (13) to delay the output of the video detector for the delay time in the frequency discriminator and the frequency variable filter.

Description

Frequency Variable Bit Noise Reduction Circuit of Television Receiver

1 is a system circuit block diagram of a television video signal processing system equipped with a conventional bit noise removing circuit.

2 is a system circuit block diagram of a television video signal processing system equipped with a bit noise removing circuit according to the present invention.

3 is a reference diagram illustrating the frequency discriminating unit in FIG. 2 in more detail.

FIG. 4 is a reference diagram illustrating the frequency variable filter unit in FIG. 2 in more detail.

(A) and (b) of FIG. 5 are NAND gate output signal waveforms when the frequency sweep sampling signal and the 3MHZ bit are generated according to the present invention.

* Explanation of symbols for main parts of the drawings

11 frequency discrimination unit 12 frequency variable filter unit

13 delay circuit 111 AD converter

112: horizontal blanking selector 113: register

114: sweep sampling signal generator 115: frequency voltage converter

116: frequency counter

The present invention relates to a bit noise removing circuit of an image signal in a television receiver, which is particularly capable of automatically detecting and removing a changing frequency even when the bit noise frequency is changed in such a circuit.

A system circuit block of a video signal processing system of a general television receiver is shown in FIG.

In this case, the television signal received from the antenna 1 is connected to the video intermediate frequency band 3, the adjacent channel trap 7 and the audio trap 8 via the tuner 2, and the video intermediate frequency signal ( The output signal of 3) is applied to the CRT via the image detector 4 and the image processor 5, and the output signals of the image detector 4 are respectively the color signal processor 9 and the synchronization signal processor ( 10 is connected to the image processing unit 5 and the deflection coil DY of the CRT 6.

In the conventional system, the television signal received by the antenna 1 is tuned by the tuner 2, and one broadcast signal desired by the viewer is output.

This output signal is amplified by the intermediate frequency through the video intermediate frequency stage (3) and applied to the adjacent channel trap (7) to attenuate the adjacent channel frequency of 47.15MHZ signal to about -40dB level to prevent interference of adjacent channel signals. It was applied to the voice trap 8 to attenuate the 41.25MHZ signal, which is the voice signal frequency, to about -50 dB level to remove 920KHZ bit noise of the voice signal and the color carrier.

The output of the image intermediate frequency stage 3 is detected through the image detection stage 4, and the output thereof is input to the image processor 5, the color signal processor 9, and the synchronization signal processor 10, respectively. Synchronous separation processing.

The demodulated color signal is added to the luminance signal through the image processor 5 to reproduce the original image signal, and the synchronization signal is applied to the CRT 6 to synchronize the television signal.

However, in such a conventional circuit, since the means for removing the bit noise can only remove the bit noise having a predetermined specific frequency by the adjacent channel trap 7 or the like, for example, an Amateur radio station is operated in the vicinity. When the frequency fluctuates due to poor viewing conditions, such as when using high-frequency generating electronic devices, when bit noise other than the specific frequency set in the bit noise trap occurs, it cannot be removed. There was a problem.

It is an object of the present invention to automatically track the changed frequency to remove the bit noise even if the bit frequency is changed in a video device such as a television receiver, so as to improve such a conventional problem, thereby providing a clearer picture quality in such a device. To provide a bit noise elimination circuit to ensure that

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 shows a system circuit block diagram of a bit noise cancellation circuit according to the present invention.

Here, the television signal received at the antenna 1 is connected so as to be applied to the video intermediate frequency band 3, the adjacent channel trap 7 and the audio trap 8 via the tuner 2, and the video intermediate frequency signal ( The output signal of 3) is applied to the CRT via the image detector 4 and the image processor 5, and the output signals of the image detector 4 are respectively the color signal processor 9 and the synchronization signal processor ( 10. In a television receiver connected to the image processing unit 5 and the deflection coil DY of the CRT 6 through 10), the image detection unit 4 and the image processing unit 5 are connected to each other. A frequency discriminating unit 11 for discriminating the bit frequency mixed into the output video signal of the image detecting unit 4, and an output voltage which is proportional to the frequency from the output side of the frequency discriminating unit 11 Frequency variable filter that receives the input and changes the filtering frequency to bit frequency (12) and the output side of the image detector (4) to delay the output signal of the image detector (4) by the processing delay time of the frequency discriminator (11) and the variable frequency filter (12). It consists of the delay circuit part 13 which matches.

In addition, the frequency discriminating unit 11 is connected to an analog / digital (AD) converter 111 for converting the analog output signal of the video detector 4 into a digital signal as shown in FIG. A horizontal blanking selector 112 for selecting a predetermined number of data among the signals in the horizontal blanking period without a signal, and a register for temporarily storing a digital signal outputted from the horizontal blanking selector 112 and output therefrom ( 113, a plurality of inverters I ₁ -In for alternately inverting the output of the register 113, followed by the output of the register 113, and the output of the register 113 are 1 0 1 0 1 0 A NAND gate N ₁ for outputting a low signal only when the signal is in a state, a swept sampling signal generator 114 for generating a sampling signal fs whose frequency is swept and outputting it to the A / D converter 111; To count the frequency of the sampling signal fs Books and the NAND gate (N _1), a frequency counter 116 to stop the counting operation when the output is low, can be implemented as a frequency to voltage converter 115 which outputs a voltage proportional to the frequency.

In addition, the frequency variable filter unit 12 may be implemented in a configuration in which the voltage variable large capacitor V ₀ and the coil L are connected in parallel as shown in FIG. 4.

When the present invention configured as described above will be described with reference to Figure 5 the operation and effect.

When the TV signal received from the antenna 1 is input to the input terminal IN of the frequency discriminating unit 11 when the video signal outputted through the tuner 2, the image intermediate frequency band 3, and the image detector 4 is input. After converting to a digital signal through the AD converter 111 of FIG. 3, a predetermined number of data are selected from the signal of the horizontal blanking period without an image signal by the horizontal blanking selector 112 and applied to the register 113.

In the register 113, the data is temporarily stored, and then an inverted signal is alternately applied to the input terminal of the NAND gate n ₁ through the inverters I ₁ -In _one by one through the output terminal.

That is, the logic low (0) signal is output from the NAND gate (N ₁ ) output terminal only when the output of the register 113 is in the state of 0 1 0 1 0 .... Will output a signal.

At this time, when the sampling signal fs whose frequency is swept from the sweep sampling signal generator 114 is applied to the AD converter 111, and the digital signal is converted in analog, the sampling signal at the instant when the NAND gate N ₁ output becomes low Since the frequency of (fs) becomes the bit frequency of the input video signal, the frequency of the bit frequency mixed in the video signal can be detected.

That is, as shown in (a) of FIG. 5, the output of the NAND gate N ₁ when the 3MHZ bit is generated in the frequency sweep sampling signal state is shown as (b) of FIG.

On the other hand, the frequency counter 116 always keeps counting the frequency of the sampling signal fs and stops counting when the low output signal is received from the NAND gate N ₁ . The corresponding value is output to the frequency voltage converter 115.

Next, when the frequency voltage converter 115 outputs a voltage proportional to the frequency and inputs the voltage to the frequency variable filter unit 12 as shown in FIG. 2, the voltage variable capacitor V ₀ and the coil L as shown in FIG. 4. ), And the filtering frequency is changed to the bit frequency, so that the bit noise is removed corresponding to the bit noise with the changed frequency.

In the case where there are a plurality of bit signals, a plurality of frequency variable filter units 12 are connected in parallel, and a plurality of frequency variable filter units 12 are controlled by a plurality of frequency information obtained from the frequency discriminating unit 11, respectively. You may.

At this time, the delay circuit unit 13 serves to match the timing by delaying the input signal by the processing delay time of the frequency discriminating unit 11 and the frequency variable filter unit 12.

Since the operation relationship of the other circuit portion is the same as that of FIG. 1, it is omitted to avoid redundant description.

As described above, in the present invention, even if the bit frequency is changed due to a bad relationship in the surrounding electromagnetic environment in a television receiver or a VCR, the tracking frequency is automatically changed to the changed frequency to automatically change the filtering frequency. By removing the noise, a better picture can be provided.

Claims (3)

Image intermediate frequency stage (3) for a double frequency amplification processing of a television signal of a specific channel received by the tuner (2) and an image detection stage (4) and an image processor (5) connected to the output thereof to detect an image signal. In a video signal processing circuit of a television equipped with a light source and the like, it is connected between the video detector 4 and the video processor 5 to sample a bit frequency mixed in the output video signal of the video detector 4. The frequency discriminating unit 11 detects the signal and generates a voltage corresponding to a predetermined frequency and provides the frequency variable filter unit 12 to the frequency variable filtering unit 12, and the frequency discriminating unit 11 is connected to the output of the frequency discriminating unit 11. A frequency variable filter unit 12 for receiving a frequency contrast voltage corresponding to a predetermined bit frequency provided by the variable frequency filter bit 12 and connected to an output side of the image detector 4 to detect an image 4. Of The output signal frequency determination unit 11 and the frequency variable filter unit 12, processing delays by the delay time delay circuit 13 to the yirwojyeo the features removed TV frequency variable bit in the receiver noise as in the circuit to match the timing of the. The frequency converter (11) according to claim 1, wherein the frequency discriminator (11) is connected to the output side of the video detector (4) and converts the video output analog signal here into a digital signal, and the AD converter (111). A horizontal blanking selector 112 that selects a predetermined number of data from the horizontal blanking period signal that is connected to the output side of the horizontal blanking period without an image signal, and is connected to the output side of the horizontal blanking selector 112, and then to a predetermined number of data of the horizontal blanking period. Register 113 for temporarily storing the data, and the output logic of the register 113 is alternately inverted so that a bit frequency that is not normal among the multiple output logics of the register 113 can be detected. gate plurality of inverters (I ₁ -In) to provide a (N1), and a plurality of NAND's provided with an inverter (I ₁ -In) in a consecutive output from frequency counter 116 is an active output to the bit frequency in case of A sweep sampling signal generator 114 connected to the input N1, the input side of the AD converter 111 and the frequency counter 116 to provide a sampling signal fs for detecting a bit frequency; The frequency counter 116 continuously counts the frequency of the sampling signal fs provided from the generator 114 and sets the bit frequency to the active output provided from the NAND gate N1 to provide the frequency voltage converter 115 with the frequency counter 116. Frequency variable bit noise of a television receiver, characterized in that it consists of a frequency voltage converter 115 which generates a voltage proportional to the predetermined bit frequency provided by the frequency counter 116 and provides the voltage variable filter unit 12 to the frequency variable filter unit 12. Removal circuit. The method of claim 1. A plurality of frequency variable filter units 12 which are connected to the output side of the delay circuit unit 13 in consideration of the case where there are a plurality of bit frequency signals, and an input side and an image of the plurality of frequency variable filter units 12. A television receiver comprising a plurality of frequency discriminators 11 connected between an output side of the detector 4 and generating a plurality of bit frequencies, respectively, and provided to the plurality of frequency variable filter units 12. Frequency variable bit noise cancellation circuit.