US6476457B2 - Semiconductor device with drift layer - Google Patents

Semiconductor device with drift layer Download PDF

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US6476457B2
US6476457B2 US09/729,081 US72908100A US6476457B2 US 6476457 B2 US6476457 B2 US 6476457B2 US 72908100 A US72908100 A US 72908100A US 6476457 B2 US6476457 B2 US 6476457B2
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well
layer
field oxide
semiconductor device
drift layer
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US20010000288A1 (en
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Han Su Oh
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MagnaChip Semiconductor Ltd
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Definitions

  • the present invention relates to a semiconductor device, and more particularly, to a semiconductor device and fabrication method thereof which increases a junction breakdown voltage and improves a snap-back characteristic thereof.
  • An integrated circuit unified within a single chip with regard to a control function and a driving function is referred to as a smart power device.
  • An output terminal of the smart power device includes a high power transistor operating at a high voltage of about 15-80V, and a logic unit includes a normal transistor operating at a low voltage of about 5V.
  • Such smart power devices are employed to drive a display apparatus such as LCD (liquid crystal display), and HDTV (high definition TV).
  • a high power transistor of the smart power device is formed such that a lightly doped region (or, called as drift region) which is lightly doped between a drain and a channel region, compared to the drain.
  • FIG. 1 is a cross-sectional view illustrating a high power semiconductor device unit of a smart power device according to the conventional art. Therein, a p-channel transistor is shown but an n-channel transistor has the same structure. That is, the conductive type of impurities or ions is opposite and the structure remains identical.
  • an n-type well 110 is formed in a p-type semiconductor substrate 100 .
  • a plurality of field oxide layers 101 are formed on the p-type semiconductor substrate 100 and the n-type well 110 .
  • a gate electrode 102 is formed to cover a predetermine portion of the upper surface of the field oxide layer 101 and the n-type well 110 .
  • p+ type impurity layers 103 a , 103 b are formed in the n-type well 110 at the sides of the gate electrode 102 .
  • the p+ impurity layer 103 a is formed adjacent to an end portion of the gate electrode 102 , and the p+ type impurity layer 103 a is formed at an end portion of the field oxide layer 101 with the gate electrode 102 laid thereon and spaced from the end portion of the gate electrode 102 .
  • the p+ type impurity layer 103 b distanced from the gate electrode 102 is a drain.
  • a p-type impurity layer 104 which is a lightly doped impurity layer in comparison to the source/drain 103 a , 103 b is extended from a certain point between the field oxide film 101 and the source 103 a to an end portion of the drain 103 b and covers the drain 103 b from bottom and side surfaces thereof.
  • the junction depth of the drift layer 104 remains constant at respective sides of the source and drain.
  • the drift layer serves as a buffer layer when a high electric field is applied to the drain side, thereby preventing a junction breakdown and restraining a hot carrier effect from generating.
  • the semiconductor device as shown in FIG. 1 has disadvantages. That is, since the junction depth of the drift layer is constant, the thickness D 1 of the drift layer beneath the drain is relatively thin compared to the thickness D 2 of the drift layer beneath the field oxide layer. Accordingly, when high power is applied to the drain region, the electric field loaded at the drain is not sufficiently relieved. Therefore, a junction breakdown easily occurs at the drain region, and the breakdown voltage is relatively low. Further, the snap-back voltage is low due to the hot carrier generation, thereby deteriorating reliability of the semiconductor device.
  • the present invention is directed to overcoming the conventional disadvantages.
  • a semiconductor device which includes a semiconductor substrate having a first conductive type impurity, a well having a second conductive type impurity formed in a predetermined region of the semiconductor substrate, a plurality of field oxide layer formed on an upper surface of the semiconductor substrate having the first conductive type impurity and the well having the second conductive type impurity, a gate electrode formed on corresponding portions of the field oxide layer and the well, and a lightly doped first impurity region formed in the well between the gate electrode and the first conductive type impurity region and surrounding the first conductive impurity region from sides and lower portions thereof and relatively lightly doped in comparison to the first conductive type impurity region, wherein the device includes a junction of the lightly doped first impurity region surrounding the first conductive type impurity region is relatively deep in comparison to a junction of the lightly doped first impurity region below the field oxide layer.
  • a semiconductor device fabrication method which includes the steps of forming a second conductive type well on a predetermined portion of a first conductive type semiconductor substrate, forming a plurality of field oxide layers on the semiconductor substrate and the well, forming a mask on the semiconductor substrate and the well so as to form a first conductive impurity layer in the well, forming a first conductive type impurity layer by implanting and annealing first conductive type impurity ions in the well using the mask, removing the mask, forming a gate electrode on the field oxide layer, the drift layer and the well, and forming a source in the well adjacent to an end portion of the gate electrode and a drain in the first conductive type impurity layer at an end portion of the field oxide layer adjacent to the other end portion of the gate electrode.
  • FIG. 1 is a cross-sectional view illustrating the structure of a conventional semiconductor device
  • FIG. 2 is a cross-sectional view illustrating the structure of a semiconductor device according to the present invention.
  • FIGS. 3A-3E are cross-sectional views illustrating the fabrication method of a semiconductor device according to the present invention.
  • FIG. 2 is a cross-sectional view of the semiconductor device according to the present invention, wherein a p-channel transistor is shown. In case of n-channel transistor, a conductive type is opposite but the structure is identical to that of P-channel transistor.
  • an n-type well 210 is formed in a p-type semiconductor substrate 200 .
  • a plurality of field oxide layers 201 are formed on the p-type semiconductor substrate 200 and the n-type well 210 .
  • a gate electrode 202 is formed on the n-type well 210 and the field oxide layer 201 provided on the n-type well 210 . That is, a portion of the gate electrode 202 is slantingly stepped and stretched on the field oxide layer 201 and another portion thereof is formed on the n-type well 210 .
  • p+ type impurity layers 203 a , 203 b In the n-type well 210 at each side of the gate electrode 202 there are formed p+ type impurity layers 203 a , 203 b , wherein the p+ type impurity layer 203 a is formed adjacent to an end portion of the gate electrode on the n-type well 210 and the p+ type impurity layer 203 b is formed spaced from another end portion of the gate electrode on the field oxide layer 210 . That is, it is formed adjacent to an end portion of the field oxide layer 201 having the gate electrode 202 formed thereon.
  • the p+ type impurity layers 203 a , 203 b are source and drain, respectively.
  • a p-type impurity layer 204 serving as a lightly doped impurity layer with a light density compared to the source and drain 203 a , 203 b is formed in the n-type well 210 , whereby it is extended from a point between the field oxide layer 201 and the source 203 a to an outside portion of the drain 203 b .
  • the lightly doped impurity layer 204 surrounds the drain 203 b.
  • the lightly doped impurity layer 204 is referred to as a drift layer and an pn junction depth of the drift layer 204 is relatively deep compared to the other portion near the end portion of the field oxide layer 201 and the drain 203 b , and the pn junction is shallower than the drain proximity at the central portion of the field oxide layer.
  • an n-type impurity layer 205 In the n-type well 210 adjacent to the source 203 c there is formed an n-type impurity layer 205 .
  • the n-type impurity layer 205 is a contact portion of the n-type well 210 .
  • the semiconductor device since there is provided a sufficient junction depth of the drift layer at a proximity of the drain and near an edge portion of the field oxide layer where electric field is strong, it is possible to improve a snap-back current characteristic by sufficiently relieving the electric field of the drain region and restraining a hot carrier generation while increasing a junction breakdown voltage.
  • a pad oxide layer 301 is formed on a p-type semiconductor substrate 300 and a silicon nitride pattern 302 is formed on the pad oxide layer 301 .
  • the silicon nitride pattern 302 is formed so as to correspond to an active region of the semiconductor substrate.
  • the silicon nitride pattern 302 serves as an anti-oxide layer in an oxidation process of the semiconductor substrate.
  • the semiconductor substrate 300 is oxidated using the silicon nitride pattern 302 as a mask so as to form a thick field oxide layer 303 on a portion where the silicon nitride pattern 302 is not covered. Then, the silicon nitride pattern 302 is removed and an n-well mask 304 is covered over the semiconductor substrate 300 with the exception of a portion saved for an n-type well formation.
  • the n-well mask 304 is used as a mask and n-type ions, for example, As or P ions are implanted into the semiconductor substrate 300 . As shown in FIG. 3B, a portion 305 along a dotted line in the semiconductor substrate 300 is implanted by As or P ions.
  • the semiconductor substrate 300 is annealed and the n-type ions implanted into the semiconductor substrate is driven-in toward a lower portion of the semiconductor substrate, thereby forming an n-type well 306 as shown in FIG. 3 C.
  • the n-well mask 304 is removed and a drift mask 307 is formed so as to form a lightly doped p-type impurity region serving as a drift region.
  • p-type ion for example, B ions are implanted into the semiconductor substrate 300 .
  • the B ions are implanted along the dotted line 308 and the ion implantation is shallow at a lower portion of the field oxide layer 303 , whereas it is deep at the active region where it is not covered with the field oxide layer 303 . That is, at the portion where the field oxide layer is covered, the ion implantation is interrupted due to a thick field oxide layer 303 during the ion implantation so that the ions are not deep implanted into the semiconductor substrate.
  • a gate oxide layer 310 is formed on a portion of the active region of the semiconductor substrate 300 .
  • a conductive layer for example, a polysilicon layer is formed on an upper front surface of the semiconductor substrate 300 .
  • a mask (not shown) is formed to form a source/drain, that is, a p+ type impurity layer, and a source 313 a and a drain 313 b are formed in the n-type well 306 at each side portion of the gate electrode 312 using the mask.
  • the drain 313 b is formed in the drift region 309 , especially at a deep junction of the drift region 309 .
  • an n+ type impurity layer 314 is formed adjacent to the source 313 b.
  • a junction depth of the drift layer is locally different.
  • the junction beneath the drain region and the field oxide layer where electric field is concentrated is provided to be deeper than the junction of other portions, so that the electric field is sufficiently relieved, thereby preventing a hot carrier generation and heightening a junction breakdown voltage.
  • a field oxide layer was conventionally formed after forming a drift layer but the field oxide layer according to the present invention is formed and then an ion implantation is carried out for the drift layer formation. Since the semiconductor device fabrication method according to the present invention does not change the conventional process in form of increasing processing steps, there is not required an additional cost or introduction of new apparatus, so that the conventional equipment can be employed without change. Further, a mask is not used to form a locally different junction of a drift layer and instead a field oxide layer is used in self-alignment, thereby facilitating the process.

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Abstract

A semiconductor device includes a semiconductor substrate having a first conductive type impurity, a well having a second conductive type impurity formed in a predetermined region of the semiconductor substrate, a plurality of field oxide layer formed on an upper surface of the semiconductor substrate having the first conductive type impurity and the well having the second conductive type impurity, a gate electrode formed on corresponding portions of the field oxide layer and the well, and a lightly doped first impurity region formed in the well between the gate electrode and the first conductive type impurity region and surrounding the first conductive impurity region from sides and lower portions thereof and relatively lightly doped in comparison to the first conductive type impurity region. The device includes a junction of the lightly doped first impurity region surrounding the first conductive type impurity region is relatively deep in comparison to a junction of the lightly doped first impurity region below the field oxide layer, thereby sufficiently relieving electric field and preventing a hot carrier generation and heightening a junction breakdown voltage.

Description

This application is a Divisional of application Ser. No. 09/326,218 filed Jun. 3, 1999 now U.S. Pat. No. 6,177,321.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and fabrication method thereof which increases a junction breakdown voltage and improves a snap-back characteristic thereof.
2. Description of the Background Art
An integrated circuit unified within a single chip with regard to a control function and a driving function is referred to as a smart power device. An output terminal of the smart power device includes a high power transistor operating at a high voltage of about 15-80V, and a logic unit includes a normal transistor operating at a low voltage of about 5V. Such smart power devices are employed to drive a display apparatus such as LCD (liquid crystal display), and HDTV (high definition TV).
A high power transistor of the smart power device is formed such that a lightly doped region (or, called as drift region) which is lightly doped between a drain and a channel region, compared to the drain.
FIG. 1 is a cross-sectional view illustrating a high power semiconductor device unit of a smart power device according to the conventional art. Therein, a p-channel transistor is shown but an n-channel transistor has the same structure. That is, the conductive type of impurities or ions is opposite and the structure remains identical.
As shown therein, an n-type well 110 is formed in a p-type semiconductor substrate 100. A plurality of field oxide layers 101 are formed on the p-type semiconductor substrate 100 and the n-type well 110. A gate electrode 102 is formed to cover a predetermine portion of the upper surface of the field oxide layer 101 and the n-type well 110. In the n-type well 110 at the sides of the gate electrode 102 there are formed p+ type impurity layers 103 a, 103 b. the p+ impurity layer 103 a is formed adjacent to an end portion of the gate electrode 102, and the p+ type impurity layer 103 a is formed at an end portion of the field oxide layer 101 with the gate electrode 102 laid thereon and spaced from the end portion of the gate electrode 102.
The p+ type impurity layer 103 b distanced from the gate electrode 102 is a drain. Also, a p-type impurity layer 104 which is a lightly doped impurity layer in comparison to the source/ drain 103 a, 103 b is extended from a certain point between the field oxide film 101 and the source 103 a to an end portion of the drain 103 b and covers the drain 103 b from bottom and side surfaces thereof. Also, the junction depth of the drift layer 104 remains constant at respective sides of the source and drain. The drift layer serves as a buffer layer when a high electric field is applied to the drain side, thereby preventing a junction breakdown and restraining a hot carrier effect from generating.
However, the semiconductor device as shown in FIG. 1 has disadvantages. That is, since the junction depth of the drift layer is constant, the thickness D1 of the drift layer beneath the drain is relatively thin compared to the thickness D2 of the drift layer beneath the field oxide layer. Accordingly, when high power is applied to the drain region, the electric field loaded at the drain is not sufficiently relieved. Therefore, a junction breakdown easily occurs at the drain region, and the breakdown voltage is relatively low. Further, the snap-back voltage is low due to the hot carrier generation, thereby deteriorating reliability of the semiconductor device.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming the conventional disadvantages.
Therefore, it is an object of the present invention to provide a semiconductor device wherein a drift layer of a portion of a drain region and a field oxide layer edge having a strong electric field is formed deeper than a drift layer of the other portion thereof, thereby sufficiently relieving electric field and preventing a hot carrier generation as well as improving product reliability.
To achieve the above-described object, there is provided a semiconductor device according to the present invention which includes a semiconductor substrate having a first conductive type impurity, a well having a second conductive type impurity formed in a predetermined region of the semiconductor substrate, a plurality of field oxide layer formed on an upper surface of the semiconductor substrate having the first conductive type impurity and the well having the second conductive type impurity, a gate electrode formed on corresponding portions of the field oxide layer and the well, and a lightly doped first impurity region formed in the well between the gate electrode and the first conductive type impurity region and surrounding the first conductive impurity region from sides and lower portions thereof and relatively lightly doped in comparison to the first conductive type impurity region, wherein the device includes a junction of the lightly doped first impurity region surrounding the first conductive type impurity region is relatively deep in comparison to a junction of the lightly doped first impurity region below the field oxide layer.
Further, to achieve the above-described object, there is provided a semiconductor device fabrication method according to the present invention which includes the steps of forming a second conductive type well on a predetermined portion of a first conductive type semiconductor substrate, forming a plurality of field oxide layers on the semiconductor substrate and the well, forming a mask on the semiconductor substrate and the well so as to form a first conductive impurity layer in the well, forming a first conductive type impurity layer by implanting and annealing first conductive type impurity ions in the well using the mask, removing the mask, forming a gate electrode on the field oxide layer, the drift layer and the well, and forming a source in the well adjacent to an end portion of the gate electrode and a drain in the first conductive type impurity layer at an end portion of the field oxide layer adjacent to the other end portion of the gate electrode.
The features and advantages of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific example, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein:
FIG. 1 is a cross-sectional view illustrating the structure of a conventional semiconductor device;
FIG. 2 is a cross-sectional view illustrating the structure of a semiconductor device according to the present invention; and
FIGS. 3A-3E are cross-sectional views illustrating the fabrication method of a semiconductor device according to the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 2 is a cross-sectional view of the semiconductor device according to the present invention, wherein a p-channel transistor is shown. In case of n-channel transistor, a conductive type is opposite but the structure is identical to that of P-channel transistor.
As shown therein, an n-type well 210 is formed in a p-type semiconductor substrate 200. A plurality of field oxide layers 201 are formed on the p-type semiconductor substrate 200 and the n-type well 210. A gate electrode 202 is formed on the n-type well 210 and the field oxide layer 201 provided on the n-type well 210. That is, a portion of the gate electrode 202 is slantingly stepped and stretched on the field oxide layer 201 and another portion thereof is formed on the n-type well 210. In the n-type well 210 at each side of the gate electrode 202 there are formed p+ type impurity layers 203 a, 203 b, wherein the p+ type impurity layer 203 a is formed adjacent to an end portion of the gate electrode on the n-type well 210 and the p+ type impurity layer 203 b is formed spaced from another end portion of the gate electrode on the field oxide layer 210. That is, it is formed adjacent to an end portion of the field oxide layer 201 having the gate electrode 202 formed thereon. The p+ type impurity layers 203 a, 203 b are source and drain, respectively. Also, a p-type impurity layer 204 serving as a lightly doped impurity layer with a light density compared to the source and drain 203 a, 203 b is formed in the n-type well 210, whereby it is extended from a point between the field oxide layer 201 and the source 203 a to an outside portion of the drain 203 b. Specifically, the lightly doped impurity layer 204 surrounds the drain 203 b.
The lightly doped impurity layer 204 is referred to as a drift layer and an pn junction depth of the drift layer 204 is relatively deep compared to the other portion near the end portion of the field oxide layer 201 and the drain 203 b, and the pn junction is shallower than the drain proximity at the central portion of the field oxide layer. In the n-type well 210 adjacent to the source 203 c there is formed an n-type impurity layer 205. The n-type impurity layer 205 is a contact portion of the n-type well 210.
In the semiconductor device according to the present invention, since there is provided a sufficient junction depth of the drift layer at a proximity of the drain and near an edge portion of the field oxide layer where electric field is strong, it is possible to improve a snap-back current characteristic by sufficiently relieving the electric field of the drain region and restraining a hot carrier generation while increasing a junction breakdown voltage.
The fabrication method of a semiconductor device according to the present invention will now be described.
First, as shown in FIG. 3A, a pad oxide layer 301 is formed on a p-type semiconductor substrate 300 and a silicon nitride pattern 302 is formed on the pad oxide layer 301. The silicon nitride pattern 302 is formed so as to correspond to an active region of the semiconductor substrate. The silicon nitride pattern 302 serves as an anti-oxide layer in an oxidation process of the semiconductor substrate.
Next, as shown in FIG. 3B, the semiconductor substrate 300 is oxidated using the silicon nitride pattern 302 as a mask so as to form a thick field oxide layer 303 on a portion where the silicon nitride pattern 302 is not covered. Then, the silicon nitride pattern 302 is removed and an n-well mask 304 is covered over the semiconductor substrate 300 with the exception of a portion saved for an n-type well formation. The n-well mask 304 is used as a mask and n-type ions, for example, As or P ions are implanted into the semiconductor substrate 300. As shown in FIG. 3B, a portion 305 along a dotted line in the semiconductor substrate 300 is implanted by As or P ions.
Then, the semiconductor substrate 300 is annealed and the n-type ions implanted into the semiconductor substrate is driven-in toward a lower portion of the semiconductor substrate, thereby forming an n-type well 306 as shown in FIG. 3C. The n-well mask 304 is removed and a drift mask 307 is formed so as to form a lightly doped p-type impurity region serving as a drift region. Using the drift mask 307, p-type ion, for example, B ions are implanted into the semiconductor substrate 300.
As shown in FIG. 3C, the B ions are implanted along the dotted line 308 and the ion implantation is shallow at a lower portion of the field oxide layer 303, whereas it is deep at the active region where it is not covered with the field oxide layer 303. That is, at the portion where the field oxide layer is covered, the ion implantation is interrupted due to a thick field oxide layer 303 during the ion implantation so that the ions are not deep implanted into the semiconductor substrate.
As shown in FIG. 3E, a gate oxide layer 310 is formed on a portion of the active region of the semiconductor substrate 300. Next, a conductive layer, for example, a polysilicon layer is formed on an upper front surface of the semiconductor substrate 300. Then, a mask (not shown) is formed to form a source/drain, that is, a p+ type impurity layer, and a source 313 a and a drain 313 b are formed in the n-type well 306 at each side portion of the gate electrode 312 using the mask. The drain 313 b is formed in the drift region 309, especially at a deep junction of the drift region 309. Then, an n+ type impurity layer 314 is formed adjacent to the source 313 b.
As described above, in the high power semiconductor device according to the present invention, a junction depth of the drift layer is locally different. In particular, the junction beneath the drain region and the field oxide layer where electric field is concentrated is provided to be deeper than the junction of other portions, so that the electric field is sufficiently relieved, thereby preventing a hot carrier generation and heightening a junction breakdown voltage.
A field oxide layer was conventionally formed after forming a drift layer but the field oxide layer according to the present invention is formed and then an ion implantation is carried out for the drift layer formation. Since the semiconductor device fabrication method according to the present invention does not change the conventional process in form of increasing processing steps, there is not required an additional cost or introduction of new apparatus, so that the conventional equipment can be employed without change. Further, a mask is not used to form a locally different junction of a drift layer and instead a field oxide layer is used in self-alignment, thereby facilitating the process.
As the present invention may be embodied in various forms without departing from the spirit of the essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.

Claims (30)

What is claimed is:
1. A semiconductor device comprising:
a semiconductor substrate having a first conductive type impurity;
a well having a second conductive type impurity formed in a predetermined region of the semiconductor substrate;
a plurality of outer first conductive type impurity regions formed in predetermined regions of the well;
a plurality of field oxide layers formed on an upper surface of the semiconductor substrate having the first conductive type impurity and the well having the second conductive type impurity;
a gate electrode formed on corresponding portions of the field oxide layer and the well; and
a lightly doped first impurity region formed in the well between one of the field oxide layers and at least one of the plurality of outer first conductive type impurity regions and surrounding an inner first conductive type impurity region from sides and lower portions thereof and relatively lightly doped in comparison to the outer and the inner first conductive type impurity regions, wherein a portion of the lightly doped first impurity region formed in the well below a portion of the gate electrode is thicker and deeper into the well from the top of the well than a portion of the lightly doped first impurity region formed in the well below one of the field oxide layers, but not beneath the gate electrode,
wherein the portion of the lightly doped first impurity region surrounding the inner first conductive type impurity region is relatively deep into the well from the top of the well in comparison to a portion of the lightly doped first impurity region below the field oxide layer.
2. The semiconductor device of claim 1, wherein the outer first conductive type impurity region is formed adjacent to an end portion of the gate electrode, and wherein the inner first conductive type impurity region is spaced from the other end portion of the gate electrode.
3. The semiconductor device of claim 2, wherein one of the first conductive type impurity regions is formed within the well at an end portion of the field oxide layer having the gate electrode provided thereon.
4. The semiconductor device of claim 1, wherein the first conductive type and the second conductive type are opposite from each other.
5. The semiconductor device of claim 1, wherein one of the first conductive type impurity regions is surrounded by the lightly doped first impurity region and comprises a drain.
6. A semiconductor device, comprising:
a second conductive type well formed on a predetermined portion of a first conductive type semiconductor substrate;
a plurality of field oxide layers formed on the semiconductor substrate and the well;
a first conductive impurity layer formed in the well, the first conductive impurity layer being formed by implanting and annealing first conductive type impurity ions in the well using a mask to form a drift layer and then removing the mask;
a gate electrode formed on each of the plurality of field oxide layers, the drift layer and the well; and
a source formed in the well adjacent to an end portion of the gate electrode and a drain formed in the first conductive type impurity layer at an end portion of the field oxide layer adjacent to the other end portion of the gate electrode, wherein a first distance between an interface between the drift layer and one of the field oxide layers and an interface, disposed below the one of the field oxide layers, between the drift layer and the well is less than a second distance between an interface between the drift layer and a gate oxide layer and an interface disposed below the gate oxide layer interface with the drift layer between the drift layer and the well.
7. The semiconductor device of claim 6, wherein the drift region has a light impurity ion density in comparison to the drain.
8. The semiconductor device of claim 6, wherein the drift layer is of a different conductivity than the well.
9. The semiconductor device of claim 6, wherein the drift layer and the impurity layer are of the same conductivity.
10. The semiconductor device of claim 6, wherein each of the interfaces extends horizontally parallel to a top surface of the semiconductor substrate.
11. A semiconductor device, comprising:
a well formed on a semiconductor substrate;
a plurality of field oxide layers formed on the semiconductor substrate and the well;
a drift layer formed beneath the plurality of field oxide layers; and
an impurity layer formed between two of the plurality of field oxide layers, wherein a first distance between an interface between the drift layer and one of the two field oxide layers and an interface, disposed below the one of the field oxide layers, between the drift layer and the well is substantially equal to a second distance between an interface between the drift layer and the impurity layer and an interface, disposed below the impurity layer, between the drift layer and the well while the first and second distances are less than a third distance between the interface of the drift layer and a gate oxide layer and an interface, disposed below the gate oxide layer interface with the drift layer, between the drift layer and the well.
12. The semiconductor device of claim 11, wherein the drift layer is of a different conductivity than the well.
13. The semiconductor device of claim 11, wherein the drift layer and the impurity layer are of the same conductivity.
14. The semiconductor device of claim 11, wherein the drift layer has a light impurity ion density in comparison to the impurity layer.
15. The semiconductor device of claim 11, further comprising gate electrodes formed on each of the plurality of field oxide layers.
16. The semiconductor device of claim 11, wherein the impurity layer is a drain and a source is formed on an opposite side of each of the two field oxide layers to the source.
17. The semiconductor device of claim 11, wherein a third distance between an interface between the drift layer and the other of the two field oxide layers and an interface, disposed below the other of the two field oxide layers, between the drift layer and the well is substantially equal to the first distance.
18. The semiconductor device of claim 11, wherein each of the interfaces extends horizontally parallel to a top surface of the semiconductor substrate.
19. A semiconductor device, comprising:
a well formed on a semiconductor substrate;
a plurality of field oxide layers formed on the semiconductor substrate and the well;
a drift layer formed beneath the plurality of field oxide layers by implanting and annealing impurity ions in the well using a mask and then removing the mask;
an impurity layer formed between two of the plurality of field oxide layers; and
a gate electrode formed on each of the plurality of field oxide layers, the drift layer and the well, wherein a first distance between an interface between the drift layer and one of the two field oxide layers and an interface, disposed below the one of the field oxide layers, between the drift layer and the well is substantially equal to a second distance between an interface between the drift layer and the impurity layer and an interface, disposed below the impurity layer, between the drift layer and the well while the first and second distances are less than a third distance between the interface of the drift layer and a gate oxide layer and an interface, disposed below the gate oxide layer interface with the drift layer, between the drift layer and the well.
20. The semiconductor device of claim 19, wherein the well is a second conductive type and the drift layer is a first conductive type.
21. The semiconductor device of claim 19, wherein the drift layer and the impurity layer are of the same conductivity.
22. The semiconductor device of claim 19, wherein the drift layer has a light impurity ion density in comparison to the impurity layer.
23. The semiconductor device of claim 19, wherein the impurity layer is a drain and the a source is formed on an opposite side of each of the two field oxide layers to the source.
24. The semiconductor device of claim 19, wherein a third distance between an interface between the drift layer and the other of the two field oxide layers and an interface, disposed below the other of the two field oxide layers, between the drift layer and the well is substantially equal to the first distance.
25. The semiconductor device of claim 19, wherein each of the interfaces extends horizontally parallel to a top surface of the semiconductor substrate.
26. The semiconductor device of claim 1, wherein a portion of the lightly doped first impurity region below both the gate electrode and one of the field oxide layers is thicker than a portion of the lightly doped first impurity region below one of the field oxide layers without the gate electrode on the top of the one of the field oxide layers.
27. The semiconductor device of claim 1, wherein the portion of the lightly doped first impurity region below a gate oxide layer is thicker than the portion of the lightly doped first impurity region below the field oxide layer.
28. The semiconductor device of claim 1, wherein the portion of the lightly doped first impurity region below a gate oxide layer is deeper in the well than the portion of the lightly doped first impurity region below the field oxide layer and not below the gate electrode.
29. The semiconductor device of claim 1, wherein a first distance between a gate oxide layer interface with the lightly doped impurity region and the interface between the lightly doped impurity region and the well is approximately greater than or equal to a second distance between the interface of the field oxide and the lightly doped impurity region and the interface between the lightly doped impurity region and the well.
30. The semiconductor device of claim 6, wherein a third distance between an interface between the drift layer and the drain and the interface disposed below the drain between the drift layer and the well is less than the second distance.
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040033666A1 (en) * 2002-08-14 2004-02-19 Williams Richard K. Isolated complementary MOS devices in epi-less substrate
US20040063291A1 (en) * 2002-09-29 2004-04-01 Williams Richard K. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
US20060057784A1 (en) * 2004-09-16 2006-03-16 Jun Cai Enhanced resurf HVPMOS device with stacked hetero-doping RIM and gradual drift region
US20070278573A1 (en) * 2004-02-27 2007-12-06 Martin Knaipp High-Voltage Pmos Transistor
US20070278568A1 (en) * 2006-05-31 2007-12-06 Advanced Analogic Technologies, Inc. High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same
USRE42232E1 (en) 2001-09-21 2011-03-22 Intellectual Ventures I Llc RF chipset architecture
US9257504B2 (en) 2002-09-29 2016-02-09 Advanced Analogic Technologies Incorporated Isolation structures for semiconductor devices
US20190305128A1 (en) * 2018-04-03 2019-10-03 Vanguard International Semiconductor Corporation Semiconductor structure and method for forming the same
US10490637B2 (en) 2016-07-08 2019-11-26 Samsung Electronics Co., Ltd. Semiconductor devices including an active fin and a drift region

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7939420B2 (en) * 2002-08-14 2011-05-10 Advanced Analogic Technologies, Inc. Processes for forming isolation structures for integrated circuit devices
US7667268B2 (en) * 2002-08-14 2010-02-23 Advanced Analogic Technologies, Inc. Isolated transistor
US8089129B2 (en) * 2002-08-14 2012-01-03 Advanced Analogic Technologies, Inc. Isolated CMOS transistors
US7902630B2 (en) * 2002-08-14 2011-03-08 Advanced Analogic Technologies, Inc. Isolated bipolar transistor
US8513087B2 (en) * 2002-08-14 2013-08-20 Advanced Analogic Technologies, Incorporated Processes for forming isolation structures for integrated circuit devices
US20080197408A1 (en) * 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolated quasi-vertical DMOS transistor
US7834421B2 (en) * 2002-08-14 2010-11-16 Advanced Analogic Technologies, Inc. Isolated diode
US7956391B2 (en) 2002-08-14 2011-06-07 Advanced Analogic Technologies, Inc. Isolated junction field-effect transistor
JP4387119B2 (en) * 2003-03-27 2009-12-16 三菱電機株式会社 Semiconductor device
JP4777676B2 (en) * 2005-03-23 2011-09-21 本田技研工業株式会社 Junction type semiconductor device and method of manufacturing junction type semiconductor device
JP2008004649A (en) * 2006-06-21 2008-01-10 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
KR100788376B1 (en) * 2006-09-13 2008-01-02 동부일렉트로닉스 주식회사 Semiconductor Device Formation Method
US7737526B2 (en) * 2007-03-28 2010-06-15 Advanced Analogic Technologies, Inc. Isolated trench MOSFET in epi-less semiconductor sustrate
US8030731B2 (en) * 2007-03-28 2011-10-04 Advanced Analogic Technologies, Inc. Isolated rectifier diode
EP2244299A1 (en) * 2009-04-22 2010-10-27 STMicroelectronics S.r.l. MOS transistor for power applications and corresponding integrated circuit and manufacturing method
US8461621B2 (en) * 2010-03-09 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus of forming bipolar transistor device
KR101450436B1 (en) * 2013-03-04 2014-10-13 주식회사 동부하이텍 Method for forming well of semiconductor device
US9263574B1 (en) * 2014-11-07 2016-02-16 Vanguard International Semiconductor Corporation Semiconductor device and method for fabricating the same
US10008593B2 (en) * 2014-12-19 2018-06-26 Mediatek Inc. Radio frequency semiconductor device
KR102389294B1 (en) * 2015-06-16 2022-04-20 삼성전자주식회사 Semiconductor device and fabricating method thereof
WO2022092035A1 (en) * 2020-10-29 2022-05-05 ローム株式会社 Semiconductor device
CN114388363B (en) * 2022-03-24 2022-06-07 晶芯成(北京)科技有限公司 Semiconductor device and manufacturing method thereof

Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4527182A (en) * 1980-09-19 1985-07-02 Nippon Electric Co., Ltd. Semiconductor photoelectric converter making excessive charges flow vertically
US4902636A (en) 1988-01-18 1990-02-20 Matsushita Electric Works, Ltd. Method for manufacturing a depletion type double-diffused metal-oxide semiconductor field effect transistor device
US5019520A (en) * 1989-11-29 1991-05-28 Mitsubishi Denki Kabushiki Kaisha Method for preparing a high mobility, lightly-doped channel mis-type FET with reduced latch up and punchthrough
US5138420A (en) * 1989-11-24 1992-08-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having first and second type field effect transistors separated by a barrier
US5283200A (en) * 1991-07-30 1994-02-01 Sony Corporation Method of fabricating complementary semiconductor device
US5304833A (en) * 1989-09-12 1994-04-19 Mitsubishi Electric Corporation Complementary MOS semiconductor device
US5313080A (en) * 1991-02-13 1994-05-17 Gold Star Electron Co., Ltd. Structure of a CCD image sensor particularly on an interline transfer method
US5384279A (en) * 1988-09-09 1995-01-24 U.S. Philips Corporation Method of manufacturing a semiconductor device comprising a silicon body in which semiconductor regions are formed by ion implantations
US5401671A (en) * 1991-07-17 1995-03-28 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device
US5411901A (en) 1993-02-01 1995-05-02 Power Integrations, Inc. Method of making high voltage transistor
US5478759A (en) * 1992-11-26 1995-12-26 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device with retrograde wells
US5510643A (en) * 1993-01-06 1996-04-23 Sharp Kabushiki Kaisha High voltage MOS transistor
US5512495A (en) 1994-04-08 1996-04-30 Texas Instruments Incorporated Method of manufacturing extended drain resurf lateral DMOS devices
US5608253A (en) * 1995-03-22 1997-03-04 Advanced Micro Devices Inc. Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits
US5719081A (en) * 1995-11-03 1998-02-17 Motorola, Inc. Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant
US5821145A (en) * 1994-07-28 1998-10-13 Lg Semicon Co., Ltd. Method for isolating elements in a semiconductor device
US5918117A (en) * 1996-09-25 1999-06-29 Samsung Electronics, Co., Ltd. Method for manufacturing semiconductor device having an ESD protection region
US5949112A (en) * 1998-05-28 1999-09-07 Lucent Technologies Inc. Integrated circuits with tub-ties
US5963799A (en) * 1998-03-23 1999-10-05 Texas Instruments - Acer Incorporated Blanket well counter doping process for high speed/low power MOSFETs
US5966599A (en) * 1996-05-21 1999-10-12 Lsi Logic Corporation Method for fabricating a low trigger voltage silicon controlled rectifier and thick field device
US6069048A (en) * 1998-09-30 2000-05-30 Lsi Logic Corporation Reduction of silicon defect induced failures as a result of implants in CMOS and other integrated circuits
US6111291A (en) * 1998-06-26 2000-08-29 Elmos Semiconductor Ag MOS transistor with high voltage sustaining capability

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235668A (en) * 1994-02-23 1995-09-05 Fuji Electric Co Ltd MOS type transistor
US5747368A (en) * 1996-10-03 1998-05-05 Mosel Vitelic Inc. Process for manufacturing CMOS device

Patent Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4527182A (en) * 1980-09-19 1985-07-02 Nippon Electric Co., Ltd. Semiconductor photoelectric converter making excessive charges flow vertically
US4902636A (en) 1988-01-18 1990-02-20 Matsushita Electric Works, Ltd. Method for manufacturing a depletion type double-diffused metal-oxide semiconductor field effect transistor device
US5384279A (en) * 1988-09-09 1995-01-24 U.S. Philips Corporation Method of manufacturing a semiconductor device comprising a silicon body in which semiconductor regions are formed by ion implantations
US5304833A (en) * 1989-09-12 1994-04-19 Mitsubishi Electric Corporation Complementary MOS semiconductor device
US5138420A (en) * 1989-11-24 1992-08-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having first and second type field effect transistors separated by a barrier
US5019520A (en) * 1989-11-29 1991-05-28 Mitsubishi Denki Kabushiki Kaisha Method for preparing a high mobility, lightly-doped channel mis-type FET with reduced latch up and punchthrough
US5313080A (en) * 1991-02-13 1994-05-17 Gold Star Electron Co., Ltd. Structure of a CCD image sensor particularly on an interline transfer method
US5401671A (en) * 1991-07-17 1995-03-28 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device
US5283200A (en) * 1991-07-30 1994-02-01 Sony Corporation Method of fabricating complementary semiconductor device
US5478759A (en) * 1992-11-26 1995-12-26 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device with retrograde wells
US5510643A (en) * 1993-01-06 1996-04-23 Sharp Kabushiki Kaisha High voltage MOS transistor
US5411901A (en) 1993-02-01 1995-05-02 Power Integrations, Inc. Method of making high voltage transistor
US5512495A (en) 1994-04-08 1996-04-30 Texas Instruments Incorporated Method of manufacturing extended drain resurf lateral DMOS devices
US5821145A (en) * 1994-07-28 1998-10-13 Lg Semicon Co., Ltd. Method for isolating elements in a semiconductor device
US5608253A (en) * 1995-03-22 1997-03-04 Advanced Micro Devices Inc. Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits
US5719081A (en) * 1995-11-03 1998-02-17 Motorola, Inc. Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant
US5966599A (en) * 1996-05-21 1999-10-12 Lsi Logic Corporation Method for fabricating a low trigger voltage silicon controlled rectifier and thick field device
US5918117A (en) * 1996-09-25 1999-06-29 Samsung Electronics, Co., Ltd. Method for manufacturing semiconductor device having an ESD protection region
US5963799A (en) * 1998-03-23 1999-10-05 Texas Instruments - Acer Incorporated Blanket well counter doping process for high speed/low power MOSFETs
US5949112A (en) * 1998-05-28 1999-09-07 Lucent Technologies Inc. Integrated circuits with tub-ties
US6111291A (en) * 1998-06-26 2000-08-29 Elmos Semiconductor Ag MOS transistor with high voltage sustaining capability
US6069048A (en) * 1998-09-30 2000-05-30 Lsi Logic Corporation Reduction of silicon defect induced failures as a result of implants in CMOS and other integrated circuits

Cited By (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE42232E1 (en) 2001-09-21 2011-03-22 Intellectual Ventures I Llc RF chipset architecture
US20050142724A1 (en) * 2002-08-14 2005-06-30 Advanced Analogic Technologies, Inc. Method of fabricating isolated semiconductor devices in epi-less substrate
US7449380B2 (en) 2002-08-14 2008-11-11 Advanced Analogic Technologies, Inc. Method of fabricating isolated semiconductor devices in epi-less substrate
US20050014324A1 (en) * 2002-08-14 2005-01-20 Advanced Analogic Technologies, Inc. Method of fabricating isolated semiconductor devices in epi-less substrate
US7666756B2 (en) 2002-08-14 2010-02-23 Advanced Analogic Technologies, Inc. Methods of fabricating isolation structures in epi-less substrate
US6900091B2 (en) * 2002-08-14 2005-05-31 Advanced Analogic Technologies, Inc. Isolated complementary MOS devices in epi-less substrate
US20050142792A1 (en) * 2002-08-14 2005-06-30 Advanced Analogic Technologies, Inc. Method of fabricating isolated semiconductor devices in epi-less substrate
US20050014329A1 (en) * 2002-08-14 2005-01-20 Advanced Analogic Technologies, Inc. Method of fabricating isolated semiconductor devices in epi-less substrate
US20050142791A1 (en) * 2002-08-14 2005-06-30 Advanced Analogic Technologies, Inc. Method of fabricating isolated semiconductor devices in epi-less substrate
US20050158939A1 (en) * 2002-08-14 2005-07-21 Advanced Analogic Technologies, Inc Method of fabricating isolated semiconductor devices in epi-less substrate
US7276431B2 (en) 2002-08-14 2007-10-02 Advanced Analogic Technologies, Inc. Method of fabricating isolated semiconductor devices in epi-less substrate
US7445979B2 (en) 2002-08-14 2008-11-04 Advanced Analogic Technologies, Inc. Method of fabricating isolated semiconductor devices in epi-less substrate
US20060223257A1 (en) * 2002-08-14 2006-10-05 Advanced Analogic Technologies, Inc. Method Of Fabricating Isolated Semiconductor Devices In Epi-Less Substrate
US7422938B2 (en) 2002-08-14 2008-09-09 Advanced Analogic Technologies, Inc. Method of fabricating isolated semiconductor devices in epi-less substrate
US20040033666A1 (en) * 2002-08-14 2004-02-19 Williams Richard K. Isolated complementary MOS devices in epi-less substrate
US7329583B2 (en) 2002-08-14 2008-02-12 Advanced Analogic Technologies, Inc. Method of fabricating isolated semiconductor devices in epi-less substrate
US7279378B2 (en) 2002-08-14 2007-10-09 Advanced Analogic Technologies, Inc. Method of fabricating isolated semiconductor devices in epi-less substrate
US20080061377A1 (en) * 2002-09-29 2008-03-13 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US9257504B2 (en) 2002-09-29 2016-02-09 Advanced Analogic Technologies Incorporated Isolation structures for semiconductor devices
US7211863B2 (en) * 2002-09-29 2007-05-01 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US7279399B2 (en) * 2002-09-29 2007-10-09 Advanced Analogic Technologies, Inc. Method of forming isolated pocket in a semiconductor substrate
US20070272986A1 (en) * 2002-09-29 2007-11-29 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US7608895B2 (en) 2002-09-29 2009-10-27 Advanced Analogic Technologies, Inc. Modular CMOS analog integrated circuit and power technology
US10074716B2 (en) 2002-09-29 2018-09-11 Skyworks Solutions (Hong Kong) Limited Saucer-shaped isolation structures for semiconductor devices
US20080023762A1 (en) * 2002-09-29 2008-01-31 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US7202536B2 (en) 2002-09-29 2007-04-10 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US9905640B2 (en) 2002-09-29 2018-02-27 Skyworks Solutions (Hong Kong) Limited Isolation structures for semiconductor devices including trenches containing conductive material
US20080061375A1 (en) * 2002-09-29 2008-03-13 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US7265434B2 (en) 2002-09-29 2007-09-04 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US20080061376A1 (en) * 2002-09-29 2008-03-13 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
US7605432B2 (en) 2002-09-29 2009-10-20 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US20040063291A1 (en) * 2002-09-29 2004-04-01 Williams Richard K. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
US20080067585A1 (en) * 2002-09-29 2008-03-20 Advanced Analogic Technologies, Inc. High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same
US20080116513A1 (en) * 2002-09-29 2008-05-22 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US7135738B2 (en) * 2002-09-29 2006-11-14 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US20060157818A1 (en) * 2002-09-29 2006-07-20 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US7745883B2 (en) 2002-09-29 2010-06-29 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US7573105B2 (en) 2002-09-29 2009-08-11 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US7576391B2 (en) 2002-09-29 2009-08-18 Advanced Analogic Technologies, Inc. High-voltage lateral trench MOSFET
US7602023B2 (en) 2002-09-29 2009-10-13 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US7602024B2 (en) 2002-09-29 2009-10-13 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US7605433B2 (en) 2002-09-29 2009-10-20 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US6855985B2 (en) * 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
US7663203B2 (en) * 2004-02-27 2010-02-16 Austriamicrosystems Ag High-voltage PMOS transistor
US20070278573A1 (en) * 2004-02-27 2007-12-06 Martin Knaipp High-Voltage Pmos Transistor
US7180132B2 (en) * 2004-09-16 2007-02-20 Fairchild Semiconductor Corporation Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region
US20060057784A1 (en) * 2004-09-16 2006-03-16 Jun Cai Enhanced resurf HVPMOS device with stacked hetero-doping RIM and gradual drift region
US7605428B2 (en) 2006-05-31 2009-10-20 Advanced Analogic Technologies, Inc. High-voltage depletion mode MOSFET
US7683426B2 (en) 2006-05-31 2010-03-23 Advanced Analogic Technologies, Inc. High-voltage lateral DMOS device with diode clamp
US7683453B2 (en) 2006-05-31 2010-03-23 Advanced Analogic Technologies, Inc. Edge termination region for high-voltage bipolar-CMOS-DMOS integrated circuit devices
US7719054B2 (en) 2006-05-31 2010-05-18 Advanced Analogic Technologies, Inc. High-voltage lateral DMOS device
US7812393B2 (en) * 2006-05-31 2010-10-12 Advanced Analogic Technologies, Inc. High-voltage extended drain MOSFET
US20080067588A1 (en) * 2006-05-31 2008-03-20 Advanced Analogic Technologies, Inc. High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same
US20080067586A1 (en) * 2006-05-31 2008-03-20 Advanced Analogic Technologies, Inc. High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same
US20080061368A1 (en) * 2006-05-31 2008-03-13 Advanced Analogic Technologies, Inc. High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same
US20070278568A1 (en) * 2006-05-31 2007-12-06 Advanced Analogic Technologies, Inc. High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same
US10490637B2 (en) 2016-07-08 2019-11-26 Samsung Electronics Co., Ltd. Semiconductor devices including an active fin and a drift region
US20190305128A1 (en) * 2018-04-03 2019-10-03 Vanguard International Semiconductor Corporation Semiconductor structure and method for forming the same

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