US6475891B2 - Method of forming a pattern for a semiconductor device - Google Patents

Method of forming a pattern for a semiconductor device Download PDF

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US6475891B2
US6475891B2 US09/984,949 US98494901A US6475891B2 US 6475891 B2 US6475891 B2 US 6475891B2 US 98494901 A US98494901 A US 98494901A US 6475891 B2 US6475891 B2 US 6475891B2
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layer
pattern
forming
sacrificial layer
conformal
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US20020068447A1 (en
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Hong-bae Moon
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Definitions

  • the present invention relates to a method of forming a pattern for a semiconductor device. More particularly, the present invention relates to a method of forming a fine pitch pattern having a feature width under several tens of nanometers for a semiconductor device using sacrificial layer patterns.
  • a base layer 12 acting as an interlayer insulation film 12 is formed on a semiconductor substrate 10 .
  • a layer 13 to be a predetermined pattern, is formed on the base layer 12 , and subsequently a photoresist film (not shown) is formed on the layer 13 .
  • a photoresist film pattern 16 is formed by exposing and developing the photoresist film.
  • the layer 13 is partially etched to expose the base layer 12 using the photoresist film pattern 16 as an etching mask, so that predetermined pattern layers 13 a , 13 b , such as metal wires or gate electrodes, are formed.
  • the resolution capability of a photoresist film is usually improved by employing a light source having a short wavelength, or by incrementing a numerical aperture (NA) of a lens.
  • a light source having a short wavelength or by incrementing a numerical aperture (NA) of a lens.
  • NA numerical aperture
  • a DUV (deep ultraviolet) light source such as KrF (248 nm) or ArF (193 nm) having a wavelength shorter than G-line (436 nm) or I-line (365 nm) has been used, and an X-ray light source is being developed.
  • a method of forming a pattern for a semiconductor device comprising forming a sacrificial layer on a semiconductor substrate, forming a sacrificial layer pattern by patterning the sacrificial layer, forming a conformal layer on a resultant structure after forming the sacrificial layer pattern, and forming a layer pattern by anisotropically etching the conformal layer.
  • a base layer may be formed between the semiconductor substrate and the sacrificial layer.
  • the sacrificial layer is formed from a material having a high etching selectivity to the conformal layer and the semiconductor substrate, wherein the sacrificial layer is preferably formed of silicon nitride.
  • the conformal layer is preferably a conductive layer formed of a material from the group consisting of aluminum, tungsten, cobalt, copper, titanium and polysilicon.
  • the conformal layer may be a polycide double layer including a polysilicon layer and a silicide layer, or a multilayer, the multilayer being formed of films selected from the group consisting of a titanium film, an aluminum film, and a titanium nitride film.
  • the method further includes planarizing an upper surface of the sacrificial layer pattern and the layer pattern after forming the layer pattern.
  • the method further includes removing the sacrificial layer pattern by means of a wet etching process after forming the layer pattern.
  • a method of forming patterns for semiconductor devices comprising forming a sacrificial layer on a semiconductor substrate having a cell region and a peripheral region; forming a sacrificial layer pattern on the semiconductor substrate of the cell region; forming a conformal layer on the entire surface of the semiconductor substrate including the sacrificial layer pattern; forming a photoresist pattern on the conformal layer formed at the peripheral region; and anisotropically etching the conformal layer to expose the semiconductor substrate, thereby forming a first pattern comprised of the conformal layer on the sidewalls of the sacrificial layer pattern at the cell region, and forming a second pattern beneath the photoresist patterns at the peripheral region, wherein the second pattern has a width relatively wider than that of the first patterns.
  • a base layer may be formed between the semiconductor substrate and the sacrificial layer.
  • the sacrificial layer is preferably formed of a material having a high etching selectivity to the semiconductor substrate, the base layer and the conformal layer.
  • the sacrificial layer is preferably formed of silicon nitride.
  • the conformal layer is preferably a conductive layer.
  • the conformal layer is preferably selected from the group consisting of aluminum, tungsten, cobalt, copper, titanium and polysilicon.
  • the conductive layer may also be formed of a double layer comprised of a polysilicon layer and a suicide layer, or a multiplayer, the multilayer being formed of films selected from the group consisting of a titanium film, an aluminum film, and a titanium nitride film.
  • the method further includes planarizing an upper surface of the sacrificial layer pattern and the first and second patterns after anisotropically etching the layer.
  • the method further includes removing the sacrificial layer pattern by means of a wet etching process after anisotropically etching the layer.
  • the sacrificial layer pattern is formed at the cell region and the peripheral region, respectively; during forming the sacrificial layer pattern, the photoresist film pattern is formed on the layer at the peripheral region, and while the second pattern is formed beneath the photoresist film pattern during anisotropic etching of the layer, a dummy pattern is formed on sidewalls of the sacrificial layer pattern at the peripheral region.
  • FIGS. 1A through 1C illustrate cross-sectional views of a semiconductor device for sequentially showing a method of forming patterns for semiconductor devices in accordance with the prior art
  • FIG. 2 illustrates a plan view of a semiconductor device showing patterns to be formed in accordance with an embodiment of the present invention
  • FIGS. 3A through 3G illustrate cross-sectional views of a semiconductor device showing a method of forming patterns for a semiconductor device in accordance with an embodiment of the present invention.
  • FIG. 2 shows patterns to be formed in accordance with an embodiment of the present invention
  • FIGS. 3A through 3G illustrate cross-sectional views taken along line I—I in FIG. 2 for showing a method of forming patterns for semiconductor devices in accordance with an embodiment of the present invention.
  • a semiconductor substrate is covered with a base layer 102 .
  • First patterns 110 a , second patterns 110 b and dummy patterns 110 c are arranged on the base layer 102 .
  • the first patterns 110 a are arranged across the cell region of the semiconductor substrate such that they are equally spaced apart.
  • the second patterns 110 b are formed in the peripheral region.
  • the second patterns 110 b have a line width greater than that of the first patterns 110 a and dummy patterns 110 c .
  • Each of the second patterns 110 b is surrounded by a dummy pattern 110 c .
  • Dummy patterns 110 c are formed to reduce the step height difference between the cell region and the peripheral region.
  • the line width d 1 of first patterns 110 a formed in the cell region is the same width as the dummy patterns 110 c formed in the peripheral region.
  • the second patterns 110 b formed in the peripheral region have line widths d 3 , d 4 , each of which is wider than the line width d 1 of the first patterns 110 a and the dummy patterns 110 c .
  • Distances d 2 between each of patterns 110 a , 110 b , 110 c are equal.
  • a base layer 102 acting as an interlayer insulation film is formed on a semiconductor substrate 100 .
  • the base layer 102 is preferably formed of silicon oxide.
  • a sacrificial layer 103 is formed on the base layer 102 .
  • the sacrificial layer 103 is preferably formed of a material that has a high etching selectivity to the base layer 102 . For instance, if silicon oxide is used as a base layer 102 , a sacrificial layer 103 is formed from silicon nitride. A thickness of the sacrificial layer 103 is determined according to a thickness of a pattern layer to be formed in accordance with the present invention.
  • a photoresist film (not shown) is formed on the sacrificial layer 103 and then patterned to be first photoresist film patterns 106 , which are used as a mask for etching the sacrificial layer 103 .
  • the first photoresist film patterns 106 are formed by considering the line widths d 1 , d 3 , d 4 of the first, second and dummy patterns 110 a , 110 b , and 110 c , respectively, and the distance d 2 between each of the patterns shown in FIG. 2 .
  • the sacrificial layer 103 is used to form the first patterns 110 a and the dummy patterns 110 c .
  • the second patterns 110 b are formed by means of a photolithography technique.
  • a shape and size of the first photoresist film patterns 106 are determined by considering the subsequent processes.
  • a line width of the first photoresist film pattern 106 is the same as the distance d 2 between each of the patterns. Accordingly, the line width of the photoresist film patterns 106 is indicated by d 2 . Further, in the cell region, the first photoresist film patterns 106 having the line width d 2 are formed at intervals of the two first patterns 110 a . Thus, a distance between each of the first photoresist film patterns 106 in the cell region preferably corresponds to a value of (2 1 +d 2 ).
  • the first photoresist film patterns 106 are not formed to cover areas in which the second patterns 110 b , the dummy patterns 110 c and the separating area between the second patterns 110 b and the dummy patterns 110 c would be formed. That is, the first photoresist film patterns 106 are formed between each of the dummy patterns 110 c in the peripheral region.
  • a distance between each of the first photoresist film patterns 106 in the peripheral region corresponds to a total value of (2 1 + 2 d 2 +d 3 ), or (2 1 + 2 d 2 +d 4 ).
  • the sacrificial layer 103 is dry etched using the first photoresist film pattern 106 as a mask, so that a sacrificial layer pattern 103 a is formed.
  • a conformal layer 110 to be used for predetermined layer patterns in accordance with an embodiment the present invention, is formed on the entire upper surface of the resultant structure shown in FIG. 3 C. That is, the conformal layer 110 covers all of the sacrificial layer pattern 103 a and the base layer 102 .
  • the conformal layer 110 may be formed of a conductive material such as aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), titanium (Ti), other metal compounds, or polysilicon.
  • the conformal layer 110 may also be formed of a double layer called a polycide comprised of a polysilicon layer and a silicide layer.
  • the conformal layer 110 may be formed of a multilayer comprised of titanium film, titanium nitride film, aluminum film and titanium nitride film.
  • the material for the conformal layer 110 is determined according to a function of the layer patterns. For instance, when using the layer patterns as a metal wire, aluminum or tungsten is a proper material for the conformal layer 110 . On the other hand, when using the layer patterns as a gate electrode, a silicide is proper.
  • a width d 1 ′ of the conformal layer 110 formed on sidewalls of the sacrificial layer patterns 103 a is preferably the same as the width d 1 of the first patterns 110 a . Accordingly, the thickness d 1 ′ of the conformal layer 110 is formed to equal the width d 1 of the first patterns 110 a .
  • second photoresist film patterns 112 are formed on the conformal layer 110 at the peripheral of the semiconductor substrate.
  • the second photoresist film pattern 112 is a mask for forming the second patterns in the peripheral region. Accordingly, a width of each of the second photoresist film patterns 112 is preferably d 3 or d 4 .
  • the conformal layer 110 is anisotropically etched, using the second photoresist film patterns 112 as an etching mask, to expose the base layer 102 .
  • the second photoresist film patterns 112 are removed by means of an oxygen plasma ashing process after which the resultant structure is rinsed.
  • layer patterns 110 a formed from the conformal layer 110 remain on the sidewalls of the sacrificial layer pattern 103 a because the conformal layer 110 is etched without an etching mask.
  • the layer patterns 110 a in the cell region correspond to the first patterns 110 a shown in FIG. 2 .
  • layer patterns 110 c remain on the sidewalls of the sacrificial layer pattern 103 a , to be used as dummy patterns 110 c , and at the same time layer patterns 110 b are formed on the base layer 102 .
  • the layer patterns 110 b correspond to the second patterns 110 b shown in FIG. 2 .
  • an upper surface of the semiconductor substrate is uneven due to a different step height of the layer patterns 110 a , 110 b and 110 c , so that a planarization process is needed.
  • the surface of the semiconductor substrate is planarized by means of a CMP (chemical mechanical polishing) technique.
  • CMP chemical mechanical polishing
  • planarnzation process may be omitted.
  • the sacrificial layer pattern 103 a are selectively removed by a wet etching process. As a result, only the layer patterns 110 a , 110 b , and 110 c that correspond to the first and second patterns 110 a , 110 b and dummy patterns 110 c remain on the base layer 102 .
  • the sacrificial layer pattern 103 a when forming an insulation layer on the patterns 110 a , 110 b and 110 c after the planarization process, it is preferable to retain the sacrificial layer pattern 103 a .
  • the sacrificial layer pattern 103 a must be removed when using the first and the second patterns 110 a and 110 b as a gate electrode.
  • the present invention provides a method of forming fine pitch patterns by using sacrificial layer patterns.
  • the cost of manufacturing highly integrated semiconductor devices can be reduced over the manufacturing cost when using short wavelength photolithography because the expensive equipment necessary for the short wavelength photolithography process is unwarranted in the present invention, and further, the process of manufacturing semiconductor devices is simplified by use of the present invention.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

A method of forming a pattern for a semiconductor device without using a photolithography technique is disclosed, wherein the method includes forming a sacrificial layer on a semiconductor substrate, forming a sacrificial layer pattern by patterning the sacrificial layer, forming a conformal layer on a resultant structure after forming the sacrificial layer pattern, and forming the layer pattern by anisotropically etching the conformal layer.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a pattern for a semiconductor device. More particularly, the present invention relates to a method of forming a fine pitch pattern having a feature width under several tens of nanometers for a semiconductor device using sacrificial layer patterns.
2. Description of the Related Art
As semiconductor devices become increasingly integrated for economic efficiency, the design rule of the devices becomes smaller. Therefore, the topological dimensions for a pattern for the semiconductor devices decrease, and the minimum line width is reduced to a range of several hundreds to several tens of nanometers. Recently, pattern miniaturization and integration of semiconductor devices has been highly dependent upon developments in photolithography. That is, due to the resolution limit obtainable with the equipment and materials used thus far in the photolithography process, the amount of pattern miniaturization and integration possible in semiconductor devices has been limited.
Several problems associated with a conventional method of forming patterns for semiconductor devices are disclosed hereinafter.
As shown in FIG. 1A, a base layer 12 acting as an interlayer insulation film 12 is formed on a semiconductor substrate 10. A layer 13, to be a predetermined pattern, is formed on the base layer 12, and subsequently a photoresist film (not shown) is formed on the layer 13. Then, as shown in FIG. 1B, a photoresist film pattern 16 is formed by exposing and developing the photoresist film. Next, as shown in FIG. 1C, the layer 13 is partially etched to expose the base layer 12 using the photoresist film pattern 16 as an etching mask, so that predetermined pattern layers 13 a, 13 b, such as metal wires or gate electrodes, are formed.
Ordinarily, fine pitch patterns are formed in a memory cell region while large pitch patterns are formed in a peripheral region relative to the memory cell region. Therefore, the resolution capability of a photoresist film must be enhanced in order to form the fine pitch patterns. This resolution requirement defines the need for a feature of the present invention.
The resolution capability of a photoresist film is usually improved by employing a light source having a short wavelength, or by incrementing a numerical aperture (NA) of a lens. With respect to the light source, a DUV (deep ultraviolet) light source such as KrF (248 nm) or ArF (193 nm) having a wavelength shorter than G-line (436 nm) or I-line (365 nm) has been used, and an X-ray light source is being developed.
Moreover, there have been other attempts to form the fine pitch patterns for semiconductor devices, such as modifying a mask pattern into a phase shift mask (PSM) to prevent imprecise pattern formation due to an optical proximity effect, or employing an off axis illumination method.
However, the various approaches described above for forming fine pitch patterns in a memory cell, photolithography using a DUV or X-ray light source, modifying a mask pattern into PSM, and employing an off axis illumination method, require costly manufacturing equipment and a process that is more precisely controlled and complicated than that of conventional photolithography techniques. For instance, using a DUV or an X-ray as a light source requires new photoresist materials that are sensitive to the short wavelength of the DUV or the X-ray. Moreover, using the X-ray as a light source requires development of a new opaque material to obstruct transmission of the X-ray used in an X-ray photolithography process.
As a result, expensive equipment and complicated process conditions are necessary to form fine pitch patterns by means of the photolithography process, thereby increasing the manufacturing costs for a semiconductor device while decreasing the productivity thereof.
In addition, up until now, highly integrated semiconductor devices having miniaturized patterns have not been attainable with a conventional photolithography process, hence the alternate, more costly approaches described above.
SUMMARY OF THE INVENTION
It is, therefore, a feature of an embodiment of the present invention to provide a method for forming a pattern of a semiconductor device using sacrificial layer patterns.
It is another feature of an embodiment of the present invention to provide a method of forming a pattern for semiconductor devices using the conventional photolithography process, wherein the pattern preferably has a line width under several tens of nanometers.
It is yet another feature of an embodiment of the present invention to provide a method of forming patterns for a semiconductor device, comprising forming a first pattern, preferably of minimum line width under several tens of nanometers, and a second pattern having a line width relatively greater than that of the first pattern by combining a photolithography process and a non-photolithography process.
In order to provide the above features of the present invention, according to an embodiment of the present invention, there is provided a method of forming a pattern for a semiconductor device comprising forming a sacrificial layer on a semiconductor substrate, forming a sacrificial layer pattern by patterning the sacrificial layer, forming a conformal layer on a resultant structure after forming the sacrificial layer pattern, and forming a layer pattern by anisotropically etching the conformal layer.
In addition, a base layer may be formed between the semiconductor substrate and the sacrificial layer.
In a method according to an embodiment of the present invention, the sacrificial layer is formed from a material having a high etching selectivity to the conformal layer and the semiconductor substrate, wherein the sacrificial layer is preferably formed of silicon nitride.
In the method according to an embodiment of the present invention, the conformal layer is preferably a conductive layer formed of a material from the group consisting of aluminum, tungsten, cobalt, copper, titanium and polysilicon. Further, the conformal layer may be a polycide double layer including a polysilicon layer and a silicide layer, or a multilayer, the multilayer being formed of films selected from the group consisting of a titanium film, an aluminum film, and a titanium nitride film.
In the method according to an embodiment of the present invention, the method further includes planarizing an upper surface of the sacrificial layer pattern and the layer pattern after forming the layer pattern.
In the method according to an embodiment of the present invention, the method further includes removing the sacrificial layer pattern by means of a wet etching process after forming the layer pattern.
According to another embodiment of the present invention, there is provided a method of forming patterns for semiconductor devices comprising forming a sacrificial layer on a semiconductor substrate having a cell region and a peripheral region; forming a sacrificial layer pattern on the semiconductor substrate of the cell region; forming a conformal layer on the entire surface of the semiconductor substrate including the sacrificial layer pattern; forming a photoresist pattern on the conformal layer formed at the peripheral region; and anisotropically etching the conformal layer to expose the semiconductor substrate, thereby forming a first pattern comprised of the conformal layer on the sidewalls of the sacrificial layer pattern at the cell region, and forming a second pattern beneath the photoresist patterns at the peripheral region, wherein the second pattern has a width relatively wider than that of the first patterns.
In addition, a base layer may be formed between the semiconductor substrate and the sacrificial layer.
In the method according to an embodiment of the present invention, the sacrificial layer is preferably formed of a material having a high etching selectivity to the semiconductor substrate, the base layer and the conformal layer.
In the method according to an embodiment of the present invention, the sacrificial layer is preferably formed of silicon nitride.
In the method according to an embodiment of the present invention, the conformal layer is preferably a conductive layer.
In the method according to an embodiment of the present invention, the conformal layer is preferably selected from the group consisting of aluminum, tungsten, cobalt, copper, titanium and polysilicon. The conductive layer may also be formed of a double layer comprised of a polysilicon layer and a suicide layer, or a multiplayer, the multilayer being formed of films selected from the group consisting of a titanium film, an aluminum film, and a titanium nitride film.
In the method according to an embodiment of the present invention, the method further includes planarizing an upper surface of the sacrificial layer pattern and the first and second patterns after anisotropically etching the layer.
In the method according to an embodiment of the present invention, the method further includes removing the sacrificial layer pattern by means of a wet etching process after anisotropically etching the layer.
In the method according to an embodiment of the present invention, the sacrificial layer pattern is formed at the cell region and the peripheral region, respectively; during forming the sacrificial layer pattern, the photoresist film pattern is formed on the layer at the peripheral region, and while the second pattern is formed beneath the photoresist film pattern during anisotropic etching of the layer, a dummy pattern is formed on sidewalls of the sacrificial layer pattern at the peripheral region.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description of the preferred embodiments that follows.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:
FIGS. 1A through 1C illustrate cross-sectional views of a semiconductor device for sequentially showing a method of forming patterns for semiconductor devices in accordance with the prior art;
FIG. 2 illustrates a plan view of a semiconductor device showing patterns to be formed in accordance with an embodiment of the present invention; and
FIGS. 3A through 3G illustrate cross-sectional views of a semiconductor device showing a method of forming patterns for a semiconductor device in accordance with an embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Korean Patent Application No. 2000-73011, filed on Dec. 4, 2000, and entitled: “Method of Forming a Pattern for Semiconductor Devices,” is incorporated by reference herein in its entirety.
The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those of ordinary skill in the art. Like numbers refer to like elements throughout.
FIG. 2 shows patterns to be formed in accordance with an embodiment of the present invention, and FIGS. 3A through 3G illustrate cross-sectional views taken along line I—I in FIG. 2 for showing a method of forming patterns for semiconductor devices in accordance with an embodiment of the present invention.
Referring to FIG. 2, a semiconductor substrate is covered with a base layer 102. First patterns 110 a, second patterns 110 b and dummy patterns 110 c are arranged on the base layer 102. The first patterns 110 a are arranged across the cell region of the semiconductor substrate such that they are equally spaced apart. The second patterns 110 b are formed in the peripheral region. The second patterns 110 b have a line width greater than that of the first patterns 110 a and dummy patterns 110 c. Each of the second patterns 110 b is surrounded by a dummy pattern 110 c. Dummy patterns 110 c are formed to reduce the step height difference between the cell region and the peripheral region. The line width d1 of first patterns 110 a formed in the cell region is the same width as the dummy patterns 110 c formed in the peripheral region. The second patterns 110 b formed in the peripheral region have line widths d3, d4, each of which is wider than the line width d1 of the first patterns 110 a and the dummy patterns 110 c. Distances d2 between each of patterns 110 a, 110 b, 110 c are equal.
Now, a method of forming patterns in accordance with an embodiment of the present invention will be described below with reference to FIGS. 3A through 3G.
As shown in FIG. 3A, a base layer 102 acting as an interlayer insulation film is formed on a semiconductor substrate 100. The base layer 102 is preferably formed of silicon oxide. Next, a sacrificial layer 103 is formed on the base layer 102. The sacrificial layer 103 is preferably formed of a material that has a high etching selectivity to the base layer 102. For instance, if silicon oxide is used as a base layer 102, a sacrificial layer 103 is formed from silicon nitride. A thickness of the sacrificial layer 103 is determined according to a thickness of a pattern layer to be formed in accordance with the present invention.
Next, as shown in FIG. 3B, a photoresist film (not shown) is formed on the sacrificial layer 103 and then patterned to be first photoresist film patterns 106, which are used as a mask for etching the sacrificial layer 103.
The first photoresist film patterns 106 are formed by considering the line widths d1, d3, d4 of the first, second and dummy patterns 110 a, 110 b, and 110 c, respectively, and the distance d2 between each of the patterns shown in FIG. 2.
In a preferred embodiment of the present invention, the sacrificial layer 103, as opposed to the photolithography technique, is used to form the first patterns 110 a and the dummy patterns 110 c. The second patterns 110 b, however, are formed by means of a photolithography technique.
Therefore, a shape and size of the first photoresist film patterns 106 are determined by considering the subsequent processes.
A line width of the first photoresist film pattern 106 is the same as the distance d2 between each of the patterns. Accordingly, the line width of the photoresist film patterns 106 is indicated by d2. Further, in the cell region, the first photoresist film patterns 106 having the line width d2 are formed at intervals of the two first patterns 110 a. Thus, a distance between each of the first photoresist film patterns 106 in the cell region preferably corresponds to a value of (21+d2).
On the other hand, in the peripheral region, the first photoresist film patterns 106 are not formed to cover areas in which the second patterns 110 b, the dummy patterns 110 c and the separating area between the second patterns 110 b and the dummy patterns 110 c would be formed. That is, the first photoresist film patterns 106 are formed between each of the dummy patterns 110 c in the peripheral region. Thus, a distance between each of the first photoresist film patterns 106 in the peripheral region corresponds to a total value of (21+2d 2+d3), or (21+2d 2+d4).
Next, as shown in FIG. 3C, the sacrificial layer 103 is dry etched using the first photoresist film pattern 106 as a mask, so that a sacrificial layer pattern 103 a is formed.
Next, as shown in FIG. 3D, a conformal layer 110, to be used for predetermined layer patterns in accordance with an embodiment the present invention, is formed on the entire upper surface of the resultant structure shown in FIG. 3C. That is, the conformal layer 110 covers all of the sacrificial layer pattern 103 a and the base layer 102. The conformal layer 110 may be formed of a conductive material such as aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), titanium (Ti), other metal compounds, or polysilicon. The conformal layer 110 may also be formed of a double layer called a polycide comprised of a polysilicon layer and a silicide layer. Alternatively, the conformal layer 110 may be formed of a multilayer comprised of titanium film, titanium nitride film, aluminum film and titanium nitride film. The material for the conformal layer 110 is determined according to a function of the layer patterns. For instance, when using the layer patterns as a metal wire, aluminum or tungsten is a proper material for the conformal layer 110. On the other hand, when using the layer patterns as a gate electrode, a silicide is proper.
A width d1′ of the conformal layer 110 formed on sidewalls of the sacrificial layer patterns 103 a is preferably the same as the width d1 of the first patterns 110 a. Accordingly, the thickness d1′ of the conformal layer 110 is formed to equal the width d1 of the first patterns 110 a.
Next, second photoresist film patterns 112 are formed on the conformal layer 110 at the peripheral of the semiconductor substrate. The second photoresist film pattern 112 is a mask for forming the second patterns in the peripheral region. Accordingly, a width of each of the second photoresist film patterns 112 is preferably d3 or d4.
Next, as shown in FIGS. 3E and 3F, the conformal layer 110 is anisotropically etched, using the second photoresist film patterns 112 as an etching mask, to expose the base layer 102. Subsequently, the second photoresist film patterns 112 are removed by means of an oxygen plasma ashing process after which the resultant structure is rinsed. As a result, in the cell region, layer patterns 110 a formed from the conformal layer 110 remain on the sidewalls of the sacrificial layer pattern 103 a because the conformal layer 110 is etched without an etching mask. The layer patterns 110 a in the cell region correspond to the first patterns 110 a shown in FIG. 2. On the other hand, in the peripheral region, layer patterns 110 c remain on the sidewalls of the sacrificial layer pattern 103 a, to be used as dummy patterns 110 c, and at the same time layer patterns 110 b are formed on the base layer 102. The layer patterns 110 b correspond to the second patterns 110 b shown in FIG. 2. After etching, however, an upper surface of the semiconductor substrate is uneven due to a different step height of the layer patterns 110 a, 110 b and 110 c, so that a planarization process is needed.
Thus, as shown in FIG. 3F, the surface of the semiconductor substrate is planarized by means of a CMP (chemical mechanical polishing) technique.
However, the planarnzation process may be omitted.
Next, as shown in FIG. 3G, the sacrificial layer pattern 103 a are selectively removed by a wet etching process. As a result, only the layer patterns 110 a, 110 b, and 110 c that correspond to the first and second patterns 110 a, 110 b and dummy patterns 110 c remain on the base layer 102.
Alternatively, when forming an insulation layer on the patterns 110 a, 110 b and 110 c after the planarization process, it is preferable to retain the sacrificial layer pattern 103 a. However, the sacrificial layer pattern 103 amust be removed when using the first and the second patterns 110 a and 110 b as a gate electrode.
As discussed above, rather than using the photolithography technique, which has been a limiting factor in the conventional miniaturization of patterns for semiconductor devices, the present invention provides a method of forming fine pitch patterns by using sacrificial layer patterns.
Therefore, by using the present invention, the cost of manufacturing highly integrated semiconductor devices can be reduced over the manufacturing cost when using short wavelength photolithography because the expensive equipment necessary for the short wavelength photolithography process is unwarranted in the present invention, and further, the process of manufacturing semiconductor devices is simplified by use of the present invention.
Preferred embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Claims (16)

What is claimed is:
1. A method of forming a layer pattern for a semiconductor device, comprising the steps of:
forming a sacrificial layer on a semiconductor substrate;
forming a sacrificial layer pattern by patterning the sacrificial layer;
forming a conformal layer on a resultant structure formed after the step of forming the sacrificial layer pattern;
forming the layer pattern by anisotropically etching the conformal layer; and
planarizing an upper surface of the sacrificial layer pattern and the layer pattern.
2. A method as claimed in claim 1, wherein the sacrificial layer is formed of a material having a high etching selectivity to the conformal layer and the semiconductor substrate.
3. A method as claimed in claim 1, wherein the conformal layer is a conductive layer.
4. A method as claimed in claim 3, wherein the conformal layer is formed of a conductive material selected from the group consisting of aluminum, tungsten, copper, cobalt, titanium and polysilicon.
5. A method as claimed in claim 3, wherein the conformal layer is formed of a polycide double layer including a polysilicon layer and a silicide layer.
6. A method as claimed in claim 1, wherein the conformal layer is formed of a multilayer, the multilayer being formed of films selected from the group consisting of a titanium film, an aluminum film, and a titanium nitride film.
7. A method as claimed in claim 1, further comprising removing the sacrificial layer pattern by means of a wet etching process after forming the layer pattern.
8. A method of forming a pattern for a semiconductor device, comprising:
forming a sacrificial layer on a semiconductor substrate having a cell region and a peripheral region;
forming a sacrificial layer pattern on the semiconductor substrate of the cell region;
forming a conformal layer on the entire surface of the semiconductor substrate including the sacrificial layer pattern;
forming a photoresist pattern on the conformal layer formed at the peripheral region; and
anisotropically etching the conformal layer to expose the semiconductor substrate, thereby forming a first pattern comprised of the conformal layer on sidewalls of the sacrificial layer pattern in the cell region and a second pattern beneath the photoresist pattern in the peripheral region, wherein the second pattern has a line width relatively greater than that of the first pattern.
9. The method of claim 8, wherein the sacrificial layer is formed of a material having a high etching selectivity to the semiconductor substrate and the conformal layer.
10. The method of claim 8, wherein the conformal layer is a conductive layer.
11. The method of claim 10, wherein the conformal layer is formed of a conductive material selected from the group consisting of aluminum, tungsten, cobalt, copper, titanium and polysilicon.
12. The method according to claim 10, wherein the conformal layer is formed of a polycide double layer including a polysilicon layer and a silicide layer.
13. The method according to claim 8, wherein the conformal layer is formed of a multilayer, the multilayer being formed of films selected from the group consisting of a titanium film, an aluminum film and a titanium nitride film.
14. The method according to claim 8, further comprising planarizing an upper surface of the sacrificial layer patterns and the first and second patterns after anisotropically etching the conformal layer.
15. The method according to claim 8, further comprising removing the sacrificial layer pattern by means of a wet etching process after anisotropically etching the conformal layer.
16. The method of claim 8, wherein the sacrificial layer pattern is formed at the cell region and the peripheral region, respectively; during forming the sacrificial layer pattern, the photoresist film pattern is formed on the conformal layer at the peripheral region, and while the second pattern is formed beneath the photoresist film pattern during anisotropic etching of the conformal layer, a dummy pattern is formed on sidewalls of the sacrificial layer pattern at the peripheral region.
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