JP2014183135A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve high integration and reduction in parasitic capacitance.SOLUTION: A semiconductor device according to an embodiment comprises: a foundation layer; a first wiring provided on the foundation layer and extending in a first direction; a second wiring provided adjacent to the first wiring on the foundation layer and extending in the first direction; an insulating layer provided between the first wiring and the second wiring; a third wiring provided between the foundation layer and the insulating layer and extending in the first direction. A group of wirings including the first wiring, the second wiring, and the third wiring is periodically aligned in a second direction crossing the first direction.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  In recent years, as a technique for narrowing the wiring structure beyond the resolution of the exposure apparatus, there is a double patterning technique using a spacer process. The double patterning technique is based on the following procedure, for example. First, after forming a layer called a core material on the film to be processed, a sidewall film is formed on the side surface of the core material. Next, the core material is removed, and the film is processed using the remaining sidewall film as a mask. According to this method, the wiring can be patterned at a pitch twice the minimum resolution pitch of the exposure apparatus.

  Recently, however, higher integration of wiring has been demanded. For this reason, double patterning technology is becoming unable to satisfy the requirements. A method of performing the spacer process once more after the core material is processed by the spacer process is also conceivable. However, this method may increase the number of processes, increase manufacturing costs, and make process control in each process difficult. In addition, in this process, since all the wirings are formed at the same height, there is a problem that the parasitic capacitance between the adjacent wirings becomes larger as the integration becomes higher.

US Pat. No. 6,475,891

  The problem to be solved by the present invention is to provide a semiconductor device capable of higher integration and reduced parasitic capacitance, and a method for manufacturing the same.

  The semiconductor device of the embodiment is provided on a base layer, a first wiring provided on the base layer and extending in a first direction, and provided on the base layer next to the first wiring. A second wiring extending in one direction, an insulating layer provided between the first wiring and the second wiring, and provided between the base layer and the insulating layer, in the first direction. And a set of wirings including the first wiring, the second wiring, and the third wiring are periodically arranged in a second direction intersecting the first direction. .

FIG. 1A to FIG. 1C are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment, and FIG. 1D is a schematic plan view illustrating the semiconductor device according to the first embodiment. is there. 2A to 2D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 3A to FIG. 3D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 4A to FIG. 4D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 5A to FIG. 5D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6A to FIG. 6D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 7A to FIG. 7D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 8A to FIG. 8D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 9A to FIG. 9D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 10A to FIG. 10D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 11A to FIG. 11D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 12A to FIG. 12D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 13A to FIG. 13D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 14A to FIG. 14D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 15A to FIG. 15D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 16A to FIG. 16D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 17A to FIG. 17D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 18A to FIG. 18D are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to a reference example. FIG. 19A to FIG. 19C are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the second embodiment. 20A to 20C are schematic cross-sectional views illustrating the manufacturing process of the semiconductor device according to the second embodiment. FIG. 21A to FIG. 21B are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. 22A to FIG. 22B are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the third embodiment. FIG. 23A to FIG. 23B are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. 24A to FIG. 24B are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. 25A to FIG. 25B are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the third embodiment. FIG. 26A to FIG. 26C are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the third embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same members are denoted by the same reference numerals, and the description of the members once described is omitted as appropriate.

(First embodiment)
FIG. 1A to FIG. 1C are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment, and FIG. 1D is a schematic plan view illustrating the semiconductor device according to the first embodiment. is there.

  FIG. 1A shows a cross section at the position of the A-A ′ line in FIG. FIG. 1B shows a cross section taken along the line B-B ′ of FIG. When the semiconductor device 1 is a semiconductor memory including a memory cell, the structures of FIGS. 1A, 1B, and 1D are arranged in the memory cell region (or element region) of the semiconductor device 1. Has been. The structure of FIG. 1C is disposed in the peripheral circuit region outside the memory cell region of the semiconductor device 1.

  In the semiconductor device 1, the base layer 11 is provided above the semiconductor layer 10. The underlayer 11 is, for example, an interlayer insulating film of the semiconductor device 1. A wiring layer 21 (first wiring) and a wiring layer 22 (second wiring) are provided on the base layer 11 (FIG. 1A). The wiring layer 22 is provided beside the wiring layer 21. The wiring layer 21 and the wiring layer 22 extend in the X direction (first direction) parallel to the lower surface 10 d of the semiconductor layer 10. In the present embodiment, the expression “wiring layer” may be replaced with “wiring”.

  The wiring layer 21 may be connected to a contact plug 50 provided in the base layer 11. Alternatively, the side surface 21w, the upper end 21u, and the lower end 21d of the wiring layer 21 may be surrounded by the insulating layers 30 and 31 and the base layer 11. The wiring layer 22 may be connected to a contact plug 51 provided in the base layer 11. Alternatively, the side surface 22w, the upper end 22u, and the lower end 22d of the wiring layer 22 may be surrounded by the insulating layers 30 and 31 and the base layer 11.

  An insulating layer 31 is provided between the wiring layer 21 and the wiring layer 22. A wiring layer 23 (third wiring) is provided below the insulating layer 31 provided between the wiring layer 21 and the wiring layer 22. That is, the wiring layer 23 is provided between the base layer 11 and the insulating layer 31. The wiring layer 23 extends in the X direction. The side wall 23 w and the lower end 23 d of the wiring layer 23 are surrounded by the base layer 11. The wiring layer 23 may be connected to a contact plug 52 provided in the base layer 11.

  The length of the wiring layer 23 in the X direction is longer than the length of the wiring layer 21 in the X direction and the length of the wiring layer 22 in the X direction (see FIG. 1D). Each of the wiring layer 21 and the wiring layer 22 is not located immediately above the wiring layer 23. That is, when the wiring layers 21, 22, and 23 are viewed from the Z direction, each of the wiring layer 21 and the wiring layer 22 does not overlap the wiring layer 23.

  In the semiconductor device 1, a plurality of wiring sets 20 including a wiring layer 21, a wiring layer 22, and a wiring layer 23 are arranged in a direction intersecting the X direction. The direction intersecting the X direction is, for example, the Y direction (second direction) perpendicular to the X direction and the Z direction. The set 20 is a minimum unit when the wiring layers are arranged in a set. The sets 20 are arranged periodically, for example, in the Y direction. The group 20 is, for example, two or more groups. The upper limit of the number of sets 20 is appropriately adjusted according to the structure of the device.

  In the semiconductor device 1, the wiring layers 21 and 22 may be upper wiring layers, and the wiring layer 23 may be a lower wiring layer. For example, in the semiconductor device 1, the upper wiring layer, the lower wiring layer, the upper wiring layer, the upper wiring layer, the lower wiring layer, the upper wiring layer, the upper wiring layer, the lower wiring layer, and the upper wiring layer in the Y direction. The wiring layers are arranged in this order.

  Further, in FIG. 1B, a wiring layer 23 is provided in the base layer 11. An insulating layer 31 is provided on the wiring layer 23. The height of the wiring layer 23 in FIG. 1B is the same as the height of the wiring layer 23 in FIG. Further, in FIG. 1C, a wiring layer 54 is provided in the base layer 11. The width of the wiring layer 54 in the Y direction is wider than the width of the wiring layer 23 in the Y direction. A contact plug 55 is connected to the wiring layer 54. An insulating layer 31 is provided on the wiring layer 54. Furthermore, the present embodiment is not limited to the structure shown in FIG. For example, a contact plug for connecting to an upper layer wiring may be provided on each of the wiring layers 21, 22, 23, 54.

  The material of the semiconductor layer 10 is, for example, a semiconductor containing an n-type impurity element such as arsenic (As) or phosphorus (P) or a p-type impurity element such as boron (B). Here, the semiconductor is silicon (Si), polysilicon (poly-Si), or the like.

The material of the wiring layers 21, 22, 23, 54 is, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum, or the like. The material of the contact plugs 50, 51, 52, 55 is, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum, or the like. The material of the base layer 11 and the insulating layers 30 and 31 is silicon oxide (SiO ₂ ) or the like.

  2A to 17D are schematic views showing the manufacturing process of the semiconductor device according to the first embodiment. Here, (a) to (c) in each drawing are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment, and (d) in each drawing is the semiconductor device according to the first embodiment. It is a plane schematic diagram showing the manufacturing process of.

  In each figure, (a) shows a cross section at the position of the A-A 'line in (d) in each figure. (B) of each figure shows a cross section at the position of the line B-B 'of (d) of each figure. (C) of each figure shows a cross section of the manufacturing process in the peripheral circuit region outside the memory cell region of the semiconductor device. In addition, the display of the semiconductor layer 10 is abbreviate | omitted in each figure of Fig.2 (a)-FIG.17 (d).

  The film and layer forming method described below is appropriately selected from any of CVD (Chemical Vapor Deposition), sputtering method, ALD (Atomic Layer Deposition) method, epitaxial method, spin coating method and the like unless otherwise specified. The The removal of the film and layer is appropriately selected from dry etching such as RIE (Reactive Ion Etching), wet etching using a hydrofluoric acid solution and an alkaline solution, ashing using an oxygen-containing gas, and CMP.

  First, as shown in FIGS. 2A to 2D, a structure in which contact plugs 50, 51, 52, and 55 are provided in the base layer 11 is prepared. The contact plugs 50, 51, 52 are, for example, wiring layers for electrical connection to the memory cell.

  Next, as illustrated in FIGS. 3A to 3D, the insulating layer 30 (first insulating layer) is formed on the base layer 11. The film thickness in the Z direction of the insulating layer 30 is, for example, 125 nm.

  Next, as shown in FIGS. 4A to 4D, a line and space is formed on the base layer 11. For example, as shown in FIGS. 4A, 4B, and 4D, a plurality of trenches 30ta (first trenches) are formed in the insulating layer 30 by photolithography and anisotropic etching. It is formed. Further, as illustrated in FIG. 4C, the insulating layer 30 is formed with a trench 30 tb.

  The anisotropic etching is, for example, RIE (Reactive Ion Etching). The trenches 30 ta and 30 tb are recessed in the direction from the insulating layer 30 toward the base layer 11. Each of the trenches 30 ta and 30 tb penetrates from the upper surface 30 u of the insulating layer 30 to the base layer 11. The line lines and spaces are periodically arranged in the Y direction. One pitch in the Y direction of this line line and space is defined as P1. For example, in the patterned insulating layer 30, the distance between the center of the insulating layer 30 and the center of the insulating layer 30 adjacent to the insulating layer 30 is P1.

  The trench 30ta extends in the X direction parallel to the upper surface 30u of the insulating layer 30. The trenches 30ta are arranged in a direction intersecting the X direction (for example, the Y direction). One pitch of the trenches 30ta is adjusted to twice the pitch of the upper wiring layers (wiring layers 21 and 22). One pitch in the Y direction of the trench 30ta is, for example, 80 nm. The width of the trench 30ta in the Y direction is, for example, 40 nm.

  As an example, the trench 30tb is shown extending in the X direction. The width of the trench 30tb in the Y direction is, for example, 26 nm wider than the width of the wiring layer 54 in the Y direction. The number of trenches 30tb is not limited to one, and a plurality of trenches 30tb may be formed.

  Next, as shown in FIGS. 5A to 5D, the width in the Y direction of the trenches 30ta and 30tb is widened by isotropic etching. The isotropic etching is, for example, wet etching. In the wet etching, for example, a 0.5% hydrofluoric acid aqueous solution is used. At this stage, the widths of the trenches 30ta and 30tb in the Y direction are enlarged by, for example, 10 nm compared to the stage shown in FIGS. 4 (a) to 4 (d). The width of the trench 30ta in the Y direction is, for example, 60 nm. One pitch of the line and space remains “P1”.

  Next, as shown in FIGS. 6A to 6D, the sidewall film 40 is formed in each of the plurality of trenches 30 ta and in the trench 30 tb. The sidewall film 40 is not completely formed in each of the plurality of trenches 30ta and in the trench 30tb. That is, the thickness of the sidewall film 40 is adjusted so that the trenches 30ta and 30tb remain. The film thickness of the sidewall film 40 is, for example, 23 nm. The material of the sidewall film 40 is, for example, silicon nitride (SiN).

  Subsequently, anisotropic etching (for example, dry etching) is performed on the sidewall film 40. By this anisotropic etching, the upper side wall film 40 is removed from the upper surface 30u of the insulating layer 30, and the side wall film 40 exposed at the bottoms of the trenches 30ta and 30tb is removed. This state is shown in FIGS. 7 (a) to 7 (d).

  As illustrated in FIG. 7A to FIG. 7D, a sidewall film 41 (third sidewall film) is formed on each side surface 30wa (first side surface) of the plurality of trenches 30ta. Further, a sidewall film 42 (fourth sidewall film) is formed on each side surface 30wb (second side surface) of each of the plurality of trenches 30ta. Further, a sidewall film 43 is formed on the side surface 30wa of the trench 30tb. Further, a sidewall film 44 is formed on the side surface 30wb of the trench 30tb.

  The material of the sidewall films 41 to 44 is the same as that of the sidewall film 40.

  Next, as shown in FIGS. 8A to 8D, the base layer 11 located between the sidewall film 41 and the sidewall film 42 is removed by anisotropic etching. In this anisotropic etching, the side wall film 41 and the side wall film 42 serve as a mask. Similarly, the foundation layer 11 located between the sidewall film 43 and the sidewall film 44 is removed by anisotropic etching. As a result, a trench 11ta (second trench) extending in the X direction is formed in the base layer 11. A trench 11tb extending in the X direction is formed in the base layer 11. The depth of the trenches 11ta and 11tb in the Z direction is, for example, 50 nm. In addition, the film thickness of the insulating layer 30 decreases under the influence of anisotropic etching.

  Next, as shown in FIGS. 9A to 9D, the sidewall films 41 to 44 are removed. The sidewall films 41 to 44 are removed by wet etching using phosphoric acid.

  Next, as shown in FIGS. 10A to 10D, the conductive layer 27 (first conductive layer) is formed in each of the plurality of trenches 30ta and in the trench 11ta. Further, a conductive layer 57 is formed in the trench 30tb and in the trench 11tb. The material of the conductive layers 27 and 57 is, for example, tungsten (W). Each thickness (thickness in the Z direction) of the conductive layers 27 and 57 from the joint portion of the base layer 11 and the insulating layer 30 is, for example, 200 nm.

  In the first embodiment, the wiring layer 23 is formed in advance, and thereafter, the process of laminating the wiring layers 21 and 22 by another process is not performed. In the first embodiment, the conductive layer 27 serving as a prototype of the wiring layers 21, 22, and 23 is collectively formed at this stage. The conductive layer 27 is connected to the contact plugs 50, 51, 52. Conductive layer 57 is connected to contact plug 55.

  Next, as shown in FIGS. 11A to 11D, the upper surface 27 u of the conductive layer 27 is lowered from the upper surface 30 u of the insulating layer 30. Thereby, a part of each side surface 30wa of the plurality of trenches 30ta and a part of the side surface 30wb facing the side surface 30wa are exposed from the conductive layer 27. Further, the upper surface 57 u of the conductive layer 57 is lowered from the upper surface 30 u of the insulating layer 30. Thereby, a part of the side surface 30wa of the trench 30tb and a part of the side surface 30wb facing the side surface 30wa are exposed from the conductive layer 57.

  At this stage, the respective thicknesses (thicknesses in the Z direction) of the conductive layers 27 and 57 from the joint portion between the base layer 11 and the insulating layer 30 are, for example, 40 nm. The removal of the conductive layers 27 and 57 is performed by at least one means such as chemical mechanical polishing (CMP), dry etching, or wet etching. For example, the conductive layers 27 and 57 are removed by a combination of CMP and dry etching or wet etching.

  Next, as shown in FIGS. 12A to 12D, a sidewall film 60 that covers the conductive layer 27 and the insulating layer 30 is formed. The sidewall film 60 is not completely formed in each of the plurality of trenches 30ta and in the trench 30tb. That is, the thickness of the sidewall film 60 is adjusted so that the trenches 30ta and 30tb remain. The material of the sidewall film 60 is, for example, silicon nitride (SiN). The thickness of the sidewall film 60 is, for example, 20 nm.

  Subsequently, anisotropic etching (for example, dry etching) is performed on the sidewall film 60. By this anisotropic etching, the upper sidewall film 60 is removed from the upper surface 30u of the insulating layer 30, and the sidewall film 60 exposed at the bottom of the trenches 30ta and 30tb is removed. This state is shown in FIGS. 13 (a) to 13 (d).

  As illustrated in FIG. 13A to FIG. 13D, a sidewall film 61 (first sidewall film) is formed on each side surface 30wa of the plurality of trenches 30ta, and the plurality of trenches 30ta are formed. A sidewall film 62 (second sidewall film) is formed on each side surface 30wb. Further, the sidewall film 63 is formed on the side surface 30wa of the trench 30tb, and the sidewall film 64 is formed on the side surface 30wb of the trench 30tb.

  The material of the sidewall films 61 to 64 is the same as that of the sidewall film 60.

  Here, as shown in FIG. 13D, in the region 1 b, a structure in which the sidewall film 61 and the sidewall film 62 are folded back via the sidewall film 65 is formed. That is, the sidewall film 61, the sidewall film 62, and the sidewall film 65 form a sidewall film loop. This is because the side wall film is formed along the side surface of the trench 30 ta surrounded by the insulating layer 30. In the region 1a, the sidewall film 61 and the sidewall film 62 both extend in the X direction, and the sidewall film 61 and the sidewall film 62 are arranged in the Y direction.

  Next, as shown in FIGS. 14A to 14D, a mask layer 90 that covers the insulating layer 30, the sidewall films 61 and 62, and the conductive layer 27 is formed in the region 1 a. The mask layer 90 is formed by photolithography and dry etching. The material of the mask layer 90 is, for example, a resist.

  Subsequently, the sidewall films 61 to 64 exposed from the mask layer 90 are removed by dry etching. Thereafter, the mask layer 90 is removed. This state is shown in FIGS. 15 (a) to 15 (d).

  As shown in FIGS. 15A to 15D, the sidewall film is removed in the region 1b (FIG. 15B) and the peripheral circuit region (FIG. 15C). In the embodiment, since the folded structure of the sidewall film is removed in the region 1b, the region 1b is set as a loop isolation region. By removing the side wall films 61 and 62 from the loop isolation region, the wiring layer 21 and the wiring layer 22 separated in the Y direction by a process described later are formed. The wiring layer 21 and the wiring layer 22 are fine wiring as an upper wiring layer (described later).

  FIG. 1C shows a state where a fine wiring layer is not provided above the wiring layer 54 in the peripheral circuit region as an example. In such a case, since it is not necessary to provide a fine wiring layer above the wiring layer 54, the sidewall films 63 and 64 are removed from the peripheral circuit region. Note that a wiring layer may be provided as appropriate above the wiring layer 54.

  Next, as shown in FIGS. 16A and 16D, the conductive layer 27 positioned between the sidewall film 61 and the sidewall film 62 is formed using the sidewall film 61 and the sidewall film 62 as a mask. Removed. A means for removing the conductive layer 27 is anisotropic etching. As a result, the conductive layer 27 is divided to form the wiring layer 21 extending in the X direction and the wiring layer 22 extending in the X direction. The wiring layer 21 is located under the side wall film 61. The wiring layer 22 is located under the side wall film 62.

  In the embodiment, the conductive layer 27 located between the sidewall film 61 and the sidewall film 62 is removed, and the upper portion of the conductive layer 27 provided in the trench 11ta is removed. The upper part of the conductive layer 27 is, for example, the conductive layer 27 from the junction between the base layer 11 and the insulating layer 30 to a depth of 10 nm (depth in the Z direction). Further, the underlying layer 11 on both upper sides is removed. In other words, overetching is performed to a depth of 10 nm from the junction between the base layer 11 and the insulating layer 30 using the sidewall films 61 and 62 as a mask.

  As a result, a wiring layer 23 is formed between the wiring layer 21 and the wiring layer 22. The wiring layer 23 extends in the X direction. The wiring layer 23 is provided under the wiring layer 21 and the wiring layer 22. As a result, a plurality of wiring sets 20 including the wiring layer 21, the wiring layer 22, and the wiring layer 23 are arranged in the Y direction.

  In the region 1b (FIG. 16B) and the peripheral circuit region (FIG. 16C), a sidewall film as a mask is not provided. Therefore, the conductive layer 27 provided in the trench 30ta and the conductive layer 57 provided in the trench 30tb are removed. Further, overetching is performed to a depth of 10 nm from the junction between the base layer 11 and the insulating layer 30. As a result, the wiring layer 23 and the contact plug 55 are formed in the base layer 11.

  That is, in the region 1b, since the side wall film is removed before the anisotropic etching, the wiring layer 23 is formed. On the other hand, in the region 1a, in addition to the wiring layer 23, the wiring layer 21 and the wiring layer 22 divided from the conductive layer 27 are formed.

  The layer thickness in the Z direction of the wiring layers 21 and 22 is 40 nm, for example. The width of the wiring layers 21 and 22 in the X direction is, for example, 20 nm. The layer thickness in the Z direction of the wiring layer 23 is, for example, 40 nm. The width of the wiring layer 23 in the X direction is, for example, 14 nm. The layer thickness in the Z direction of the wiring layer 54 is, for example, 40 nm. The width of the wiring layer 54 in the Y direction is wider than the width of each of the wiring layers 21, 22 and 23 in the X direction. The insulating layer 30 is further thinned by the influence of anisotropic etching.

  Next, as shown in FIGS. 17A to 17D, the sidewall films 61 and 62 are removed by wet etching. In this wet etching, phosphoric acid is used. Thus, three wiring layers 21, 22, and 23 are formed in the pitch P1.

  Thereafter, as shown in FIGS. 1A to 1D, an insulating layer 31 as a cap member is formed. The film thickness in the Z direction of the insulating layer 31 is, for example, 100 nm.

Before describing the effects of the first embodiment, a reference example will be described. Reference examples described below are also included in this embodiment.
FIG. 18A to FIG. 18D are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to a reference example. FIG. 18A to FIG. 18D illustrate the double patterning process described above.

  First, as shown in FIG. 18A, the insulating layer 101 is patterned on the base layer 100. The insulating layer 101 extends in the X direction. One pitch in the Y direction of the insulating layer 101 is “P1”.

  Next, as illustrated in FIG. 18B, the sidewall film 102 is formed on the sidewall of the insulating layer 101.

  Next, as shown in FIG. 18C, the insulating layer 101 is removed.

  Next, as illustrated in FIG. 18D, anisotropic etching is performed on the base layer 100 using the sidewall film 102 as a mask. As a result, the trench 103 is formed in the base layer 100. For example, a wiring layer is formed in the trench 103. Note that a stopper layer for improving the accuracy of the dry etching process may be formed on a part of the base layer 11 or the insulating layer 30. For example, by using, for example, a silicon nitride (SiN) film as a stopper layer in the uppermost layer of the base layer 11 or the lowermost layer of the insulating layer 30, variations in the depth of the trenches 30ta and 30tb shown in FIG. 4 are reduced. . In this case, as the sidewall film 40, for example, a different type of film from a stopper film such as amorphous silicon is used.

  The reference example can be combined with the first embodiment. For example, the base layer 100 is replaced with the insulating layer 30. In this case, the following flow is performed.

  First, on the insulating layer 30, a plurality of insulating layers (mask layers) that are arranged at a pitch twice that of the plurality of trenches 30ta arranged in the Y direction and extend in the X direction are formed (FIG. 18 ( a)).

  Next, a sidewall film 102 (fifth sidewall film) is formed on each sidewall of the plurality of insulating layers 101 (FIG. 18B).

  Next, the plurality of insulating layers 101 are removed (FIG. 18C).

  A plurality of trenches 103 are formed by etching the insulating layer 30 exposed from the sidewall film 102 (FIG. 18D). In this case, the trench 103 corresponds to the trench 30ta.

  In the reference example, a sidewall film 102 is formed on the sidewall of the insulating layer 101 having a pitch of P1, and the base layer 100 is etched using the sidewall film 102 as a mask. For this reason, one pitch in the Y direction of the trench 103 is ½ of P1. That is, in the reference example, two wiring layers are formed in one pitch of line and space.

  On the other hand, according to the first embodiment, three wiring layers can be formed in one pitch of line and space (see FIG. 17A). In other words, the wiring layer can be formed at a pitch of 1/3 with respect to the same pitch as the line and space according to the reference example. That is, in the reference example, the wiring is miniaturized at a pitch of 1/2 with respect to one line and space pitch, whereas in the first embodiment, 1 with respect to one line and space pitch. The wiring is miniaturized at a pitch of / 3. Thus, according to the first embodiment, the miniaturization of the wiring is further promoted.

  Furthermore, by combining the manufacturing process according to the reference example and the manufacturing process according to the first embodiment, wiring is performed at a pitch of 1/6 (1/2 × 1/3) with respect to one pitch of line and space. Can be formed. That is, by combining the manufacturing process according to the reference example and the manufacturing process according to the first embodiment, six wiring layers can be formed in one line-and-space pitch.

  Even in a process in which the manufacturing process according to the reference example is repeated twice, the wiring layer can be miniaturized. However, in this case, the wiring layer is only formed at a pitch of 1/4 (1/2 × 1/2) with respect to one line and space pitch. On the other hand, by combining the manufacturing process according to the reference example and the manufacturing process according to the first embodiment, the wiring can be formed at a pitch of 1/6 with respect to one line and space pitch. That is, according to the first embodiment, miniaturization of the wiring layer is more reliably promoted.

  Further, according to the first embodiment, among the wiring layers 21, 22, and 23 at one pitch, the wiring layers 21 and 22 are formed on the upper side, and the wiring layer 23 is formed on the lower side (FIG. 1A )). Further, the conductive layer 27, which is a prototype of the wiring layers 21, 22, and 23, is formed in a lump (FIG. 10A). Accordingly, the mutual positions of the wiring layers 21 and 22 (upper wiring layer) and the wiring layer 23 (lower wiring layer) are determined by self-alignment.

  Thereby, the wiring layer 23 and the wiring layers 21 and 22 do not overlap in the Z direction and do not overlap in the Y direction. That is, the wiring layer 23 and the wiring layers 21 and 22 do not overlap vertically and horizontally. Therefore, even if the wiring layers 21 and 22 are stacked on the wiring layer 23, an increase in parasitic capacitance (inter-wiring capacitance) is suppressed.

  In the first embodiment, the length of the wiring layer 23 in the X direction is longer than the length of the wiring layers 21 and 22 in the X direction (FIGS. 1D and 17D). For example, as illustrated in FIG. 1D, the wiring layer 23 includes a portion 23 a in which the end portion of the wiring layer 23 protrudes from the end portions of the wiring layers 21 and 22. This portion 23 a is not sandwiched between the wiring layers 21 and 22.

  That is, in the first embodiment, it is possible to provide a connection structure that connects the portion 23a and a contact plug or the like. The contact plug is provided on the portion 23a, for example. In order to form this connection structure, a photolithography process is performed. In this photolithography process, since the portion 23a is not sandwiched between the wiring layers 21 and 22, it is difficult to receive interference from the upper wiring layer (wiring layers 21 and 22). For this reason, in the photolithography process of this connection structure, misalignment hardly occurs. Thus, according to the first embodiment, high integration and reduction of parasitic capacitance are realized.

(Second Embodiment)
FIG. 19A to FIG. 20C are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the second embodiment. Here, the left diagram, the middle diagram, and the right diagram of each figure correspond to FIGS. 1A to 1C of the first embodiment.

  In the second embodiment, first, as shown in FIG. 19A, the same state as that in FIGS. 15A to 15C is prepared.

  Next, as shown in FIG. 19B, the insulating layer 30 is etched back by wet etching or dry etching. For example, the insulating layer 30 is etched back by wet etching using a 0.5% hydrofluoric acid aqueous solution so that the height of the insulating layer 30 is the same as the height of the conductive layers 27 and 57.

  Next, as shown in the left diagram of FIG. 19C, the conductive layer 27 located between the sidewall film 61 and the sidewall film 62 is removed. Further, the insulating layer 30 is also removed. Further, as shown in the middle and right diagrams of FIG. 19C, the upper conductive layers 27 and 57 are removed from the base layer 11. Further, the insulating layer 30 is also removed. These removing means are, for example, anisotropic etching.

  In the left diagram of FIG. 19C, overetching is performed to a depth of 10 nm from the junction between the base layer 11 and the insulating layer 30 using the sidewall films 61 and 62 as a mask. As a result, a wiring layer 23 is formed between the wiring layer 21 and the wiring layer 22.

  In the middle and right diagrams of FIG. 19C, overetching is performed to a depth of 10 nm from the junction between the base layer 11 and the insulating layer 30. As a result, the wiring layer 23 and the contact plug 55 are formed in the base layer 11.

  The thickness of each of the wiring layers 21 and 22 in the Z direction is, for example, 40 nm, and the width in the Y direction is, for example, 20 nm. Further, the thickness of the wiring layer 23 in the Z direction is, for example, 40 nm, and the width in the Y direction is, for example, 14 nm. The thickness of the wiring layer 54 in the Z direction is 40 nm, for example.

  Next, as shown in FIG. 20A, the sidewall films 61 and 62 are removed by wet etching using phosphoric acid.

  Next, after the insulating layer 30 is removed, an insulating layer 33 (second insulating layer) is formed between the wiring layer 21 and the wiring layer 22 as shown in FIG. The insulating layer 33 has a dielectric constant lower than that of the insulating layers 30 and 31. The thickness of the insulating layer 33 in the Z direction is, for example, 100 nm.

  As the material of the insulating layer 33, for example, a so-called low dielectric constant material having a relative dielectric constant of 3.7 or less is selected. Thereby, the parasitic capacitance between the wiring layer 21 and the wiring layer 22 is further reduced as compared with the case where silicon oxide (relative dielectric constant: 4.0 to 4.5) is used as the material of the insulating layer 33.

  Examples of the low dielectric constant material include inorganic films such as fluorinated silicon oxide film (FSG), carbon-containing silicon oxide film (SiOC), hydrogen silsesquioxane (HSQ), and methyl silsesquioxane (MSQ), poly Examples thereof include organic materials such as allyl ether, benzocyclobutene, and polytetrafluoroethylene, and porous silica materials having a pore structure in the film.

  Alternatively, in the second embodiment, after the insulating layer 30 is removed, as illustrated in FIG. 20C, the insulating layer 31 in which a gap 31 h exists between the wiring layer 21 and the wiring layer 22. May be formed. The material of the insulating layer 31 may be the same as that of the insulating layer 33.

  For example, the insulating layer 31 is formed under CVD conditions with poor step coverage. As a result, a gap 31 h is formed in the insulating layer 31 between the wiring layer 21 and the wiring layer 22. As a result, the parasitic capacitance between the wiring layer 21 and the wiring layer 22 is further reduced.

(Third embodiment)
In the third embodiment, the same manufacturing process as in FIGS. 2A to 4D is performed in advance. However, the thickness of the insulating layer 30 illustrated in FIG. 2A in the Z direction is, for example, 140 nm. Further, the width of the trench 30tb in the Y direction is 20 nm wider than the width of the trench 30ta in the Y direction.

  FIG. 21A to FIG. 25C are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the third embodiment. Here, the left diagram, the middle diagram, and the right diagram of each figure correspond to FIGS. 1A to 1C of the first embodiment.

  First, as shown in FIG. 21A, the same state as that in FIGS. 5A to 5C is prepared.

  Next, as illustrated in FIG. 21B, the conductive layer 27 is formed in the trench 30 ta and on the upper surface 30 u of the insulating layer 30. A conductive layer 57 is formed in the trench 30tb and on the upper surface 30u of the insulating layer 30. The thickness of the conductive layers 27 and 57 is, for example, 250 nm.

  Next, as shown in FIG. 22A, the conductive layers 27 and 57 are etched back. Thereby, the trenches 30ta and 30tb are formed again. The thickness of the conductive layers 27 and 57 in the Z direction is, for example, 40 nm. The removal of the conductive layers 27 and 57 is performed by at least one means such as chemical mechanical polishing, dry etching, and wet etching. For example, the conductive layers 27 and 57 are removed by a combination of CMP and dry etching or wet etching.

  Next, as shown in FIG. 22B, the sidewall film 40 is formed in each of the plurality of trenches 30ta and in the trench 30tb. The sidewall film 40 is not completely formed in each of the plurality of trenches 30ta and in the trench 30tb. That is, the thickness of the sidewall film 40 is adjusted so that the trenches 30ta and 30tb remain. The film thickness of the sidewall film 40 is, for example, 20 nm. The material of the sidewall film 40 is, for example, silicon nitride (SiN).

  Subsequently, anisotropic etching (for example, dry etching) is performed on the sidewall film 40. By this anisotropic etching, the upper side wall film 40 is removed from the upper surface 30u of the insulating layer 30, and the side wall film 40 exposed at the bottoms of the trenches 30ta and 30tb is removed. This state is shown in FIG.

  As shown in FIG. 23A, the sidewall film 41 is formed on each side surface 30wa of the plurality of trenches 30ta. Further, a sidewall film 42 is formed on each side surface 30wb of the plurality of trenches 30ta. Further, a sidewall film 43 is formed on the side surface 30wa of the trench 30tb. Further, a sidewall film 44 is formed on the side surface 30wb of the trench 30tb. The material of the sidewall films 41 to 44 is the same as that of the sidewall film 40.

  Next, as shown in FIG. 23B, the wiring layer 21 is formed under the sidewall film 41 and the wiring layer 22 is formed under the sidewall film 42. Further, the base layer 11 located between the sidewall film 41 and the sidewall film 42 is removed. As a result, a trench 11ta extending in the X direction is formed in the base layer 11.

That is, using the side wall films 41 and 42 as a mask, the conductive layer 27 located between the side wall film 41 and the side wall film 42 and a part of the base layer 11 under the conductive layer 27 are removed. Further, using the side wall films 43 and 44 as a mask, the conductive layer 57 located between the side wall film 43 and the side wall film 44 and a part of the base layer 11 under the conductive layer 57 are removed. The removing means is, for example, anisotropic etching.
Thereby, the wiring layers 21 and 22 are formed. The conductive layer 57 is divided to form the wiring layer 57. The depth in the Z direction of the trenches 11ta and 11tb provided in the base layer 11 is, for example, 50 nm. Further, the thickness of the insulating layer 30 decreases due to the influence of anisotropic etching.

  Next, in the left view of FIG. 24A, a mask layer 90 is formed. In the middle and right views of FIG. 24A, the mask layer 90 is not formed. This is to remove the folded structure of the sidewall films 41 and 42 described above.

  That is, as shown in FIG. 24B, the sidewall films 41 to 44 are removed in the middle view and the right view in FIG. The mask layer 90 is also removed. The removal of the sidewall films 41 to 44 follows, for example, a dry etching process.

  Next, as shown in FIG. 25A, conductive layers 28 and 58 are formed in the trenches 30ta and 30tb and in the trenches 11ta and 11tb. Thereby, the conductive layer 28 (second conductive layer) is formed between the wiring layer 21 and the wiring layer 22 and between the sidewall film 41 and the sidewall film 42. The thickness of the conductive layers 28 and 58 in the Z direction is, for example, 300 nm. The material of the conductive layers 28 and 58 is, for example, tungsten.

  Next, as shown in the left diagram of FIG. 25B, the upper surface of the conductive layer 28 is lowered from the upper surface 11 u of the base layer 11. That is, the conductive layer 28 between the sidewall film 41 and the sidewall film 42 is removed using the sidewall films 41 and 42 as a mask. Further, over-etching is performed to a depth of 10 nm from the junction between the base layer 11 and the insulating layer 30 using the sidewall films 41 and 42 as a mask. Thereby, the wiring layer 23 is formed between the wiring layer 21 and the wiring layer 22 and under the wiring layer 21 and the wiring layer 22.

  25B, the upper surface of the conductive layer 28 is lowered from the upper surface 11u of the base layer 11, and the wiring layer 53 is formed. Further, as shown in the right diagram of FIG. 25B, the upper surface of the conductive layer 58 is lowered from the upper surface 11u of the base layer 11, and the wiring layer 54 is formed.

  The conductive layers 28 and 58 are removed by at least one means such as chemical mechanical polishing, dry etching, and wet etching. For example, the conductive layers 28 and 58 are removed by a combination of CMP and dry etching or wet etching.

  The thickness of each of the wiring layers 21 and 22 in the Z direction is, for example, 40 nm, and the width in the Y direction is 20 nm. Further, the thickness of the wiring layer 23 in the Z direction is, for example, 40 nm, and the width in the Y direction is, for example, 20 nm. The thickness of the wiring layer 54 in the Z direction is 40 nm, for example.

  Next, as shown in FIG. 26A, the sidewall films 41 and 42 are removed by wet etching using phosphoric acid.

  Next, as illustrated in FIG. 26B, the insulating layer 33 is formed between the wiring layer 21 and the wiring layer 22. As described above, the insulating layer 33 has a dielectric constant lower than that of the insulating layers 30 and 31. The thickness of the insulating layer 33 in the Z direction is, for example, 100 nm.

  Alternatively, in the third embodiment, after the insulating layer 30 is removed, as illustrated in FIG. 26C, the insulating layer 31 in which a gap 31 h exists between the wiring layer 21 and the wiring layer 22. May be formed. The material of the insulating layer 31 may be the same as that of the insulating layer 33. Also in the third embodiment, the same effect as the first embodiment or the second embodiment can be obtained.

  The embodiment has been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the embodiments as long as they include the features of the embodiments. Each element included in each of the specific examples described above and their arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be appropriately changed.

  In addition, in the case of “part A is provided on part B”, “on” means that part A is in contact with part B and part A is provided on part B. And the site A is not in contact with the site B, and the site A is used above the site B.

  In addition, each element included in each of the above-described embodiments can be combined as long as technically possible, and combinations thereof are also included in the scope of the embodiment as long as they include the features of the embodiment. In addition, in the category of the idea of the embodiment, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the embodiment. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 1a, 1b area | region, 10 Semiconductor layer, 10d Lower surface, 11 Underlayer, 11ta, 11tb, 30ta, 30tb Trench, 11u, 27u, 30u Upper surface, 20 sets, 21, 22, 23, 53, 54, 57 Wiring layer, 21d, 22d, 23d Lower end, 21u, 22u Upper end, 21w, 22w, 30wa, 30wb Side surface, 23a part, 23w Side wall, 27, 28, 57, 58 Conductive layer, 30, 31, 33 Insulating layer, 31h Air gap 40, 41, 42, 43, 44, 60, 61, 62, 63, 64, 65 Side wall film, 50, 51, 52, 55 Contact plug, 90 Mask layer, 100 Underlayer, 101 Insulating layer, 102 Side wall film , 103 trench

Claims (6)

An underlayer,
A first wiring provided on the underlayer and extending in a first direction;
A second wiring provided on the underlayer next to the first wiring and extending in the first direction;
An insulating layer provided between the first wiring and the second wiring;
A third wiring provided between the base layer and the insulating layer and extending in the first direction;
With
A set of wirings including the first wiring, the second wiring, and the third wiring is periodically arranged in a second direction intersecting the first direction;
A semiconductor device in which each of the first wiring and the second wiring is not located immediately above the third wiring. An underlayer,
A first wiring provided on the underlayer and extending in a first direction;
A second wiring provided on the underlayer next to the first wiring and extending in the first direction;
An insulating layer provided between the first wiring and the second wiring;
A third wiring provided between the base layer and the insulating layer and extending in the first direction;
With
A semiconductor device in which a set of wirings including the first wiring, the second wiring, and the third wiring is periodically arranged in a second direction intersecting the first direction. (A) forming a first insulating layer on the underlayer;
(B) a second penetrating from the upper surface of the first insulating layer to the underlying layer, extending in a first direction parallel to the upper surface of the first insulating layer, and intersecting the first direction; Forming a plurality of first trenches arranged in a direction;
(C) forming a first conductive layer in each of the plurality of first trenches;
(D) by lowering the upper surface of the first conductive layer from the upper surface of the first insulating layer, a part of the first side surface of each of the plurality of first trenches from the first conductive layer; Exposing a part of the second side surface facing the first side surface;
(E) forming a first sidewall film on the first side surface and forming a second sidewall film on the second side surface;
(F) a first wiring extending in the first direction under the first sidewall film by removing the first conductive layer located between the first sidewall film and the second sidewall film; And forming a second wiring extending in the first direction under the second sidewall film;
A method for manufacturing a semiconductor device comprising: Between the step (b) and the step (c),
(G) forming a third sidewall film on the first side surface of each of the plurality of first trenches and forming a fourth sidewall film on the second side surface of each of the plurality of first trenches; And a process of
(H) forming a second trench extending in the first direction in the foundation layer by removing the foundation layer located between the third sidewall film and the fourth sidewall film;
(I) removing the third sidewall film and the fourth sidewall film;
Further,
In the step (c),
Forming the first conductive layer in the second trench in addition to each of the plurality of first trenches;
In the step (f),
By removing the first conductive layer located between the first sidewall film and the second sidewall film and removing the upper portion of the first conductive layer provided in the second trench, Forming the first wiring under the first side wall film and the second wiring under the second side wall film; and further, between the first wiring and the second wiring, 4. The method for manufacturing a semiconductor device according to claim 3, wherein a third wiring extending in the first direction is formed below the first wiring and the second wiring. In the step (f),
Forming the first wiring under the first side wall film and the second wiring under the second side wall film, and the lower part positioned between the first side wall film and the second side wall film; Forming a second trench extending in the first direction in the underlying layer by removing a formation;
After forming the second trench, the second conductive layer in the second trench, between the first wiring and the second wiring, and between the first sidewall film and the second sidewall film. Form the
By lowering the upper surface of the second conductive layer from the upper surface of the base layer, a third is provided between the first wiring and the second wiring and below the first wiring and the second wiring. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the wiring is formed. The step (b)
(J) On the first insulating layer, a plurality of mask layers arranged at a pitch twice that of the plurality of first trenches arranged in the second direction and extending in the first direction are formed. Process,
(K) forming a fifth sidewall film on each sidewall of the plurality of mask layers;
(L) removing the plurality of mask layers;
(M) forming the plurality of first trenches by etching the first insulating layer exposed from the fifth sidewall film;
The method for manufacturing a semiconductor device according to claim 3, wherein:

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