TW201733007A - Approaches for patterning metal line ends for back end of line (BEOL) interconnects - Google Patents

Abstract

Approaches for patterning metal line ends for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a metallization layer of an interconnect structure for a semiconductor die includes a metal line disposed in a trench of an interlayer dielectric (ILD) material layer. The ILD material layer is composed of a first dielectric material. A conductive via is disposed in the ILD material layer, below and electrically connected to the metal line. A dielectric plug is directly adjacent to the metal line and the conductive via. The dielectric plug is composed of a second dielectric material different from the first dielectric material.

Description

Method for patterning metal wire ends of back end (BEOL) interconnects

Embodiments of the present invention are in the field of semiconductor structures and processing, and in particular, methods for patterning back end of line (BEOL) interconnect metal lines.

In the past few decades, the scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to smaller and smaller features enables the density of functional units to be increased over a limited area of the semiconductor wafer. For example, shrinking the transistor size allows for the incorporation of memory or logic devices on an increased number of wafers, resulting in the manufacture of products with increased capacity. Drives more capacity, but it's not without problems. The need to optimize the performance of each device has become increasingly significant.

Integrated circuits typically include a conductive microelectronic structure, referred to in the art as a via, for electrically connecting metal lines over a via or other metal lines or other interconnects that are interconnected under the via. Through holes are typically formed by lithography procedures. Typically, the photoresist layer can be spin coated over the dielectric layer. The photoresist layer can be exposed to patterned actinic radiation by a patterned mask, and then the exposed layer can be developed to form openings in the photoresist layer. Next, the opening for the via can be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a through hole opening. Finally, the via opening can be filled with one or more metals or other conductive materials to form vias.

In the past, the size and spacing of vias have been gradually reduced, and it is expected that in the future, for at least some types of integrated circuits (eg, advanced microprocessors, chipset components, graphics wafers, etc.), the size of the vias and The spacing will continue to decline gradually. One measure of the size of the via is the critical dimension of the via opening. One measure of the via pitch is the via pitch. The via spacing represents the center-to-center distance between the nearest adjacent vias. It should be understood that scaling to smaller vias, scaling to smaller non-conducting spaces or breaks between metal lines connected by vias (referred to as "line ends", "plugs" or "cuts") may also Need to be executed.

When such a lithography procedure is used to pattern very small line ends ("plugs" or "cuts") at very small pitches, several challenges are self-presenting, especially when the pitch is about 70 nanometers (nm) or more. The hour and/or when the critical dimension of the wire end is about 35 nm or less. In addition, as the line spacing is scaled smaller and smaller over time, the coverage tolerance is often scaled faster than the lithography device can keep up.

Another such challenge is that the critical dimension of the line ends tends to scale faster than the resolution capabilities of the lithography scanner. The shrinking technique exists to reduce the critical size of the via opening. However, the amount of reduction is often the smallest The line end spacing, as well as the ability to have a sufficient optical proximity correction (OPC) neutral reduction process, does not significantly compromise line width roughness (LWR) and/or critical dimension uniformity (CDU).

Yet another such challenge is that as the critical dimension of the line ends decreases, the LWR and/or CDU characteristics of the photoresist typically need to be improved to maintain the same overall portion of the critical dimension budget. However, the LWR and/or CDU characteristics of most photoresists today do not improve as the critical dimension of the line ends decreases.

Yet another such challenge is that very small via pitches tend to be even lower than the resolution capabilities of extreme ultraviolet (EUV) lithography scanners. As a result, typically two, three or more different lithographic masks may be used, which tends to increase cost. At some point, if the spacing is continuously reduced, even with multiple masks, it may not be possible to print these very small pitch ends with an EUV scanner.

Therefore, there is a need for improvements in the field of online manufacturing technology.

100‧‧‧metallization

102‧‧‧Metal wire

103‧‧‧Bottom through hole

104‧‧‧ dielectric layer

105‧‧‧ Plug area

106‧‧‧Line trench

108‧‧‧through hole trench

110‧‧‧ hard mask layer

112‧‧‧Line trench

114‧‧‧through hole trench

116‧‧‧ Single large exposure

200‧‧‧ underlying metallization

202‧‧‧Metal wire

204‧‧‧Dielectric layer

206‧‧‧Interlayer dielectric (ILD) materials

208‧‧‧Line groove

208'‧‧‧ line trench

210‧‧‧ lower part

210'‧‧‧ lower

212A‧‧‧through hole trench

212B‧‧‧through hole trench

214‧‧‧Sacrificial materials

214'‧‧‧Sacrificial materials

216‧‧‧ patterned hard mask layer

218‧‧‧ dielectric materials

220A‧‧‧ dielectric plug

220B‧‧‧ dielectric plug

222‧‧‧Metal wire

224‧‧‧ conductive vias

300‧‧‧ seams

320‧‧‧ dielectric plug

320A‧‧‧ dielectric plug

320B‧‧‧ dielectric plug

400‧‧‧ computing device

402‧‧‧ board

404‧‧‧ processor

406‧‧‧Communication chip

500‧‧‧Intermediary

502‧‧‧First substrate

504‧‧‧second substrate

506‧‧‧Ball Gate Array (BGA)

508‧‧‧Metal interconnection

510‧‧‧through hole

512‧‧‧through through hole (TSV)

514‧‧‧ embedded devices

1A shows a plan view of a metallization layer of a prior art semiconductor device and corresponding cross-sectional views taken along the a-a' axis of the plan view.

Figure 1B shows a cross-sectional view of a wire end or plug made using a prior art processing scheme.

Figure 1C shows another cross-sectional view of a wire end or plug made using a prior art processing scheme.

2A through 2G show representations in accordance with an embodiment of the present invention. A cross-sectional view of various operations in a process for patterning a metal line end of a back end of section (BEOL) interconnect, wherein: FIG. 2A shows having an interlayer dielectric (ILD) material layer formed over the underlying metallization layer The starting structure of the line trench in the upper portion; FIG. 2B shows the structure of FIG. 2A after the formation of the via trench in the lower portion of the layer forming the ILD material; FIG. 2C shows the layer above the ILD material layer and the trench After the sacrificial material in the via trench is formed, the structure of FIG. 2B; FIG. 2D shows after patterning the sacrificial material to form an opening of a portion of the lower metallization layer between the two metal lines exposing the underlying metallization layer, 2C shows the structure of FIG. 2C after filling the opening of the sacrificial material with a dielectric material; FIG. 2F shows the structure of FIG. 2E after removing the sacrificial material to provide a dielectric plug; and FIG. 2G shows conductive After the material fills the line trenches and via trenches, the structure of Figure 2F.

3A shows a cross-sectional view of a metallization layer comprising an interconnect structure of a semiconductor die having a dielectric end or a plug therein having a seam, in accordance with an embodiment of the present invention.

3B shows a cross-sectional view of a metallization layer of an interconnect structure including semiconductor dies that are not in close proximity to the dielectric ends or plugs of the conductive vias, in accordance with an embodiment of the present invention.

Figure 4 shows an implementation in accordance with an embodiment of the present invention. Computing device.

Figure 5 is an interposer that implements one or more embodiments of the present invention.

SUMMARY OF THE INVENTION AND EMBODIMENT

Methods and resulting structures for patterning the back end of a (BEOL) interconnect wire are described. In the following description, numerous specific details are set forth, such as a It will be apparent to those skilled in the art that the embodiments of the invention may be practiced without the specific details. In other instances, well-known features such as integrated circuit design layout have not been described in detail in order not to unnecessarily obscure the embodiments of the present invention. In addition, it should be understood that the various embodiments are illustrated and

One or more embodiments described herein relate to techniques for patterning metal wire ends. Embodiments may include aspects of one or more of contact fabrication, damascene processing, dual damascene processing, interconnect fabrication, and metal line trench patterning.

In order to provide context, in advanced nodes in semiconductor fabrication, low-level interconnects are established by separate patterning procedures for line gratings, line ends, and vias. When the through hole encroaches on the line end, the fidelity of the composite pattern tends to decrease, and vice versa. The embodiments described herein provide a line end program, also known as a plug program, which eliminates the associated proximity rules. Embodiments may allow a through hole to be placed at the wire end and a large through hole to be used with a wire end.

To provide a further context, FIG. 1A shows a plan view and corresponding cross-sectional views taken along the a-a' axis of a plan view of a metallization layer of a prior art semiconductor device. Figure 1B shows a cross-sectional view of a wire end or plug made using a prior art processing scheme. Figure 1C shows another cross-sectional view of a wire end or plug made using a prior art processing scheme.

Referring to FIG. 1A, metallization layer 100 includes metal lines 102 formed in dielectric layer 104. Metal line 102 can be coupled to underlying via 103. Dielectric layer 104 can include a wire end or plug region 105. Referring to FIG. 1B, the most advanced line end or plug region 105 of the dielectric layer 104 can be fabricated by patterning the hard mask layer 110 over the dielectric layer 104, followed by etching the exposed portions of the dielectric layer 104. The exposed portions of the dielectric layer 104 can be etched to a depth suitable for forming the line trenches 106 or further etched to a depth suitable to form the via trenches 108. Referring to FIG. 1C, two vias of the wire end or plug 105 adjacent the opposing sidewalls can be fabricated in a single large exposure 116 to ultimately form the wire trench 112 and the via trench 114.

However, referring again to Figures 1A through 1C, fidelity issues and/or hard mask erosion problems may result in imperfect patterning schemes. In contrast, one or more embodiments described herein include an implementation of a program flow for constructing a line-end dielectric (plug) after a trench and via patterning process.

In one aspect, next, one or more embodiments described herein relate to a space or interruption of non-conductivity between the construction of metal lines (in some embodiments, and associated conductive vias) (referred to as The method of "line end", "plug" or "cut". By definition, conductive vias are used to drop On the metal pattern of the previous layer. In this regard, the embodiments described herein result in a more robust interconnect manufacturing scheme since the alignment by the lithography apparatus is less dependent. Such interconnect fabrication methods can be used to relax alignment/exposure limitations, can be used to improve electrical contact (eg, by reducing via resistance), and can be used to reduce overall program operation and to pattern these features using conventional methods. The processing time required.

In an exemplary processing scheme, Figures 2A through 2G show cross-sectional views of various operations of a program representative of a wire end of a patterned back-end (BEOL) interconnect, in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a method of fabricating a metallization layer of an interconnect structure of a semiconductor die is included in an upper portion (above the lower portion 210) of an interlayer dielectric (ILD) material layer 206 formed over the underlying metallization layer 200. A line trench 208 is formed. The underlying metallization layer 200 includes metal lines 202 disposed on the dielectric layer 204.

Referring to FIG. 2B, via trenches 212A and 212B are formed in a lower portion 210 of the ILD material layer 206 to form a patterned lower portion 210' of the ILD material layer 206. As an exemplary embodiment, via trenches 212A expose two metal lines 202 of underlying metallization layer 200, while via trenches 212B expose one metal line 202 of underlying metallization layer 200.

Referring to FIG. 2C, a sacrificial material 214, such as a host material, is formed over the ILD material layer (shown in portion 210' of FIG. 2C) and in the line trench 208 and via trenches 212A and 212B. In an embodiment, as shown in FIG. 2C, a patterned hard mask layer 216 is formed over sacrificial material 214.

Referring to FIG. 2D, the sacrificial material 214 is patterned to form an opening exposing a portion of the lower metallization layer 200 between the two metal lines 202 of the underlying metallization layer 200 associated with the via trench 212A of FIG. 2B (FIG. 2D) The opening on the left side). In the exemplary embodiment shown, the sacrificial material 214 is further patterned to form an opening that exposes a portion of the patterned lower portion 210' of the ILD material layer adjacent to the via trench 212B of FIG. 2B (right side of FIG. 2D) Opening). In an embodiment, the sacrificial material 214 is patterned by patterning the patterned hard mask 216 to the sacrificial material 214 by an etch process.

Referring to FIG. 2E, the opening of the sacrificial material 214 (now shown as patterning and filling the sacrificial material 214') is filled with a dielectric material 218. In one embodiment, the opening of the sacrificial material 214 is filled with a dielectric material 218 using a deposition process selected from the group consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD). In one embodiment, the opening of the sacrificial material 214 is filled with a dielectric material 218 of a first dielectric material composition. In one such embodiment, the ILD material layer 206 comprises a second dielectric material comprised of a different material than the first dielectric material composition. In another such embodiment, however, the ILD material layer 206 is comprised of a first dielectric material.

Referring to Figure 2F, the filled sacrificial material 214' is removed to provide dielectric plugs 220A and 220B. In the exemplary embodiment shown, dielectric plug 220A is disposed in a portion of lower metallization layer 200 between two metal lines 202 of underlying metallization layer 200. Dielectric plug 220A is adjacent to via trench 212A and trench 208' and is shown in FIG. 2F In the case, it is between the substantially symmetrical via trench 212A and the trench 208'. Dielectric plug 220B is disposed on a portion of patterned lower portion 210' of ILD material layer 206. The dielectric plug 220B is adjacent to the via trench 212B and the corresponding line trench (on the right side of the dielectric plug 220B). In an embodiment, the structure of FIG. 2E is subjected to a planarization process for removing the cap layer region of dielectric material 218 to remove the patterned hard mask 216 and reduce the height of sacrificial material 214' and the dielectric therein. A portion of electrical material 218. The sacrificial material 214' is then removed by using selective wet or dry process etching techniques.

Referring to FIG. 2G, the line trench 208' and the via trenches 212A and 212B are filled with a conductive material. In one embodiment, the line trenches 208' and via trenches 212A and 212B are filled with a metal material 222 and conductive vias 224 formed of a conductive material in the patterned dielectric layer 210'. In an exemplary embodiment, with reference to plug 220A, first metal line 222 and first conductive via 224 are directly adjacent to the left side wall of dielectric plug 220A. The second metal line 222 and the second conductive via 224 are directly adjacent to the right side wall of the dielectric plug 220A. Referring to plug 220B, first metal line 222 is directly adjacent to the right side wall of dielectric plug 220B, and the bottom portion of patterned lower portion 210' of the ILD layer is directly adjacent to first conductive via 224. However, on the left side of the dielectric plug 220B, only the metal line 22, rather than the associated conductive via, is associated with the dielectric plug 220B. In an embodiment, the metal fill process is performed by depositing on the structure of FIG. 2F and then planarizing one or more metal layers.

Referring again to Figure 2G, the illustration can be used to illustrate several The same embodiment. For example, in an embodiment, the structure of Figure 2G represents the final metallization layer structure. In another embodiment, the dielectric plugs 220A and 22B are removed to provide an air gap structure. In another embodiment, dielectric plugs 220A and 22B are replaced by another dielectric material. In another embodiment, the dielectric plugs 220A and 22B may be sacrificial patterns that are ultimately transferred to another bottom interlayer dielectric material layer.

In an exemplary embodiment, referring again to FIG. 2G (and previous processing operations), the metallization layer of the interconnect structure of the semiconductor die includes a trench 208' disposed in the interlayer dielectric (ILD) material layer 206. Metal wire 222. The ILD material layer 206 is made of a first dielectric material. Conductive vias 224 are disposed in ILD material layer 206, under metal lines 222, and electrically connected to metal lines 222. Dielectric plug 220A (or 220B) is directly adjacent to metal line 222 and conductive via 224. The second metal line 222 and the conductive via 224 may also be directly adjacent to the dielectric plug (eg, dielectric plug 220A). In one embodiment, the dielectric plug 220A (or 220B) is made of a second dielectric material that is different than the first dielectric material.

It will be appreciated that filling the opening of the sacrificial material 214 with a dielectric material can result in a seam formed in the dielectric material at the center of the resulting dielectric plug. For example, FIG. 3A shows a cross-sectional view of a metallization layer comprising an interconnect structure of a semiconductor die having a dielectric end or a plug therein having a seam, in accordance with an embodiment of the present invention.

Referring to FIG. 3A, the metallization layer of the interconnect structure of the semiconductor die includes a metal line 220 (shown in the lower portion 210') disposed in a trench of an interlayer dielectric (ILD) material layer. Conductive through holes 224 are provided in the ILD material In the material layer 210', under the metal line 222 and electrically connected to the metal line 222. Dielectric plugs 320A and 320B are directly adjacent to metal line 222 and conductive via 224. Dielectric plugs 320A and 320B each include a seam 300 about the center of the dielectric plug, for example, due to deposition by chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form a dielectric plug.

It should be understood that the wire ends or plugs may be associated with metal wires that do not have an underlying via that is in close proximity to the dielectric plug. For example, FIG. 3B shows a cross-sectional view of a metallization layer of an interconnect structure including semiconductor dies that are not in close proximity to the dielectric ends or plugs of the conductive vias, in accordance with an embodiment of the present invention. Referring to FIG. 3B, the dielectric plug 320 is associated with a metal line 222 that does not have an underlying via such as via 224 that is in close proximity to the dielectric plug 320.

3A or 3B can then be used as a basis for forming subsequent metal lines/vias and ILD layers, such as the resulting structure described in association with FIG. 2G. Alternatively, the structure of FIG. 2G, FIG. 3A, or FIG. 3B may represent the final metal interconnect layer in the integrated circuit. It should be understood that the above described program operations may be performed in alternative sequences, rather than each operation being performed and/or additional program operations being performed. In an embodiment, the offset that must be tolerated by conventional lithography/dual damascene patterning is a factor that is mitigated for the resulting structure described herein. It will also be appreciated that in subsequent fabrication operations, the dielectric layer(s) may be removed to provide an air gap between the resulting metal lines.

In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material is comprised of or comprises a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, an oxide of cerium (eg, cerium oxide (SiO ₂ )), a nitride of cerium (eg, cerium nitride (Si ₃ N ₄ )), doping of cerium Oxides, cerium fluoride oxides, cerium carbon doped oxides, various low k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In an embodiment, as also used throughout this specification, the interconnect material is comprised of one or more metals or other electrically conductive structures. A common example is the use of copper wires and structures that may or may not include a barrier between copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of various metals. For example, the metal interconnects can include barrier layers, stacks of different metals, alloys, and the like. Interconnect lines are sometimes referred to in the art as traces, wires, wires, metals, or simple interconnects.

In an embodiment, as also used throughout this specification, the hard mask material is comprised of a dielectric material that is different from the interlayer dielectric material. In one embodiment, different hard mask materials can be used in different regions to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer comprises a tantalum nitride layer (eg, tantalum nitride) or tantalum oxide layer, or a combination of both or a combination thereof. Other suitable materials may include carbon based materials such as tantalum carbide. In another embodiment, the hard mask material comprises a metallic species. For example, the hard mask or other capping material may comprise a nitride layer of titanium (eg, titanium nitride) or other metal. Potentially lesser amounts of other materials such as oxygen may be included in one or more of these layers. Alternatively, other hard mask layers known in the art It can be used according to a specific implementation. The hard mask layer may be formed by CVD, PVD, or by other deposition methods.

It should be understood that the layers and materials described with respect to Figures 2A-2G, Figures 3A and 3B are typically formed on or over a semiconductor substrate or structure, such as the underlying device layer(s) of the integrated circuit. In one embodiment, the underlying semiconductor substrate represents a general workpiece object used to fabricate an integrated circuit. A semiconductor substrate typically comprises a wafer or other germanium or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal germanium, polycrystalline germanium, and germanium on insulator (SOI), as well as similar substrates formed from other semiconductor materials. The semiconductor substrate usually includes a transistor, an integrated circuit, or the like depending on the manufacturing stage. The substrate may also comprise semiconductor materials, metals, dielectrics, dopants, and other materials that are common in semiconductor substrates. Furthermore, the structure shown in FIG. 1G or 3F can be fabricated in an interconnect layer of a lower layer of the underlying layer.

As noted above, the patterned features can be patterned in a grating-like pattern of lines, holes or trenches having a certain pitch and spaced apart. For example, the pattern can be fabricated by a pitch dichotomy or a pitch quadrature method. In an example, blanket film (eg, polysilicon film) use may be patterned with respect to, for example, spacer-based quadratic patterning (SBQP) or pitch quadrature lithography and etching processes. It should be understood that the grating pattern of the line can be fabricated by a variety of methods, including 193 nm immersion lithography (193i), EUV and/or EBDW lithography, directed self-assembly, and the like.

In an embodiment, the lithography operation is performed using 193 nm immersion lithography (193i), EUV and/or EBDW lithography, and the like. can use Positive or negative adjustment of photoresist. In one embodiment, the lithography mask is a three layer mask consisting of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In certain such embodiments, the topographic masking portion is a carbon hard mask (CHM) layer and the anti-reflective coating layer is a tantalum ARC layer.

In order to provide further context for the above embodiments, patterning and aligning features at pitches less than about 50 nanometers requires many masks and strict alignment strategies that are extremely expensive for semiconductor fabrication processes. In general, the embodiments described herein relate to the fabrication of metal and line end patterns based on locations of orthogonal grating structures that can be aligned with the underlying layer. Embodiments disclosed herein can be used to fabricate a variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, a semiconductor memory can be fabricated. In addition, integrated circuits or other microelectronic devices can be used with a wide variety of electronic devices known in the art. For example, in a computer system (for example, a desktop computer, a laptop computer, a server), a cellular phone, a personal electronic device, or the like. The integrated circuit can be coupled to the bus bar and other components in the system. For example, the processor can be coupled to a memory, a chipset, etc. by one or more bus bars. Each of the processor, memory, and wafer set may potentially be fabricated using the methods disclosed herein.

FIG. 4 shows a computing device 400 in accordance with an implementation of the present invention. The computing device 400 houses a board 402. The board 402 can include a number of components including, but not limited to, a processor 404 and at least one communication chip 406. Processor 404 can be physically and electrically coupled to board 402. In some In implementation, at least one of the communication chips 406 can also be physically and electrically coupled to the board 402. In other implementations, communication chip 406 can be part of processor 404.

Computing device 400 may include other components that may or may not be physically and electrically coupled to board 402, depending on its application. These other components may include, but are not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, Antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras and Large-capacity storage devices (such as hard drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

The communication chip 406 can be used to communicate wireless communications to and from the computing device 400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which may be transmitted by non-solid media using modulated electromagnetic radiation. This term does not imply that the associated device does not contain any wires, although in some embodiments they may not. Communication chip 406 can implement any number of wireless standards or protocols including, but not limited to, Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+ , HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof and those designated as 3G, 4G, 5G And any other wireless agreement after that. Computing device 400 can include a plurality of communication chips 406. For example, the first communication chip 406 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 406 can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev. -DO and others.

Processor 404 of computing device 400 includes integrated circuit dies that are packaged within processor 404. In some implementations of embodiments of the present invention, the integrated circuit die of the processor includes one or more structures, such as a metal having metal wire ends (plugs or slits) established in accordance with an embodiment of the present invention. Interconnect layer. The term "processor" may refer to any device or device that processes electronic material from a register and/or memory to convert the electronic data into other electronic material that can be stored in a register and/or memory. section.

Communication chip 406 may also include integrated circuit dies that are packaged within communication chip 406. According to other implementations of embodiments of the present invention, the integrated circuit die of the communication chip includes one or more structures, such as metal interconnects having metal wire ends (plugs or slits) established in accordance with implementations of embodiments of the present invention. Linked department.

In a further implementation, another component housed within computing device 400 can include integrated circuit dies that include one or more structures, such as metal wire ends (plugs) that have been implemented in accordance with implementations of embodiments of the present invention. Or a metal interconnect layer of the slit).

In various implementations, computing device 400 can be a laptop, a small notebook, a notebook, an ultra-thin computer, a smart phone, a flat Board computer, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player Or digital video recorder. In further implementations, computing device 400 can be any other electronic device for processing data.

FIG. 5 shows an interposer 500 that includes one or more embodiments of the present invention. The interposer 500 is an intervening substrate for bridging the first substrate 502 to the second substrate 504. The first substrate 502 can be, for example, an integrated circuit die. The second substrate 504 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the interposer 500 is to spread connections to wider spacing and/or to reroute connections to different connections. For example, the interposer 500 can couple the integrated circuit die to a ball gate array (BGA) 506 that can then be coupled to the second substrate 504. In some embodiments, the first and second substrates 502 / 504 are attached to opposite sides of the interposer 500. In other embodiments, the first and second substrates 502 / 504 are attached to the same side of the interposer 500. And in a further embodiment, three or more substrates are interconnected by means of interposer 500.

The interposer 500 may be formed of an epoxy resin, a glass fiber reinforced epoxy resin, a ceramic material, or a polymeric material such as polyimide. In a further implementation, the interposer may be formed from alternative rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as tantalum, niobium, and other III-V and IV materials.

The interposer may include a metal interconnect 508 and a via 510, Includes, but is not limited to, a through hole (TSV) 512. The interposer 500 can further include an embedded device 514 that includes passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices can also be formed on the interposer 500. According to an embodiment, the apparatus or program disclosed herein may be used to fabricate the interposer 500.

Accordingly, embodiments of the present invention include methods for patterning metal line ends of back end of line (BEOL) interconnects, as well as resulting structures.

In one embodiment, a metallization layer for an interconnect structure of semiconductor dies includes metal lines disposed in trenches of an interlayer dielectric (ILD) material layer. The layer of ILD material consists of a first dielectric material. a conductive via disposed in the ILD material layer below the metal line and electrically connected to the metal line. A dielectric plug directly adjacent to the metal line and the conductive via. The dielectric plug is comprised of a second dielectric material that is different than the first dielectric material.

In one embodiment, the metal line and the conductive via are adjacent to the first sidewall of the dielectric plug. The metallization layer further includes a second metal line disposed in the second trench of the ILD material layer directly adjacent to the opposite second sidewall of the dielectric plug.

In one embodiment, the metallization layer further includes a second conductive via disposed in the ILD material layer, under the second metal line, and electrically connected to the second metal line, and directly adjacent to the Dielectric plug The second side wall.

In one embodiment, a portion of the ILD material layer is directly under the second metal line, the second metal line being directly adjacent to the second sidewall of the dielectric plug.

In one embodiment, the dielectric plug includes a seam about the center of the dielectric plug.

In one embodiment, a metallization layer for an interconnect structure of semiconductor dies includes metal lines disposed in trenches of an interlayer dielectric (ILD) material layer. a conductive via disposed in the ILD material layer below the metal line and electrically connected to the metal line. A dielectric plug directly adjacent to the metal line and the conductive via, the dielectric plug including a seam about the center of the dielectric plug.

In one embodiment, the metal line and the conductive via are adjacent to the first sidewall of the dielectric plug. The metallization layer further includes a second metal line disposed in the second trench of the ILD material layer directly adjacent to the opposite second sidewall of the dielectric plug.

In one embodiment, the metallization layer further includes a second conductive via disposed in the ILD material layer, under the second metal line, and electrically connected to the second metal line, and directly adjacent to the The second side wall of the dielectric plug.

In one embodiment, a portion of the ILD material layer is directly under the second metal line, the second metal line being directly adjacent to the second sidewall of the dielectric plug.

In one embodiment, a fabrication for a semiconductor die A method of metallizing a layer of interconnect structure, the method comprising: forming a trench in an upper portion of an interlayer dielectric (ILD) material layer formed over the underlying metallization layer. The method also includes forming a via trench in the lower portion of the ILD material layer, the via trench exposing the two metal lines of the underlying metallization layer. The method also includes forming a sacrificial material over the layer of ILD material and in the trench of the line and the via. The method also includes patterning the sacrificial material to form an opening that exposes a portion of the lower metallization layer between the two metal lines of the underlying metallization layer. The method also includes filling the opening of the sacrificial material with a dielectric material. The method also includes removing the sacrificial material to provide a dielectric plug on the portion of the lower metallization layer between the two metal lines of the underlying metallization layer. The method also includes filling the line trench and the via trench with a conductive material.

In one embodiment, filling the line trench with the conductive material and the via trench include forming a first metal line in the line trench and forming a first conductive via in the via trench, the first A metal line and the first conductive via are directly adjacent to the first sidewall of the dielectric plug.

In one embodiment, filling the line trench with the conductive material and the via trench include forming a second metal line in the line trench and forming a second conductive via in the via trench, the first The second metal line and the second conductive via are directly adjacent to the second sidewall of the dielectric plug relative to the first sidewall.

In one embodiment, filling the opening of the sacrificial material with the dielectric material comprises using a deposition process selected from the group consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD).

In one embodiment, filling the opening of the sacrificial material with the dielectric material comprises forming a seam at the center of the dielectric plug at the center of the dielectric material.

In one embodiment, the opening in which the sacrificial material is filled with the dielectric material comprises filling with a first dielectric material composition.

In one embodiment, the ILD material layer comprises a second dielectric material composition that is different from the first dielectric material composition.

In one embodiment, the ILD material layer comprises the first dielectric material composition.

In one embodiment, the sacrificial material is patterned to include a patterned hard mask on the sacrificial material, and the pattern of the patterned hard mask is transferred to the sacrificial material by an etch process.

In one embodiment, removing the sacrificial material includes planarizing the sacrificial material and the dielectric material, and then selectively etching away the remaining portion of the sacrificial material.

In one embodiment, a method for fabricating a metallization layer of an interconnect structure of a semiconductor die includes forming a trench in an upper portion of an interlayer dielectric (ILD) material layer formed over an underlying metallization layer . The method also includes forming a sacrificial material over the layer of ILD material and in the trench of the line. The method also includes patterning the sacrificial material to form an opening that exposes a portion of a lower portion of the layer of ILD material. The method also includes filling the opening of the sacrificial material with a dielectric material. The method also includes removing the sacrificial material to provide a dielectric plug on the portion of the lower portion of the layer of ILD material. The method also includes filling the line trench with a conductive material.

In one embodiment, filling the line trench with the conductive material includes forming a first metal line in the line trench, the first metal line directly adjacent to the first sidewall of the dielectric plug, and A second metal line is formed in the line trench, the second metal line being directly adjacent to the second sidewall of the dielectric plug relative to the first sidewall.

In one embodiment, filling the opening of the sacrificial material with the dielectric material comprises using a deposition process selected from the group consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD).

In one embodiment, filling the opening of the sacrificial material with the dielectric material comprises forming a seam at the center of the dielectric plug at the center of the dielectric material.

In one embodiment, the opening of the sacrificial material filled with the dielectric material comprises filling with a first dielectric material composition, and the ILD material layer comprises a second dielectric material different from the first dielectric material composition. ingredient.

In one embodiment, filling the opening of the sacrificial material with the dielectric material comprises filling with a first dielectric material composition, and the ILD material layer comprises the first dielectric material composition.

200‧‧‧ underlying metallization

202‧‧‧Metal wire

204‧‧‧Dielectric layer

206‧‧‧Interlayer dielectric (ILD) materials

208‧‧‧Line groove

210‧‧‧ lower part

Claims (25)

A metallization layer for an interconnect structure of a semiconductor die, the metallization layer comprising: a metal line disposed in a trench of an interlayer dielectric (ILD) material layer, the ILD material layer comprising a first dielectric a conductive via disposed in the ILD material layer below the metal line and electrically connected to the metal line; and a dielectric plug directly adjacent to the metal line and the conductive via The electrical plug includes a second dielectric material that is different than the first dielectric material. The metallization layer of claim 1, wherein the metal line and the conductive via are adjacent to the first sidewall of the dielectric plug, the metallization layer further comprising: a layer disposed on the ILD material layer A second metal line in the second trench that is directly adjacent to the opposite second sidewall of the dielectric plug. The metallization layer of claim 1, further comprising: a second conductive via disposed in the ILD material layer, under the second metal line and electrically connected to the second metal line, and directly Adjacent to the second sidewall of the dielectric plug. The metallization layer of claim 1, wherein a portion of the ILD material layer is directly under the second metal line, the second metal line being directly adjacent to the second sidewall of the dielectric plug . The metallization layer of claim 1, wherein the dielectric plug comprises a seam about the center of the dielectric plug. A metallization layer for an interconnect structure of a semiconductor die, the metallization layer comprising: a metal line disposed in a trench of an interlayer dielectric (ILD) material layer; a conductive via disposed at the ILD a dielectric layer under the metal line and electrically connected to the metal line; and a dielectric plug directly adjacent to the metal line and the conductive via, the dielectric plug including the dielectric plug The seam of the center. The metallization layer of claim 6, wherein the metal line and the conductive via are adjacent to the first sidewall of the dielectric plug, the metallization layer further comprising: a layer disposed on the ILD material layer A second metal line in the second trench that is directly adjacent to the opposite second sidewall of the dielectric plug. The metallization layer of claim 6, further comprising: a second conductive via disposed in the ILD material layer, under the second metal line and electrically connected to the second metal line, and directly Adjacent to the second sidewall of the dielectric plug. The metallization layer of claim 6, wherein a portion of the ILD material layer is directly under the second metal line, the second metal line being directly adjacent to the second sidewall of the dielectric plug . A method of fabricating a metallization layer for an interconnect structure of a semiconductor die, the method comprising: an interlayer dielectric (ILD) material formed over the underlying metallization layer a line trench is formed in an upper portion of the layer; a via trench is formed in a lower portion of the layer of ILD material, the via trench exposing two metal lines of the underlying metallization layer; above and over the layer of ILD material Forming a sacrificial material in the trench and the via trench; patterning the sacrificial material to form an opening exposing a portion of the lower metallization layer between the two metal lines of the underlying metallization layer; a material filling the opening of the sacrificial material; removing the sacrificial material to provide a dielectric plug on the portion of the lower metallization layer between the two metal lines of the underlying metallization layer; and a conductive material The line trench and the via trench are filled. The method of claim 10, wherein filling the line trench with the conductive material and the via trench comprises forming a first metal line in the line trench and forming a first conductive layer in the via trench a via, the first metal line and the first conductive via being directly adjacent to the first sidewall of the dielectric plug. The method of claim 11, wherein filling the line trench with the conductive material and the via trench comprises forming a second metal line in the line trench and forming a second conductive layer in the via trench a via, the second metal line and the second conductive via being directly adjacent to a second sidewall of the dielectric plug relative to the first sidewall. The method of claim 10, wherein the opening of the sacrificial material filled with the dielectric material comprises using a layer selected from the group consisting of atomic layer deposition A deposition procedure for a group consisting of (ALD) and chemical vapor deposition (CVD). The method of claim 13, wherein the opening of the sacrificial material filled with the dielectric material comprises a seam formed at the center of the dielectric plug at the center of the dielectric material. The method of claim 10, wherein the opening of the sacrificial material filled with the dielectric material comprises filling with a first dielectric material composition. The method of claim 15, wherein the ILD material layer comprises a second dielectric material component different from the first dielectric material composition. The method of claim 15, wherein the ILD material layer comprises the first dielectric material component. The method of claim 10, wherein the patterning of the sacrificial material comprises forming a patterned hard mask on the sacrificial material, and transferring the pattern of the patterned hard mask to the sacrificial material by an etching process. . The method of claim 10, wherein removing the sacrificial material comprises planarizing the sacrificial material and the dielectric material, and then selectively etching the remaining portion of the sacrificial material. A method for fabricating a metallization layer of an interconnect structure of a semiconductor die, the method comprising: forming a line trench in an upper portion of an interlayer dielectric (ILD) material layer formed over the underlying metallization layer; Forming a sacrificial material over the layer of ILD material and in the trench of the line; patterning the sacrificial material to form an opening exposing a portion of a lower portion of the layer of ILD material; filling the opening of the sacrificial material with a dielectric material; The sacrificial material to provide a dielectric plug on the portion of the lower portion of the ILD material layer; and to fill the line trench with a conductive material. The method of claim 20, wherein filling the line trench with the conductive material comprises forming a first metal line in the line trench, the first metal line directly adjacent to the first of the dielectric plug a sidewall, and a second metal line formed in the trench, the second metal line being directly adjacent to the second sidewall of the dielectric plug relative to the first sidewall. The method of claim 20, wherein filling the opening of the sacrificial material with the dielectric material comprises using a deposition process selected from the group consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD). The method of claim 22, wherein the opening of the sacrificial material filled with the dielectric material comprises a seam formed at the center of the dielectric plug at the dielectric material. The method of claim 20, wherein the opening of the sacrificial material filled with the dielectric material comprises filling with a first dielectric material composition, and the ILD material layer comprises a different composition than the first dielectric material. The second dielectric material composition. For example, the method of claim 20, wherein the dielectric is The opening of the material filling the sacrificial material comprises filling with a first dielectric material composition, and the ILD material layer comprises the first dielectric material composition.