TW202230621A - Metallization layer of an interconnect structure for a semiconductor die, method of fabricating the metallization layer, integrated circuit structure comprising the metallization layer and computing device comprising the integrated circuit structure - Google Patents

Abstract

Approaches for patterning metal line ends for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a metallization layer of an interconnect structure for a semiconductor die includes a metal line disposed in a trench of an interlayer dielectric (ILD) material layer. The ILD material layer is composed of a first dielectric material. A conductive via is disposed in the ILD material layer, below and electrically connected to the metal line. A dielectric plug is directly adjacent to the metal line and the conductive via. The dielectric plug is composed of a second dielectric material different from the first dielectric material.

Description

Metallization layer for interconnect structure of semiconductor die, method for making the metallization layer, integrated circuit structure including the metallization layer, and computing device including the integrated circuit structure

Embodiments of the present invention are in the field of semiconductor structures and processing, and in particular, methods for patterning back-end-of-line (BEOL) interconnect metal line terminations.

Feature scaling in integrated circuits has been the driving force behind the growing semiconductor industry for the past few decades. Scaling to smaller and smaller features enables the density of functional units to be increased over the limited area of a semiconductor wafer. For example, shrinking transistor size enables the incorporation of an increased number of memory or logic devices on a wafer, resulting in the fabrication of devices with increased capacity product. A larger capacity was driven, but not without problems. The need to optimize the performance of each device becomes increasingly apparent.

Integrated circuits typically include conductive microelectronic structures, known in the art as vias, for electrically connecting metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are usually formed by a lithography process. Typically, a photoresist layer can be spin-coated over a dielectric layer, the photoresist layer can be exposed to patterned actinic radiation through a patterned mask, and the exposed layer can be developed to form the Open your mouth. Next, the openings for the vias can be etched in the dielectric layer by using the openings in the photoresist layer as etch masks. This opening is called a via opening. Finally, the via openings may be filled with one or more metals or other conductive materials to form vias.

Via size and pitch have been progressively reduced in the past, and it is expected that in the future, for at least some types of integrated circuits (eg, advanced microprocessors, chip set components, patterned wafers, etc.), via size and Spacing will continue to gradually decrease. One measure of via size is the critical dimension of the via opening. One measure of via pitch is via pitch. Via pitch represents the center-to-center distance between the nearest adjacent vias. It should be understood that scaling to smaller vias, scaling to smaller non-conductive spaces or breaks between metal lines connected by vias (referred to as "line terminations", "plugs" or "cutouts") is also possible needs to be executed.

When patterning extremely small wire ends ("plugs" or "cuts") at extremely small pitches by this lithographic process, several challenges arise, especially when the pitches are on the order of 70 nanometers (nm) or more hours and/or when the line end of the Pro The realm size is about 35 nm or less. Furthermore, as the line end spacing scales smaller and smaller over time, overlay tolerances tend to scale faster than the lithography device can keep up.

Another such challenge is that the critical dimensions of the line ends generally tend to scale faster than the resolution capabilities of the lithography scanner. Shrinking techniques exist to shrink the critical dimensions of via openings. However, the amount of downscaling is often limited by the minimum line-end spacing, and by the ability of a downscaling process with sufficient optical proximity correction (OPC) neutrality without significantly compromising line width roughness (LWR) and/or critical dimension uniformity Sexuality (CDU).

Yet another such challenge is that as the critical dimension of the line ends decreases, the LWR and/or CDU characteristics of the photoresist often need to be improved to maintain the same overall portion of the critical dimension budget. However, the LWR and/or CDU characteristics of most photoresists today do not improve with the speed at which the critical dimension of the line ends decreases.

Another such challenge is that extremely small via pitches are often even below the resolution capabilities of extreme ultraviolet (EUV) lithography scanners. As a result, often two, three or more different lithography masks may be used, which tends to increase cost. At some point, even with multiple masks, printing these very fine-pitch line ends with an EUV scanner may not be possible if the pitch continues to decrease.

Accordingly, there is a need for field improvements in in-line manufacturing techniques.

100: metallization layer

102: Metal Wire

103: Bottom through hole

104: Dielectric layer

105: Plug area

106: Line Groove

108: Through hole trench

110: Hard mask layer

112: Line groove

114: Through hole trench

116: Single Big Exposure

200: Bottom metallization layer

202: Metal Wire

204: Dielectric Layer

206: Interlayer Dielectric (ILD) Materials

208: Line Groove

208': Line Groove

210: Lower

210': Lower

212A: Through Hole Trench

212B: Through-hole trench

214: Sacrificial Materials

214': Sacrificial Material

216: Patterned Hardmask Layer

218: Dielectric Materials

220A: Dielectric Plug

220B: Dielectric Plug

222: metal wire

224: Conductive Vias

300: seams

320: Dielectric Plug

320A: Dielectric Plug

320B: Dielectric Plug

400: Computing Device

402: Board

404: Processor

406: Communication chip

500:Intermediary layer

502: First substrate

504: Second substrate

506: Ball Gate Array (BGA)

508: Metal Interconnect

510: Through hole

512: Through Silicon Via (TSV)

514: Embedded Devices

FIG. 1A shows a metallization layer of a prior art semiconductor device A plan view of and the corresponding cross-sectional view taken along the a-a' axis of that plan view.

Figure IB shows a cross-sectional view of a wire end or plug fabricated using a prior art processing scheme.

Figure 1C shows another cross-sectional view of a wire end or plug fabricated using a prior art processing scheme.

2A-2G show cross-sectional views representing various operations in a process for patterning metal line terminations for back end-of-line (BEOL) interconnects, in accordance with embodiments of the present invention, wherein:

2A shows a starting structure with line trenches formed in an upper portion of an interlayer dielectric (ILD) material layer formed over an underlying metallization layer;

FIG. 2B shows the structure of FIG. 2A after the formation of via trenches in the lower portion of the layer of ILD material;

FIG. 2C shows the structure of FIG. 2B after the formation of sacrificial material over the layer of ILD material and in the line and via trenches;

2D shows the structure of FIG. 2C after patterning the sacrificial material to form openings exposing a portion of the lower metallization layer between two metal lines of the underlying metallization layer;

FIG. 2E shows the structure of FIG. 2C after filling the opening of the sacrificial material with a dielectric material;

Figure 2F shows the structure of Figure 2E after removal of the sacrificial material to provide a dielectric plug; and

FIG. 2G shows the structure of FIG. 2F after filling the line trenches and via trenches with conductive material.

FIG. 3A shows an embodiment of the invention including a A cross-sectional view of the metallization layer of the interconnect structure of the semiconductor die of the seamed dielectric wire end or plug.

3B shows a cross-sectional view of a metallization layer of an interconnect structure including a semiconductor die that is not immediately adjacent to a dielectric wire termination or plug of a conductive via, in accordance with an embodiment of the present invention.

4 shows a computing device according to one implementation of an embodiment of the present invention.

5 is an interposer implementing one or more embodiments of the present invention.

Methods and resulting structures are described for patterning metal line terminations for back end of line (BEOL) interconnects. In the following description, numerous specific details are set forth, such as specific integrations and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts have not been described in detail in order not to unnecessarily obscure embodiments of the invention. Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and have not necessarily been drawn to scale.

One or more embodiments described herein relate to techniques for patterning metal line terminations. Embodiments may include aspects of one or more of contact fabrication, damascene processing, dual damascene processing, interconnect fabrication, and metal line trench patterning.

To provide context, in advanced nodes of semiconductor fabrication, low-level interconnects are established by separate patterning procedures for wire gratings, wire terminations, and vias. The fidelity of the composite pattern tends to decrease when vias encroach on the wire ends, and vice versa. Embodiments described herein provide an end-of-line procedure, also known as a plug procedure, that eliminates the associated proximity rules. Embodiments may allow vias to be placed on the wire ends, and large vias to take over the wire ends.

To provide further context, FIG. 1A shows a plan view and a corresponding cross-sectional view taken along the a-a' axis of a plan view of a metallization layer of a prior art semiconductor device. Figure IB shows a cross-sectional view of a wire end or plug fabricated using a prior art processing scheme. Figure 1C shows another cross-sectional view of a wire end or plug fabricated using a prior art processing scheme.

Referring to FIG. 1A , metallization layer 100 includes metal lines 102 formed in dielectric layer 104 . Metal lines 102 may be coupled to bottom vias 103 . Dielectric layer 104 may include line termination or plug regions 105 . Referring to FIG. 1B , the most advanced line termination or plug regions 105 of the dielectric layer 104 may be fabricated by patterning the hard mask layer 110 on the dielectric layer 104 and then etching the exposed portions of the dielectric layer 104 . Exposed portions of dielectric layer 104 may be etched to a depth suitable for forming line trenches 106 or further etched to a depth suitable for forming via trenches 108 . Referring to FIG. 1C , the two vias of the wire end or plug 105 adjacent to opposite sidewalls may be fabricated in a single large exposure 116 to ultimately form wire trenches 112 and via trenches 114 .

However, referring again to Figures 1A-1C, fidelity issues and/or hardmask erosion issues may result in an imperfect patterning scheme. In contrast, one or more embodiments described herein include reference to trench and via patterns The realization of the process flow to construct the line-end dielectric (plug) after the process.

In one aspect, then, one or more of the embodiments described herein relate to creating non-conductive spaces or interruptions between metal lines (and, in some embodiments, associated conductive vias) (referred to as "wire ends", "plugs" or "cuts"). By definition, conductive vias are used to land on the metal patterns of previous layers. In this regard, the embodiments described herein result in a more robust interconnect fabrication scheme since alignment by lithography equipment is less dependent. Fabrication methods for such interconnects can be used to relax alignment/exposure constraints, can be used to improve electrical contact (eg, by reducing via resistance), and can be used to reduce overall process operations and pattern these features using conventional methods required processing time.

In an exemplary processing scheme, Figures 2A-2G show cross-sectional views representing various operations of a procedure for patterning metal line ends of a back end of line (BEOL) interconnect in accordance with an embodiment of the present invention.

Referring to FIG. 2A , a method of fabricating a metallization layer of an interconnect structure of a semiconductor die is included in an upper portion (above lower portion 210 ) of an interlayer dielectric (ILD) material layer 206 formed over an underlying metallization layer 200 Line trenches 208 are formed. Bottom metallization layer 200 includes metal lines 202 disposed on dielectric layer 204 .

Referring to FIG. 2B , via trenches 212A and 212B are formed in the lower portion 210 of the ILD material layer 206 to form a patterned lower portion 210 ′ of the ILD material layer 206 . As an exemplary embodiment, via trench 212A exposes two metal lines 202 of bottom metallization layer 200 , while via trench 212B exposes one metal line 202 of bottom metallization layer 200 .

Referring to Figure 2C, a sacrificial material 214, such as a host material, is formed over the layer of ILD material (shown in portion 210' of Figure 2C) and in the line trenches 208 and via trenches 212A and 212B. In an embodiment, a patterned hard mask layer 216 is formed on the sacrificial material 214 as shown in FIG. 2C .

Referring to FIG. 2D, sacrificial material 214 is patterned to form openings that expose a portion of bottom metallization layer 200 between two metal lines 202 of bottom metallization layer 200 associated with via trench 212A of FIG. 2B (FIG. 2D opening on the left). In the exemplary embodiment shown, the sacrificial material 214 is further patterned to form an opening that exposes a portion of the patterned lower portion 210' of the ILD material layer adjacent to the via trench 212B of FIG. 2B (right side of FIG. 2D ). opening). In an embodiment, the sacrificial material 214 is patterned by transferring the patterned hardmask 216 to the sacrificial material 214 by an etch process.

Referring to FIG. 2E , the openings of sacrificial material 214 (now shown patterned and filled with sacrificial material 214 ′) are filled with dielectric material 218 . In one embodiment, openings of sacrificial material 214 are filled with dielectric material 218 using a deposition process selected from the group consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD). In one embodiment, the openings of the sacrificial material 214 are filled with a dielectric material 218 of the first dielectric material composition. In one such embodiment, the layer of ILD material 206 includes a second dielectric material composed of a material of a different composition than the first dielectric material. In another of these embodiments, however, the ILD material layer 206 is composed of the first dielectric material.

Referring to Figure 2F, the filled sacrificial material 214' is removed to provide dielectric plugs 220A and 220B. In the exemplary embodiment shown, the media The electrical plug 220A is arranged in the portion of the bottom metallization layer 200 between the two metal lines 202 of the bottom metallization layer 200 . Dielectric plug 220A is adjacent to via trench 212A and line trench 208' and, in the case shown in Figure 2F, is interposed between substantially symmetrical via trench 212A and line trench 208'. Dielectric plug 220B is disposed on a portion of patterned lower portion 210 ′ of ILD material layer 206 . Dielectric plug 220B is adjacent to via trench 212B and the corresponding line trench (to the right of dielectric plug 220B). In an embodiment, the structure of FIG. 2E is subjected to a planarization process to remove the capping layer regions of the dielectric material 218 to remove the patterned hardmask 216 and reduce the height of the sacrificial material 214' and the dielectric material therein part of the electrical material 218 . The sacrificial material 214' is then removed by using selective wet or dry process etching techniques.

Referring to Figure 2G, line trenches 208' and via trenches 212A and 212B are filled with conductive material. In one embodiment, line trenches 208' and via trenches 212A and 212B are filled with metal lines 222 and conductive vias 224 formed in patterned dielectric layer 210' with conductive material. In an exemplary embodiment, referring to the plug 220A, the first metal line 222 and the first conductive via 224 are directly adjacent to the left side wall of the dielectric plug 220A. The second metal line 222 and the second conductive via 224 are directly adjacent to the right side wall of the dielectric plug 220A. Referring to the plug 220B, the first metal line 222 is directly adjacent to the right sidewall of the dielectric plug 220B, and the bottom portion of the patterned lower portion 210' of the ILD layer is directly adjacent to the first conductive via 224. However, on the left side of the dielectric plug 220B, only the metal lines 22 and not the associated conductive vias are associated with the dielectric plug 220B. In an embodiment, a metal fill process is performed by depositing and then planarizing one or more metal layers on the structure of FIG. 2F.

Referring again to Figure 2G, several different embodiments may be illustrated using the diagram. For example, in an embodiment, the structure of FIG. 2G represents the final metallization layer structure. In another embodiment, the dielectric plugs 220A and 22B are removed to provide an air gap structure. In another embodiment, the dielectric plugs 220A and 22B are replaced with another dielectric material. In another embodiment, the dielectric plugs 220A and 22B may be sacrificial patterns that are ultimately transferred to another bottom interlayer dielectric material layer.

In an exemplary embodiment, referring again to FIG. 2G (and previous processing operations), the metallization layer of the interconnect structure of the semiconductor die includes a metallization layer disposed in the trench 208 ′ of the interlayer dielectric (ILD) material layer 206 . Metal wire 222 . The ILD material layer 206 is made of a first dielectric material. Conductive vias 224 are disposed in the ILD material layer 206 below and electrically connected to the metal lines 222 . Dielectric plug 220A (or 220B) is directly adjacent to metal line 222 and conductive via 224 . Second metal lines 222 and conductive vias 224 may also be directly adjacent to dielectric plugs (eg, dielectric plug 220A). In one embodiment, the dielectric plug 220A (or 220B) is made of a second dielectric material that is different from the first dielectric material.

It will be appreciated that filling the openings of the sacrificial material 214 with dielectric material may result in the formation of a seam in the dielectric material about the center of the resulting dielectric plug. For example, FIG. 3A shows a cross-sectional view of a metallization layer of an interconnect structure including a semiconductor die with a dielectric wire end or plug having a seam therein, in accordance with an embodiment of the present invention.

3A, the metallization layer of the interconnect structure of the semiconductor die includes metal disposed in the trenches of the interlayer dielectric (ILD) material layer Line 220 (lower portion 210' shown). Conductive vias 224 are disposed in the ILD material layer 210 ′ below and electrically connected to the metal lines 222 . Dielectric plugs 320A and 320B are directly adjacent to metal lines 222 and conductive vias 224 . The dielectric plugs 320A and 320B each include a seam 300 about the center of the dielectric plug, eg, as a result of deposition by chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form the dielectric plug.

It should be understood that a wire end or plug may be associated with a metal line that does not have an underlying via next to the dielectric plug. For example, FIG. 3B shows a cross-sectional view of a metallization layer of an interconnect structure including a semiconductor die that is not immediately adjacent a dielectric wire termination or plug of a conductive via, in accordance with an embodiment of the present invention. Referring to FIG. 3B , dielectric plug 320 is associated with metal line 222 that does not have underlying vias (such as vias 224 ) adjacent to dielectric plug 320 .

3A or 3B may then be used as a basis for forming subsequent metal lines/vias and ILD layers, such as the resulting structure described in connection with FIG. 2G. Alternatively, the structures of FIG. 2G, FIG. 3A, or FIG. 3B may represent the final metal interconnect layer in an integrated circuit. It should be understood that the above-described program operations may be performed in alternate orders, and that not every operation needs to be performed and/or that additional program operations may be performed. In embodiments, the amount of offset that must be tolerated for conventional lithography/dual damascene patterning is a mitigating factor for the resulting structures described herein. It is also understood that in subsequent fabrication operations, the dielectric layer(s) may be removed to provide air gaps between the resulting metal lines.

In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (eg, silicon dioxide (SiO ₂ )), nitrides of silicon (eg, silicon nitride (Si ₃ N ₄ )), doped silicon Oxides, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In embodiments, as also used throughout this specification, the interconnect material is comprised of one or more metals or other conductive structures. A common example is the use of copper lines and structures, which may or may not contain a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of metals. For example, metal interconnects may include barrier layers, stacks or alloys of different metals, and the like. Interconnects are also sometimes referred to in the art as traces, wires, wires, metals, or simply interconnects.

In an embodiment, as also used throughout this specification, the hardmask material is composed of a dielectric material other than the interlayer dielectric material. In one embodiment, different hardmask materials may be used in different regions to provide different growth or etch selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer comprises a silicon nitride layer (eg, silicon nitride) or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials such as silicon carbide. In another embodiment, the hardmask material includes a metallic species. For example, the hardmask or other capping material may comprise a titanium nitride layer (eg, titanium nitride) or other metal. Potentially smaller amounts of other materials such as oxygen may be contained in either multiple of these layers. Alternatively, other hardmask layers known in the art may be used depending on the particular implementation. The hard mask layer may be formed by CVD, PVD or by other deposition methods.

It should be understood that the layers and materials described with respect to Figures 2A-2G, Figures 3A and 3B are generally formed on or over a semiconductor substrate or structure, such as an underlying device layer(s) of an integrated circuit. In one embodiment, the underlying semiconductor substrate represents a general workpiece object used to fabricate integrated circuits. Semiconductor substrates typically include wafers or other silicon wafers or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, monocrystalline silicon, polycrystalline silicon, and silicon-on-insulator (SOI), as well as similar substrates formed from other semiconductor materials. Depending on the manufacturing stage, semiconductor substrates typically contain transistors, integrated circuits, and the like. The substrate may also contain semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the structures shown in Figures 1G or 3F can be fabricated at the underlying lower interconnect layers.

As described above, the patterned features may be patterned in a raster-like pattern of lines, holes, or trenches that are spaced at a certain pitch and have a certain width. For example, patterns can be fabricated by pitch bisection or pitch quadrant. In an example, a blanket film, such as a polysilicon film, is patterned using a lithography and etch process that may be related, for example, to spacer based quadruple patterning (SBQP) or pitch quarting. It should be understood that the grating pattern of lines can be fabricated by a variety of methods, including 193 nm immersion lithography (193i), EUV and/or EBDW lithography, directed self-assembly, and the like.

In an embodiment, the lithography operation is performed using 193 nm immersion lithography (193i), EUV and/or EBDW lithography, or the like. Positive tuning can be used or negative dimming resistors. In one embodiment, the lithography mask is a three-layer mask consisting of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In certain such embodiments, the topographic masking portion is a carbon hardmask (CHM) layer, and the antireflective coating layer is a silicon ARC layer.

To provide further context for the above-described embodiments, patterning and aligning features at pitches less than about 50 nanometers requires many reticles and stringent alignment strategies, which are prohibitively expensive for semiconductor fabrication processes. In general, the embodiments described herein relate to the fabrication of metal and line end patterns based on the locations of the overlaying orthogonal grating structures that can be aligned with the underlying layers. Embodiments disclosed herein may be used to fabricate many different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memory may be fabricated. Furthermore, integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art. For example, in computer systems (eg, desktop computers, laptop computers, servers), cellular telephones, personal electronic devices, and the like. Integrated circuits may be coupled with bus bars and other components in the system. For example, a processor may be coupled to a memory, chip set, etc. by one or more bus bars. Each of processors, memories, and chipsets may potentially be fabricated using the methods disclosed herein.

FIG. 4 shows a computing device 400 according to one implementation of the present invention. The computing device 400 houses the board 402 . Board 402 may include a number of components including, but not limited to, processor 404 and at least one communication die 406 . The processor 404 may be physically and electrically coupled to the board 402 . In some implementations, At least one communication die 406 may also be physically and electrically coupled to board 402 . In other implementations, the communication die 406 may be part of the processor 404 .

Depending on its application, computing device 400 may include other elements that may or may not be physically and electrically coupled to board 402 . These other components may include, but are not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, Antennas, monitors, touchscreen monitors, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras and Mass storage devices (such as hard disks, compact discs (CDs), digital versatile discs (DVDs), etc.).

Communication chip 406 may enable wireless communication for data transfer to and from computing device 400 . The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which can transmit data through non-solid state media through the use of modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. Communication chip 406 may implement any number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+ , HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof and those designated as 3G, 4G, 5G and any other thereafter wireless protocol. Computing device 400 may include a plurality of communication chips 406 . For example, the first communication chip 406 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 406 can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev -DO and others.

The processor 404 of the computing device 400 includes an integrated circuit die packaged within the processor 404 . In some implementations of embodiments of the present invention, the integrated circuit die of the processor includes one or more structures, such as metal with metal wire terminations (plugs or cutouts) established in accordance with implementations of embodiments of the present invention Interconnect layer part. The term "processor" may refer to any device or device that processes electronic data from scratchpad and/or memory to convert the electronic data into other electronic data that may be stored in scratchpad and/or memory. part.

The communication die 406 may also include an integrated circuit die packaged within the communication die 406 . According to other implementations of embodiments of the present invention, the integrated circuit die of the communication chip includes one or more structures, such as metal interconnects with metal wire terminations (plugs or cutouts) established according to implementations of embodiments of the present invention Layers Department.

In further implementations, another element housed within computing device 400 may contain an integrated circuit die that contains one or more structures, such as metal wire terminations (plugs) with implementations established in accordance with embodiments of the present invention. or notch) of the metal interconnect layer portion.

In various implementations, computing device 400 may be a laptop computer, a small notebook computer, a notebook computer, an ultraportable computer, a smartphone, a tablet Computers, personal digital assistants (PDAs), ultra-mobile PCs, mobile phones, desktop computers, servers, printers, scanners, monitors, set-top boxes, entertainment control units, digital cameras, portable music players Or a digital video recorder. In further implementations, computing device 400 may be any other electronic device for processing data.

FIG. 5 shows an interposer 500 including one or more embodiments of the present invention. The interposer 500 is an intervening substrate for bridging the first substrate 502 to the second substrate 504 . The first substrate 502 may be, for example, an integrated circuit die. The second substrate 504 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of interposer 500 is to spread connections to wider spacing and/or to reroute connections to different connections. For example, the interposer 500 may couple the integrated circuit die to a ball gate array (BGA) 506 which may then be coupled to the second substrate 504 . In some embodiments, the first and second substrates 502 / 504 are attached to opposite sides of the interposer 500 . In other embodiments, the first and second substrates 502 / 504 are attached to the same side of the interposer 500 . And in further embodiments, three or more substrates are interconnected by means of the interposer 500 .

The interposer 500 may be formed of epoxy, glass fiber reinforced epoxy, ceramic materials, or polymeric materials such as polyimide. In further implementations, the interposer may be formed of alternative rigid or flexible materials that may include the same materials used in semiconductor substrates described above, such as silicon, germanium, and other III-V and IV materials.

The interposer may include metal interconnects 508 and vias 510 , including but not limited to through-silicon vias (TSVs) 512 . The interposer 500 can enter A step includes embedded devices 514, which include passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices can also be formed on the interposer 500 . According to an embodiment, the apparatus or process disclosed herein may be used to manufacture the interposer 500 .

Accordingly, embodiments of the present invention include methods for patterning metal line terminations for back end of line (BEOL) interconnects, and resulting structures.

In one embodiment, a metallization layer for an interconnect structure of a semiconductor die includes metal lines disposed in trenches in a layer of interlayer dielectric (ILD) material. The ILD material layer consists of a first dielectric material. A conductive via is disposed in the ILD material layer below the metal line and electrically connected to the metal line. A dielectric plug directly adjacent to the metal line and the conductive via. The dielectric plug is composed of a second dielectric material different from the first dielectric material.

In one embodiment, the metal line and the conductive via are adjacent to the first sidewall of the dielectric plug. The metallization layer further includes a second metal line disposed in the second trench of the ILD material layer directly adjacent to the opposite second sidewall of the dielectric plug.

In one embodiment, the metallization layer further includes a second conductive via disposed in the ILD material layer below and electrically connected to the second metal line and directly adjacent to the second metal line the second sidewall of the dielectric plug.

In one embodiment, a portion of the layer of ILD material is directly under the second metal line, which is directly adjacent to the second sidewall of the dielectric plug.

In one embodiment, the dielectric plug includes a seam about the center of the dielectric plug.

In one embodiment, a metallization layer for an interconnect structure of a semiconductor die includes metal lines disposed in trenches in a layer of interlayer dielectric (ILD) material. A conductive via is disposed in the ILD material layer below the metal line and electrically connected to the metal line. A dielectric plug directly adjacent the metal line and the conductive via, the dielectric plug including a seam about the center of the dielectric plug.

In one embodiment, the metal line and the conductive via are adjacent to the first sidewall of the dielectric plug. The metallization layer further includes a second metal line disposed in the second trench of the ILD material layer directly adjacent to the opposite second sidewall of the dielectric plug.

In one embodiment, the metallization layer further includes a second conductive via disposed in the ILD material layer below and electrically connected to the second metal line and directly adjacent to the second metal line the second sidewall of the dielectric plug.

In one embodiment, a portion of the layer of ILD material is directly under the second metal line, which is directly adjacent to the second sidewall of the dielectric plug.

In one embodiment, a method of fabricating a metallization layer for an interconnect structure of a semiconductor die, the method comprising: forming on a substrate Line trenches are formed in the upper portion of the interlayer dielectric (ILD) material layer above the layer metallization layer. The method also includes forming a via trench in the lower portion of the ILD material layer, the via trench exposing two metal lines of the underlying metallization layer. The method also includes forming a sacrificial material over the layer of ILD material and in the line trench and the via trench. The method also includes patterning the sacrificial material to form openings exposing a portion of the lower metallization layer between the two metal lines of the underlying metallization layer. The method also includes filling the opening of the sacrificial material with a dielectric material. The method also includes removing the sacrificial material to provide a dielectric plug on the portion of the lower metallization layer between the two metal lines of the bottom metallization layer. The method also includes filling the line trench and the via trench with a conductive material.

In one embodiment, filling the line trench and the via trench with the conductive material includes forming a first metal line in the line trench and forming a first conductive via in the via trench, the first A metal line and the first conductive via are directly adjacent to the first sidewall of the dielectric plug.

In one embodiment, filling the line trench and the via trench with the conductive material includes forming a second metal line in the line trench and forming a second conductive via in the via trench, the first The two metal lines and the second conductive via are directly adjacent to the second sidewall of the dielectric plug relative to the first sidewall.

In one embodiment, filling the opening of the sacrificial material with the dielectric material includes using a deposition process selected from the group consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD).

In one embodiment, the sacrificial is filled with the dielectric material The opening of material includes a seam formed in the dielectric material about the center of the dielectric plug.

In one embodiment, wherein filling the opening of the sacrificial material with the dielectric material includes filling with a first dielectric material composition.

In one embodiment, wherein the ILD material layer comprises a second dielectric material composition different from the first dielectric material composition.

In one embodiment, the ILD material layer includes the first dielectric material composition.

In one embodiment, patterning the sacrificial material includes forming a patterned hardmask on the sacrificial material, and transferring the pattern of the patterned hardmask to the sacrificial material by an etching process.

In one embodiment, removing the sacrificial material includes planarizing the sacrificial material and the dielectric material, followed by selectively etching away the remainder of the sacrificial material.

In one embodiment, a method for fabricating a metallization layer of an interconnect structure of a semiconductor die includes forming a line trench in an upper portion of a layer of interlayer dielectric (ILD) material formed over an underlying metallization layer . The method also includes forming a sacrificial material over the layer of ILD material and in the line trench. The method also includes patterning the sacrificial material to form openings exposing a portion of the lower portion of the layer of ILD material. The method also includes filling the opening of the sacrificial material with a dielectric material. The method also includes removing the sacrificial material to provide a dielectric plug on the portion of the lower portion of the ILD material layer. The method also includes filling the line trench with a conductive material.

In one embodiment, the trench is filled with the conductive material The trench includes forming a first metal line in the line trench, the first metal line directly adjacent to the first sidewall of the dielectric plug, and forming a second metal line in the line trench, the second metal line The line is directly adjacent to the second sidewall of the dielectric plug relative to the first sidewall.

In one embodiment, filling the opening of the sacrificial material with the dielectric material includes using a deposition process selected from the group consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD).

In one embodiment, filling the opening of the sacrificial material with the dielectric material includes forming a seam in the dielectric material about the center of the dielectric plug.

In one embodiment, filling the opening of the sacrificial material with the dielectric material includes filling with a first dielectric material composition, and the ILD material layer includes a second dielectric material having a different composition than the first dielectric material Element.

In one embodiment, filling the opening of the sacrificial material with the dielectric material includes filling with a first dielectric material composition, and the ILD material layer includes the first dielectric material composition.

200: Bottom metallization layer

202: Metal Wire

204: Dielectric Layer

206: Interlayer Dielectric (ILD) Materials

208: Line Groove

210: Lower

Claims (15)

An integrated circuit structure comprising: Lower metallization layer, including: a first wire in the first dielectric layer; a second wire in the first dielectric layer, the second wire being spaced apart from the first wire; and a third wire in the first dielectric layer, the third wire being spaced apart from the second wire; and an upper metallization layer located above the lower metallization layer, the upper metallization layer comprising: a second dielectric layer on the second wire of the lower metallization layer and the third wire; a fourth wire on the second dielectric layer, the fourth wire is on the third wire; a fifth wire on the second dielectric layer, the fifth wire is on the first wire; Coupling the fifth wire to a conductive via of the first wire, the conductive via is directly between the fifth wire and the first wire, and the conductive via is laterally adjacent to the second dielectric layer and contact; and a dielectric plug on the second dielectric layer, the dielectric plug is between and in contact with the fourth wire and the fifth wire, and the dielectric plug has a different ingredients of ingredients. The integrated circuit structure of claim 1, wherein the dielectric plug has a first height and the fourth conductor has a second height, and Wherein the first height and the second height are substantially the same. The integrated circuit structure of claim 1, wherein the dielectric plug has a bottom surface and the conductive via has a bottom surface, and wherein the bottom surface of the dielectric plug is tied to the bottom surface of the conductive via above. An integrated circuit structure comprising: Lower metallization layer, including: a first wire in the first dielectric layer; a second wire in the first dielectric layer, the second wire being spaced apart from the first wire; and a third wire in the first dielectric layer, the third wire being spaced apart from the second wire; and an upper metallization layer located above the lower metallization layer, the upper metallization layer comprising: a second dielectric layer on the second wire of the lower metallization layer and the third wire; a fourth wire on the second dielectric layer, the fourth wire is on a portion of the third wire; a fifth wire on the second dielectric layer, the fifth wire is on a portion of the first wire; Coupling the fifth wire to a conductive via of the first wire, the conductive via is directly between the fifth wire and the first wire, and the conductive via is laterally adjacent to the second dielectric layer and contact; and a dielectric plug on the second dielectric layer, the dielectric plug is on the second dielectric layer Between and in contact with the fourth wire and the fifth wire, and the dielectric plug has a composition different from that of the second dielectric layer. The integrated circuit structure of claim 4, wherein the dielectric plug has a first height and the fourth wire has a second height, and wherein the first height and the second height are substantially the same. The integrated circuit structure of claim 4, wherein the dielectric plug has a bottom surface and the conductive via has a bottom surface, and wherein the bottom surface of the dielectric plug is tied to the bottom surface of the conductive via above. A computing device comprising: board; and A component coupled to the board, the component including an integrated circuit structure including: Lower metallization layer, including: a first wire in the first dielectric layer; a second wire in the first dielectric layer, the second wire being spaced apart from the first wire in the first dielectric layer; and a third wire in the first dielectric layer, the third wire being spaced apart from the second wire in the first dielectric layer; and an upper metallization layer located above the lower metallization layer, the upper metallization layer comprising: a second dielectric layer on the second wire of the lower metallization layer and the third wire; the fourth wire on the second dielectric layer, the fourth wire is in the on three wires; a fifth wire on the second dielectric layer, the fifth wire is on the first wire; Coupling the fifth wire to a conductive via of the first wire, the conductive via is directly between the fifth wire and the first wire, and the conductive via is laterally adjacent to the second dielectric layer and contact; and a dielectric plug on the second dielectric layer, the dielectric plug is between and in contact with the fourth wire and the fifth wire, and the dielectric plug has a different ingredients of ingredients. The computing device of claim 7, further comprising: memory coupled to the board. The computing device of claim 7, further comprising: A communication chip coupled to the board. The computing device of claim 7, further comprising: A camera coupled to the board. The computing device of claim 7, further comprising: A battery coupled to the board. The computing device of claim 7, further comprising: An antenna coupled to the board. The computing device of claim 7, wherein the component is a packaged integrated circuit die. The computing device of claim 7, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor. The computing device of claim 7, wherein the computing device is selected from the group consisting of a mobile phone, a laptop computer, a desktop computer, a server, and a set-top box.

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