US6448115B1 - Semiconductor device having quasi-SOI structure and manufacturing method thereof - Google Patents
Semiconductor device having quasi-SOI structure and manufacturing method thereof Download PDFInfo
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- US6448115B1 US6448115B1 US09/686,883 US68688300A US6448115B1 US 6448115 B1 US6448115 B1 US 6448115B1 US 68688300 A US68688300 A US 68688300A US 6448115 B1 US6448115 B1 US 6448115B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 204
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 204
- 239000010703 silicon Substances 0.000 claims abstract description 204
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 229910021426 porous silicon Inorganic materials 0.000 claims abstract description 69
- 238000009413 insulation Methods 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 15
- 239000012212 insulator Substances 0.000 abstract description 4
- 230000008859 change Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007743 anodising Methods 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/96—Porous semiconductor
Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor device having a quasi silicon-on-insulator (SOI) structure, and a manufacturing method thereof.
- SOI silicon-on-insulator
- silicon substrates are widely used in semiconductor devices.
- silicon substrates have several drawbacks.
- it is difficult to form a thin source/drain region and to reduce a parasitic junction capacitance that is produced in the junction area between the silicon substrate and the source/drain region. This can detrimentally effect the operation speed of the device.
- An SOI semiconductor device having a silicon-on-insulator (SOI) structure has been proposed.
- An SOI semiconductor device is constructed such that a silicon layer on which a unit device is formed is completely electrically insulated from a lower silicon substrate by an insulation layer. This reduces the capacitive coupling occurring between unit devices formed in an integrated circuit (IC) chip.
- IC integrated circuit
- An SOI semiconductor device has a large threshold slope and exhibits little decrease in the device characteristic even at a low voltage of less than 2 V.
- a thin SOI device exhibits excellent characteristics, such as a decrease in the short channel effect, an increase in the sub-threshold swing, high mobility, and a decrease in the hot carrier effect, compared to existing semiconductor devices.
- an active region is isolated from a silicon substrate so that body contact is not formed, resulting in floating body effects. Floating body effects occur when excess carriers are accumulated in a floated body during device operation, and parasitic bipolar-induced breakdown or latch-up is accordingly induced.
- a semiconductor device having a quasi-SOI structure, in which a body contact is formed for extracting excess carriers by partially forming contact hole under the active region.
- FIG. 1 shows a conventional semiconductor device having a quasi-SOI structure.
- an oxide layer 10 is formed under a source region 3 and a drain region 5 that are to be insulated from a lower silicon substrate 1 .
- the body region under a channel region is opened so that it is not insulated from the lower silicon substrate 1 .
- a body contact can be formed in the same manner as in a bulk device.
- reference numerals 2 , 7 and 9 denote a field oxide layer, a gate oxide layer, and a gate electrode, respectively.
- the oxide layer 10 is formed by implanting oxygen ions using the gate electrode 9 as a mask and then performing high-temperature annealing on the resultant structure.
- the gate oxide layer 7 or the ion implanted state of the channel region may be affected by ion implantation or annealing, the conventional SOI semiconductor device has drawbacks in practical fabrication.
- a semiconductor device having a silicon-on-insulator (SOI) structure includes a lower silicon substrate; an upper silicon pattern formed over the lower silicon substrate; a reverse T-type hole formed between the upper silicon pattern and the lower silicon substrate; an isolating insulation layer formed in the reverse T-type hole for partially electrically insulating the upper silicon pattern from the lower silicon substrate; a gate insulation layer and a gate electrode formed over the upper silicon pattern; a source region formed in the upper silicon pattern adjacent to the gate electrode; a drain region formed in the upper silicon pattern adjacent to the gate electrode; a channel region formed in the upper silicon pattern between the source and drain regions; and a silicon layer formed under the channel region for electrically connecting the lower silicon substrate and the upper silicon pattern.
- SOI silicon-on-insulator
- the silicon layer is preferably a porous silicon layer.
- An air layer may be formed in the isolating insulation layer below the upper silicon pattern.
- the upper silicon pattern is preferably a single-crystal silicon layer.
- a method for manufacturing a semiconductor device having an SOI structure is provided.
- a porous silicon pattern is formed over a lower silicon substrate.
- An upper silicon pattern is then formed over the a porous silicon pattern.
- a hole is then formed in the upper silicon pattern and the porous silicon pattern to expose the lower silicon substrate.
- a reverse T-type hole and an undercut porous silicon pattern are then formed under the upper silicon pattern by partially etching the porous silicon pattern, the resulting undercut porous silicon pattern partially electrically contacting the lower silicon substrate and the upper silicon pattern.
- the lower silicon substrate is partially electrically isolated from the upper silicon pattern by forming an isolating insulation layer in the reverse T-type hole.
- a gate insulation layer and a gate electrode are formed over the upper silicon pattern, and source and drain regions are formed in the upper silicon pattern.
- a mask pattern may also be formed over the upper silicon layer.
- the hole is formed in the upper silicon pattern and the porous silicon pattern by sequentially etching the upper silicon layer and the porous silicon layer using the mask pattern as a mask.
- an insulation layer may be formed over the upper silicon pattern and in the reverse T-type hole. This insulation layer is then subsequently planarized by etching, at which time the mask pattern is simultaneously removed.
- an impurity-containing silicon layer may be formed over the lower silicon substrate, and silicon can then be extracted from the impurity-containing silicon layer.
- a thermal oxide layer may be formed over an entire exposed surface in the reverse T-type hole.
- an air layer may be formed in the isolating insulation layer under the upper silicon pattern adjacent to the undercut porous silicon layer.
- the undercut porous silicon pattern may be obtained by isotropically etching the porous silicon pattern.
- a porous silicon layer is formed in a lower silicon substrate to define a first region of the lower silicon substrate.
- An upper silicon layer is then formed over the porous silicon layer and the lower silicon substrate.
- a hole is then formed in the upper silicon layer and the porous silicon layer to expose a second region of the lower silicon substrate and to define an upper silicon pattern and a porous silicon pattern.
- a reverse T-type hole is formed by removing the porous silicon pattern, and at the same time partially electrically contacting the lower silicon substrate and the upper silicon pattern through the first region of the lower silicon substrate.
- the lower silicon substrate is partially electrically isolated from the upper silicon pattern by forming an isolating insulation layer in the reverse T-type hole.
- a gate insulation layer and a gate electrode are formed over the upper silicon pattern, and source and drain regions are formed in the upper silicon pattern.
- a first mask pattern may be formed over the lower silicon substrate.
- An impurity region is then selectively formed in an exposed portion of the lower silicon substrate by implanting impurities in the exposed portion of the lower silicon substrate using the first mask pattern as a mask.
- the porous silicon layer is then formed by extracting silicon from the impurity region, and the first mask pattern is removed.
- the method may also include forming a thermal oxide layer over an entire exposed surface in the reverse T-type hole.
- a second mask pattern may be formed over the upper silicon layer and the porous silicon layer lower silicon substrate. The upper silicon layer and the porous silicon layer may then be sequentially etched using the second mask pattern as a mask.
- an insulation layer may be formed over the upper silicon payer and in the reverse T-type hole.
- the insulation layer may then be planarized by etching, at which time the second mask pattern is simultaneously removed.
- an air layer may be formed under the upper silicon pattern.
- a body contact that is the same as that of a general semiconductor device is allowed without requiring a special change in the design of the semiconductor device.
- FIG. 1 shows a conventional semiconductor device having a quasi-SOI structure
- FIG. 2 is a cross-sectional view illustrating a semiconductor device having a quasi-SOI structure according to a first preferred embodiment of the present invention
- FIG. 3 is a cross-sectional view illustrating a semiconductor device having a quasi-SOI structure according to a second preferred embodiment of the present invention
- FIGS. 4 through 9 are cross-sectional views respectively illustrating the manufacturing process sequence of the semiconductor device of FIG. 2;
- FIGS. 10 through 17 are cross-sectional views respectively illustrating the manufacturing process sequence of the semiconductor device of FIG. 3 .
- FIG. 2 A semiconductor device having a quasi-SOI structure according to a first preferably embodiment of the present invention is shown in FIG. 2 .
- portions of an upper silicon layer 25 a are isolated from each other by an isolating insulation layer 33 a .
- the upper silicon layer 25 a includes a source region 36 , a drain region 37 , and a channel region 40 disposed between the source region 36 and the drain region 37 .
- a gate insulation layer 38 and a gate electrode 39 are formed over the upper silicon layer 25 a and the channel region 40
- the upper silicon layer 25 a is partially isolated from a silicon substrate 21 (lower silicon layer) by the isolating insulation layer 33 a .
- a porous silicon layer 23 b is formed under the channel region 40 .
- the porous silicon layer 23 b becomes a passage for partial contact between the lower silicon layer 21 (the silicon substrate) and the upper silicon layer 25 a , thereby allowing a body contact which is the same as the conventional body contact.
- the semiconductor having a quasi-SOI structure includes a silicon-on-air (SOA) structure produced by forming an air layer 35 in the isolating insulation layer 33 a disposed under the upper silicon layer 25 a . Since the air layer 35 has a dielectric constant lower than that of the oxide layer used as the insulation layer in a conventional SOI semiconductor device, more effective device characteristics can be obtained.
- SOA silicon-on-air
- FIG. 3 is a cross-sectional view illustrating a semiconductor device having a quasi-SOI structure according to a second preferred embodiment of the present invention.
- portions of an upper silicon layer 49 a are isolated from each other by an isolating insulation layer 57 a .
- the upper silicon layer 49 a includes a source region 61 , a drain region 63 , and a channel region 60 disposed between the source region 61 and the drain region 63 .
- a gate insulation layer 65 and a gate electrode 67 are formed over the upper silicon layer 49 a and the channel region 60 .
- the upper silicon layer 49 a is partially isolated from a silicon substrate 41 (lower silicon layer) by the isolating insulation layer 57 a .
- a silicon layer 41 a is formed under the channel region 60 and connects the upper silicon layer 49 a in the channel region 60 to the lower silicon layer 41 .
- the silicon layer 41 a thus becomes a passage for partial contact between the lower silicon layer 41 and the upper silicon layer 49 a , thereby allowing a body contact similar to a conventional body contact.
- the semiconductor having a quasi-SOI structure according to the present invention also includes a silicon-on-air (SOA) structure produced by forming an air layer 59 in the isolating insulation layer 57 a disposed under the upper silicon layer 49 a . Since the air layer 59 has a dielectric constant lower than that of the oxide layer used as the insulation layer in a conventional SOI semiconductor device, more effective device characteristics can be obtained.
- SOA silicon-on-air
- FIGS. 4 through 9 are cross-sectional views respectively illustrating the manufacturing process sequence of the semiconductor device of FIG. 2, respectively.
- a porous silicon layer 23 is initially formed over a silicon substrate 21 (lower silicon layer) by an anodizing method.
- an impurity-containing silicon layer (not shown) is formed over the lower silicon substrate 21 and then silicon is extracted from the impurity-containing silicon layer, thereby forming the porous silicon layer 23 .
- a single-crystal upper silicon layer 25 is formed over the porous silicon layer 23 , preferably using an epitaxy method.
- a mask pattern 27 is then formed over the upper silicon layer 25 .
- the mask pattern 27 is preferably formed using a photolithography method after forming a nitride layer (not shown) over the upper silicon layer 25 .
- the upper silicon layer 25 and the porous silicon layer 23 are then etched using the mask pattern 27 as an etching mask, thereby forming an upper silicon layer pattern 25 a and a porous silicon pattern 23 a .
- a hole 29 is formed to open the surface of the lower silicon substrate 21 and to expose side walls of the porous silicon pattern 23 a.
- the porous silicon pattern 23 a is then isotropically etched using diluted HF solution having a high etching selectivity with respect to silicon.
- the etching degree is adjusted such that a portion the porous silicon pattern 23 a is etched under the upper silicon pattern 25 a , thereby forming an undercut porous silicon pattern 23 b and a reverse T-type hole 30 for opening the surface of the lower silicon substrate 21 .
- the exposed surface of the reverse T-type hole 30 is then thermally oxidized, thereby forming a thermal oxide layer 31 .
- the thermal oxide layer 31 is formed on the entire surface of the undercut porous silicon pattern 23 b , the upper silicon pattern 25 a , and lower silicon substrate 21 .
- an insulation layer 33 e.g., an oxide layer, is formed over the entire surface of the lower silicon substrate 21 and the thermal oxide layer 31 , partially filling the reverse T-type hole 30 .
- the reverse T-type hole 30 is not completely filled, but rather, an air layer 35 is formed below the upper silicon pattern 25 a .
- the insulation layer 33 is formed by a chemical vapor deposition (CVD) method.
- the insulation layer 33 is then planarized, preferably by a chemical mechanical polishing (CMP) method, thereby forming an isolating insulation layer 33 a .
- CMP chemical mechanical polishing
- the mask pattern 27 is also removed.
- the lower silicon substrate 21 is partially isolated from the upper silicon pattern 25 a by the isolating insulation layer 33 a , and the porous silicon layer 23 b allows the upper silicon pattern 25 a and the lower silicon substrate 21 to be partially contacted with each other, thereby forming a quasi-SOI structure.
- the gate insulation layer 38 and the gate electrode 39 are formed over the upper silicon pattern 25 a , and then source and drain regions 36 and 37 are formed in the upper silicon pattern 25 a , thereby completing the semiconductor device having a quasi-SOI structure.
- the semiconductor device of this embodiment also includes the SOA structure. And because the air layer 35 has a dielectric constant lower than that of an oxide layer used as the insulation layer in the conventional SOI semiconductor device, the resulting device has more effective device characteristics.
- FIGS. 10 through 17 are cross-sectional views respectively illustrating the manufacturing process sequence of the semiconductor device of FIG. 3 .
- a first mask pattern 43 is initially formed over a P-type silicon substrate (i.e., a lower silicon substrate) 41 . Subsequently, P-type impurities are implanted into the entire surface of the lower silicon substrate 41 using the first mask pattern 43 as a mask, thereby forming a P + -impurity region 45 .
- a P + region is formed in a P-type silicon substrate.
- an N + region may be formed in an N-type silicon substrate.
- the first mask pattern 43 is then removed. Subsequently, as described in the first preferred embodiment, silicon is extracted from the impurity region 45 , thereby selectively forming a porous silicon layer 47 on a the lower silicon substrate 41 .
- the porous silicon layer 47 is formed on a portion exclusive of a first region 41 a of the lower silicon substrate 41 .
- a single-crystal upper silicon layer 49 is then formed over the lower silicon substrate 41 and the porous silicon layer 47 , preferably using an epitaxy method.
- a second mask pattern 51 is formed over the upper silicon layer 49 .
- the second mask pattern 51 is preferably formed using a photolithography method after forming a nitride layer over the upper silicon layer 49 .
- the upper silicon layer 49 and the porous silicon layer 47 are then etched using the second mask pattern 51 as an etching mask, thereby forming an upper silicon layer pattern 49 a and a porous silicon pattern 47 a .
- a hole 53 is then formed to expose a second region 41 b of the lower silicon substrate 41 disposed under the porous silicon layer 47 and to expose the side walls of the porous silicon pattern 47 a.
- the porous silicon pattern 47 a is then isotropically etched, preferably using a dilute HF solution having a high etching selectivity with respect to silicon, thereby forming a reverse T-type hole 30 between the upper silicon patterns 49 a.
- the surface of the reverse T-type hole 52 is then thermally oxidized, thereby forming a thermal oxide layer 55 .
- a thermal oxide layer 55 is formed on the surface of the lower silicon substrate 41 , on sidewalls of the first region of the lower silicon substrate 41 , and on the lateral surface and bottom of the upper silicon pattern 49 .
- an insulation layer 57 e.g., an oxide layer, is then formed over the entire surface of the lower silicon substrate 41 and the thermal oxide layer 55 , and in the reverse T-type hole 52 , preferably by a CVD method.
- the reverse T-type hole 52 is not completely filled and an air layer 59 is formed below the upper silicon pattern 49 a.
- the insulation layer 57 is then planarized, preferably by a CMP method, thereby forming an isolating insulation layer 57 a .
- the second mask pattern 51 is also removed.
- the lower silicon substrate 41 is partially insulated from the upper silicon pattern 49 a by the isolating insulation layer 57 a .
- a silicon layer 41 a allows the upper silicon pattern 49 a and the lower silicon substrate 41 to be partially contacted with each other, thereby forming a quasi-SOI structure.
- the gate insulation layer 65 and the gate electrode 67 are formed in the upper silicon pattern 49 a of the lower silicon substrate 41 , and then source and drain regions 61 and 63 are formed in the upper silicon pattern 49 a , thereby completing the semiconductor device having the quasi-SOI structure.
- the semiconductor device of this embodiment also includes an SOA structure. And because the air layer 59 has a dielectric constant lower than that of an oxide layer used as the insulation layer in the conventional SOI semiconductor device, more effective device characteristics can be obtained.
- the semiconductor device having a quasi-SOI structure has a porous silicon layer or a silicon layer under an upper silicon substrate. Accordingly, the porous silicon layer or the silicon layer becomes a passage for partial contact with a lower silicon substrate, thereby allowing a body contact which is the same as that of a general semiconductor device, without a special change in the design of the semiconductor device.
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US10/201,781 US6657258B2 (en) | 1999-10-12 | 2002-07-25 | Semiconductor device having quasi-SOI structure |
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KR1019990043988A KR100304713B1 (en) | 1999-10-12 | 1999-10-12 | Semiconductor device having quasi-SOI structure and manufacturing method thereof |
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US10/201,781 Expired - Fee Related US6657258B2 (en) | 1999-10-12 | 2002-07-25 | Semiconductor device having quasi-SOI structure |
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Also Published As
Publication number | Publication date |
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JP2001148479A (en) | 2001-05-29 |
KR20010036815A (en) | 2001-05-07 |
KR100304713B1 (en) | 2001-11-02 |
US6657258B2 (en) | 2003-12-02 |
JP3678641B2 (en) | 2005-08-03 |
US20020182787A1 (en) | 2002-12-05 |
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