US6198269B1 - Converter with continuous currents flowing through secondary windings - Google Patents

Converter with continuous currents flowing through secondary windings Download PDF

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Publication number
US6198269B1
US6198269B1 US09/319,770 US31977099A US6198269B1 US 6198269 B1 US6198269 B1 US 6198269B1 US 31977099 A US31977099 A US 31977099A US 6198269 B1 US6198269 B1 US 6198269B1
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chain
transistor
transistors
collector
transformer
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John Ronald Beeley
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DRS Technologies UK Ltd
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DRS Hadland Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/335—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductor devices with more than two electrodes and exhibiting avalanche effect
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage

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  • the present invention is concerned with fast voltage ramp generators and particularly voltage ramps of nano-second and sub-nano-second duration.
  • the sweep plates of a known prior art streak camera have been driven from a chain of avalanche transistors typically connected in series.
  • One transistor of the chain would be triggered into avalanche switching by applying a positive going voltage pulse to the base of the transistor.
  • the remaining transistors of the chain would then slave trigger from the resultant step voltage transient across them.
  • FIG. 1 illustrates a prior art switching chain used for producing a high speed ramp to drive the sweep plates of a streak camera.
  • the chain comprises a chain TR 1 to TRn of small signal high gain—bandwidth product NPN avalanche transistors.
  • the triggering input 9 to the circuit is coupled by means of a transformer T 1 to the base-emitter junction of the transistor TR 1 at the bottom of the chain.
  • the bases and emitters of the other transistors TR 2 to TRn are connected together.
  • the whole chain can be avalanche switched by the application of a forward biasing current pulse to the bottom most transistor TR 1 of the chain via a triggering transformer T 1 .
  • a capacitance C 1 across the transistor TR 1 ensures this transistor is capacitively loaded. If an avalanche transistor is only resistively loaded, on triggering, the collector voltage of the transistor switches only from its collector-base breakdown voltage to a value near its collector-emitter breakdown voltage. These two voltages can be relatively close so that the effect of switching is a small change of voltage. However, if the transistor is capacitively loaded, sufficient current is available from the capacitor on avalanche switching of the transistor to cause the transistor to saturate so that the collector voltage of the transistor drops from the collector-base breakdown voltage, typically 130 volts, to the collector-emitter saturation voltage, typically about 1 volt.
  • the presence of capacitor C 1 causes the collector of this transistor to change rapidly between the above two voltages, producing a negative voltage transient of typically 130 volts applied to the emitter of the next transistor TR 2 of the chain, and which then propagates up the chain to the emitter of the uppermost transistor TRn.
  • the negative voltage transient initiates the avalanche multiplication process in the base region of each transistor as the emitter of the transistor receives the negative transient. If all the transistors are well matched, the triggering times for each transistor are very similar, probably to within a few pico-seconds.
  • the avalanche action that has been initiated in each of the devices TR 2 to TR(n ⁇ 1) is initially primarily resistively loaded so that these transistors initially switch only between the collector-base breakdown voltage and the collector-emitter breakdown voltage for each transistor.
  • the transistors near the top of the chain may see sufficient charge stored in the stray capacitance to provide sufficient current to saturate the transistor as it performs avalanche switching.
  • TR 2 and the transistors near the bottom of the chain will probably switch with relatively small changes in collector voltage, the transistors at the top of the chain will be more likely to switch to the saturation voltage levels, i.e. with large voltage excursions.
  • the effect may be the production of small, random perturbations in the voltage gradient at the collector of the uppermost transistor TRn.
  • ramp generators of the kind described above with reference to FIG. 1 are used to drive the deflection plates of an image converter tube used for streak recording
  • shortcomings have been observed such as shot-to-shot jitter, out of focus and/or distorted images at higher streak writing rates, and considerable loss of ramp linearity, particularly over the initial parts of the ramp which would otherwise be the fastest, most useful sections.
  • C 2 represents the overall capacitive circuit load for the ramp generator and resistor R 2 is a limiting resistor required to limit the switched current to a safe value to prevent damage to the switching transistors.
  • the illustrated additional capacitor C 3 which is provided to assist the start up of avalanche conduction may be dispensed with since sufficient capacitance may be provided by stray capacitances to ground.
  • transistor TR 2 has at this time performed only a small collector voltage type switching, i.e. to the collector-emitter breakdown voltage, the instantaneous power dissipation in the device would destroy the device unless the current transient is substantially limited by providing a sufficiently high value for resistance R 2 .
  • a fast voltage ramp generator comprises a chain of transistors in avalanche switching mode connected collector to emitter in series, each said transistor being connected to have a low resistance path between its base and emitter, a voltage source connected across said chain between the collector of a transistor at one end of the chain and the emitter of a transistor at the other end of the chain, and arranged to bias said transistors to avalanche switching mode, and a transformer having a secondary connected to apply a switching pulse across the base-emitter junction of one of the transistors of the chain to initiate avalanche switching of the transistors of the chain to generate a fast ramp voltage across the load, characterised in that a respective transformer secondary is connected to apply a switching pulse across the base-emitter junction of each transistor of the chain.
  • said voltage source has a value to bias each transistor of said chain into collector-base breakdown and includes a series resistance to limit the breakdown current through the chain of transistors to a quiescent value below the current at which avalanche switching occurs.
  • each of said transformer secondaries have sufficient capacitance to load the collector of the next transistor of the chain to allow that transistor to saturate when switched.
  • the transistors of the chain are substantially simultaneously switched, they are all switched to the low voltage state, i.e. to the state in which the collector-emitter voltage is substantially the saturation voltage.
  • the respective transformer secondaries are the secondaries of discrete transformers having respective primaries which are connected in series.
  • each of said transformers comprises a ferrite bead having a plated through hole constituting the secondary of the transformer and an insulated conductor threaded through the hole constituting the primary. Then, the ferrite beads of the transformer may be threaded on a single insulated conductor forming said series connected primaries.
  • the transformers and the associated avalanche transistors are preferably arranged physically in a circle. This provides a compact arrangement whilst maximising the diametric separation of devices which are separated along the length of the chain.
  • said voltage source connected across said chain is a balanced source
  • the generator includes a switching pulse driver connected to apply a balanced switching pulse voltage across said series connected transformer primaries, wherein the transformers having primaries directly connected to said driver, at opposite ends of said series connected primaries, are associated with two central transistors at or adjacent the centre of said chain, the transformers having primaries connected to said end primaries are associated with the next transistors outwards from said central transistors, and so on, so that two transformers having primaries at or adjacent to the centre of said series connected primaries are associated with the end transistors of the chain.
  • leads connecting the switching pulse voltage to the opposite ends of the series connected primaries can be located near points where the quiescent DC voltage (before switching) along the chain of transistors is close to ground potential and where transient voltages induced from the chain of transistors back towards the switching pulse driver tend to cancel each other out. Also, it takes a finite time for the switching pulse voltage transients applied to the series connected primaries to propagate inwards from opposite ends of the series connected primaries. As a result, the transistors in the central part of the chain will have received their switching pulse voltage signals before the transistors at the ends of the chain. This ensures that the load current transient that subsequently propagates inwards from the ends of the chain of transistors can pass regularly through transistor devices which are already in saturation conduction and then cancel each other halfway along the chain of transistors.
  • the generator includes a switching pulse driver connected to apply a switching pulse voltage across said series connected transformer primaries, wherein said driver comprises a driver avalanche transistor having its collector-emitter circuit capacitively coupled across said series connected transformer primaries, a triggering transformer having a secondary connected to provide a low resistance path between the base and emitter of said driver transformer, a drive voltage source connected across the collector and emitter of the driver transistor and having a value exceeding the collector-base breakdown voltage of said driver transistor, a resistance in series with said drive voltage source to limit the collector-base breakdown current through the driver transistor to a quiescent value below the current at which avalanche switching of the driver transistor occurs, and a triggering pulse source, the triggering transformer having a primary connected to receive a triggering pulse from said source to trigger the driver transistor into avalanche switching.
  • said driver comprises a driver avalanche transistor having its collector-emitter circuit capacitively coupled across said series connected transformer primaries, a triggering transformer having a secondary connected to provide a low resistance path between the base
  • the generator includes a printed circuit board (PCB) having printed contact pads for the terminals of said avalanche transistors of said chain, each said transistor being contained in an E-line package, said PCB having a well, milled part way through the thickness of the board, receiving each said E-line package with the terminals of the transistor extending parallel to the plane of the PCB so as to overlie the respective said printed contact pads.
  • PCB printed circuit board
  • the transistors can be mounted on the PCB with the terminal leads of the transistor cropped short and minimum distance between the point of soldered contact between each of the leads and the respective printed circuit pad.
  • a plurality of said E-line packages are located in a common said well.
  • the or each said well may be filled with encapsulation material around the respective E-line package contained therein.
  • FIG. 1 is a circuit diagram illustrating a prior art switching chain.
  • FIG. 2 is a circuit diagram illustrating an embodiment of the present invention
  • FIG. 3 is a plan view of the transistor chain and switching transformer arrangement as mounted on a printed circuit board;
  • FIGS. 4A and 4B are an end view and cross-sectional view respectively illustrating the form of transformer used in the embodiment illustrated in FIG. 3;
  • FIG. 5 is a cross-sectional view taken along the line X—X of FIG. 2 illustrating the mounting of the transistors of the chain.
  • a chain 10 of series connected avalanche transistors is shown.
  • the collector of the uppermost transistor, identified TR 1 is connected to a positive voltage source +V cc2 via a resistance 11
  • the emitter of the lowermost transistor, identified as TRn is connected via a resistance 12 to a negative voltage source ⁇ V ee2 .
  • the remaining transistors of the chain 10 are connected emitter to collector directly, as shown, except that the emitter of TR n/2 is connected to the collector of TR 1+n/2 via a resistance 14 .
  • each of the transistors of the chain 10 is connected to the emitter of the respective transistor by means of the secondary 13 of a respective transformer.
  • the transformer associated with the topmost transistor TR 1 is identified as transformer T 1 and the transformer for the lowermost transistor TRn is identified Tn.
  • the transformer secondaries 13 provide a low resistance path between the base and emitter of the respective transistor.
  • Each of the transformers has a primary 15 and all these transformer primaries are connected in series as illustrated. Thus, a current pulse can be driven substantially simultaneously through all the primaries 15 of the transformers T 1 to Tn.
  • the voltage sources +V cc2 and ⁇ V ee2 provide a balanced source of sufficient potential difference to exceed the sum of the collector-base breakdown voltages of all the transistors of the chain 10 .
  • all the transistors of the chain 10 are driven into the collector-base breakdown region.
  • the resistors 11 and 12 are chosen to limit the breakdown current flowing through the devices to less than that which would produce in any one transistor a voltage drop across the intrinsic base-emitter resistance of the device sufficient to switch the device into avalanche conduction.
  • the collector-emitter voltage across each transistor of the chain 10 remains substantially at the collector-base breakdown voltage.
  • a switching pulse driver indicated generally at 18 is arranged to produce a balanced switching voltage transient across the series connected primaries 15 of the transformers 14 via end terminals 19 and 20 .
  • the switching pulse driver 18 comprises an avalanche transistor TRin having a collector connected via a resistance 22 to a positive drive voltage source +V cc1 , and its emitter connected via a resistance 23 to a negative drive voltage source ⁇ V ee1 .
  • the values of the drive voltage sources +V cc1 and ⁇ V ee1 are selected to exceed the collector-base breakdown voltage of the transistor TRin.
  • the resistances 22 and 23 ensure the quiescent breakdown current through the transistor TRin is insufficient to bias the intrinsic base-emitter resistance of the transistor TRin to the forward bias voltage of the junction.
  • transistor TRin remains in the collector-base breakdown region so that the voltage between the emitter and collector of the transistor TRin corresponds to the collector-base breakdown voltage, typically 130 volts.
  • the collector of the transistor TRin is connected via a capacitance 24 to one end terminal 19 of the series connected primaries of the transformers T 1 to Tn, and the emitter of the transistor TRin is connected via a capacitance 25 to the other end terminal 20 .
  • the terminals 19 and 20 are each connected to ground by a respective resistance 37 and 38 to provide a balanced DC return for capacitances 24 and 25 .
  • a triggering transformer Tin has a secondary 27 connected to provide a low resistance path between the base and the emitter of the transistor TRin.
  • An input triggering signal is supplied from a source 28 to the primary 29 of the transformer Tin.
  • a triggering pulse applied from the source 28 to the primary 29 of the transformer Tin supplies sufficient voltage bias to the base emitter junction of the transistor TRin to cause avalanche switching of the transistor. Because the transistor TRin is capacitively loaded, by the capacitors 24 and 25 and the distributed capacitance of transformer Tin, sufficient current is available on switching of the transistor TRin to saturate the transistor so that the collector emitter voltage of the transistor drops quickly from the collector-base breakdown voltage to a very low value, typically 1 volt. This voltage transient is applied across the series connected primaries 15 of the transformers T 1 to Tn. All the transformers T 1 to Tn are connected in the same polarity so that the voltage transient produces correspondingly sufficient forward voltage at the base of each of the transistors of the chain 10 to initiate avalanche switching of these transistors.
  • the transformers T 1 to Tn have sufficient distributed capacity so as effectively to capacitively load the adjacent transistor of the chain 10 .
  • each of the transistors of the chain 10 switch directly to the saturation condition, i.e. with a relatively low voltage across the collector/emitter of the transistor.
  • the upper transistor TR 1 is clearly capacitively loaded by the load capacitance to which the ramp generator is to be connected.
  • the voltage between the rails 16 and 17 very quickly drops from the previous value, typically 1560 volts to a very low value, say 12 volts and this large fast voltage transient is used to provide the required fast ramp.
  • the primaries 15 of the transformers T 1 to Tn are connected in series so that the end terminals 19 and 20 of the series connected primaries are connected directly to the primaries of the transformers associated with the central pair of transistors of the chain 10 , that is the transistors identified TR (n/2) and TR (1+n/2) .
  • the end terminals 19 and 20 to the series connected primaries 15 of the transformers 14 can be kept physically well away from the portions of the circuit which may be at relatively high quiescent voltage.
  • FIG. 3 illustrates the physical layout of the chain 10 of transistors from FIG. 2 and their associated transformers T 1 to Tn.
  • FIG. 3 there are twelve transistors and associated transformers in the chain.
  • the topmost transistor in the chain is also identified as TR 1 , so that the transistor in FIG. 3 corresponding to the lowermost transistor in the chain 10 of FIG. 2 is that identified TR 12 in FIG. 3 .
  • the associated transformers are designated T 1 to T 12 in FIG. 3 .
  • the transistors TR 1 to TR 12 of the chain are physically arranged in a circular array with the associated transformers T 1 to T 12 arranged in a corresponding circular array inside the array of transistors.
  • Each of the transformers T 1 to T 12 is a transmission line transformer fabricated from a small ferrite bead with an electrically conductive through plated hole.
  • FIG. 4A illustrates one such ferrite bead from one end. The bead may have square cros-section as illustrated.
  • FIG. 4B illustrates an axial section through the bead along line Y—Y of FIG. 4 A.
  • the ferrite bead 30 has a through hole 31 .
  • a layer of conductive material 32 extends completely through the hole 31 on the inside of the bead and also covers the ends of the bead providing substantial contact areas 33 and 34 on the outer periphery of the bead at each end.
  • the plated through layer 32 between contact surfaces 33 and 34 constitutes the secondary of the transformer formed by the bead.
  • a primary of the transformer is provided by an insulated conductor 35 threaded through the bead.
  • the conductor 35 may be PTFE insulated.
  • each of transformers T 1 to T 12 is surface mounted on corresponding conductive pads provided on a printed circuit board supporting the circuit of the ramp generator. As can be seen in the drawing, printed circuit tracks extend between the collector of one transistor and the emitter of the next transistor.
  • One end of the transformer bead of transformer T 1 is mounted on a conductive pad connected to the base of transistor TR 1
  • the other end of the transformer bead T 1 is on a conductive pad connected to the collector of transistor TR 2 , and hence also to the emitter of transistor TR 1 .
  • Transformer beads T 2 to T 12 are similarly connected between the base and emitter of respective ones of transistors TR 2 to TR 12 .
  • the emitter of TR 6 is connected to the collector of TR 7 via a surface mounted resistor 46 , corresponding to the resistance 14 of FIG. 2 .
  • All the transformer beads T 1 to T 12 have a continuous insulated conductor 40 threaded through them and the conductor 40 thereby provides the series connected primaries of the transformers.
  • TR 1 corresponds to the uppermost transistor of the chain and has its collector connected via a conductive track on the printed circuit board to a terminal point +SW corresponding to line 16 in FIG. 2 .
  • the emitter of transistor TR 12 is connected similarly to a contact point ⁇ SW corresponding to the line 17 in FIG. 2 .
  • the continuous insulated conductor 40 has one end 41 connected to a contact point on the printed circuit board +TR and the other end 42 connected to a contact point ⁇ TR.
  • the contact points +TR and ⁇ TR correspond to end terminals 19 and 20 of FIG. 2 .
  • the first transformer from contact point +TR through which the insulated conductor 40 is threaded is T 6 , associated with transistor TR 6
  • the last transformer through which the conductor is threaded is T 7 , associated with TR 7 .
  • the transistors TR 1 to TR 12 illustrated in FIG. 3 are contained in E-line packages which have the three terminals of the transistor emerging from the package in a line.
  • FIG. 5 is a cross-sectional view through the printed circuit board of FIG. 3 taken along line X—X, and illustrates how each transistor is mounted on the board.
  • a well 54 is milled about halfway through the thickness of the printed circuit board to receive the transistor 51 lying on its side as illustrated in FIG. 5 .
  • the well 54 is arranged to be just deep enough so as to receive the transistor and allow the leads 52 of the transistor 51 to overlie the printed circuit connection pads 53 of the printed circuit board, without any substantial bending of the leads. In this way, connections may be made to the transistor leads at positions very close to the entry points of the leads to the body of the transistor 51 .
  • a single well 50 in the shape of a circular arc is provided to receive all of transistors TR 1 to TR 6 and a second well 54 is provided to receive the transistors TR 7 to TR 12 .
  • the remaining volume of the wells 50 and 54 can be filled with an encapsulating material 55 as illustrated in FIG. 5 .
  • the circuit of FIG. 2 may be regarded as a pair of identical circuits of opposed polarity.
  • switching results in a positive current pulse propagating down the transmission line formed by transistors TR 1 to TR n/2 .
  • transistors TR 1 to TR n/2 in the upper part of the circuit (transistors TR 1+n/2 to TRn) on switching a negative current pulse propagates up from TRn to TR 1+n/2 .
  • the upper and lower transmission lines appear to a propagating pulse to be grounded at the junction between the two halves of the circuit, i.e. between transistor TR n/2 and transistor TR 1+n/2 .
  • Resistance 14 (FIG. 2) is connected in series between TR n/2 and TR 1+n/2 in order to provide matching termination for the upper and lower transmission lines. If the characteristic impedance of the upper and lower lines, selected to match the source impedance for the respective current pulses entering the transmission lines, is Z 0 , then the value of resistance 14 should preferably be about 2Z 0 .
  • the transistors TR 1 to TRn exhibit, during the dynamics of avalanche switching, an effective negative capacitance.
  • This negative capacitance is caused by stored electric charges within the semiconductor junction regions as these regions change substantially in thickness during is avalanche switching. The effect is similar to a positive inductance within each transistor.
  • a small value trimming capacitance 21 is connected between the collector of each of transistors TR 1 to TRn and ground.
  • the capacitances 21 may be graded to provide the desired characteristic impedance with the capacitances 21 nearest the centre of the transistor chain (the ends of the respective upper and lower transmission lines) having the highest values, and the capacitances at the upper and lower transistors TR 1 and TRn having the lowest values.
  • each of the transformers T 1 to Tn have an effective capacitance linking their respective primaries and secondaries. These capacitances are illustrated in dotted outline in FIG. 2 as capacitors 26 .
  • the chain 10 of avalanche transistors is formed of a total of 12 transistors.
  • the applied voltage source +V cc2 is +780 volts
  • the voltage source ⁇ V ee2 is ⁇ 780 volts.
  • the voltage across the collector emitter terminals of each transistor in the chain, before switching is 130 volts.
  • the emitter of transistor TR 1 sees a negative going voltage edge from 650 to zero volts, i.e. an edge of ⁇ 650 volts which may be transmitted through the capacitance 26 from the secondary 13 to the primary 15 of the associated transformer T 1 .
  • a similar excursion of the opposite polarity (+650 volts) is seen by the emitter of transistor TR 11 , which may in turn be transmitted via the capacitance 26 to the primary of the transformer T 11 . Since all the primaries of the transformers are connected together in series, the voltage pulse transmitted by transformer T 1 should cancel out the voltage pulse transmitted by transformer T 11 .
  • transistor TR 2 its emitter will see a negative going voltage change on switching of 520 volts and the effect of this transmitted via the capacitance of transformer T 2 should be cancelled by the opposite polarity excursion of the emitter of transistor 10 .
  • the emitter of TR 6 is effectively at ground potential both before and after switching and so experiences no substantial excursion.
  • an additional capacitance may be connected between the series connected primaries of the transformers and the line 16 which is connected to the collector of the uppermost transistor TR 1 . Then on switching of the circuit, a corresponding negative going voltage change of ⁇ 780 volts is communicated through this additional capacitance to the series connected primaries. So long as the additional capacitance matches the capacitance 26 of the transformers T 1 to Tn (which should all be themselves closely matched), the additional capacitance will cancel out the effect of the capacitance of transformer Tn.
  • a very convenient way of providing the required additional capacitance is to connect the primary of an additional balancing transformer Tbal in series with the primaries 15 of transformers T 1 to Tn.
  • the secondary 13 of the additional transformer Tbal may then have one terminal connected to the line 16 .
  • the other terminal of the secondary may be left floating. If the transformer Tbal is matched to the transformers T 1 to Tn, then this arrangement will provide a corresponding capacitance 26 between the line 16 and the series connected primaries of the transformers, as required effectively to cancel out the capacitance 26 of the transformer Tn.
  • the additional transformer may comprise a ferrite bead identical to those of transformers T 1 to T 12 and also threaded on the insulating conductor 40 which forms the series connected primaries of the various transformers. As shown in FIG. 3, one end only of the transformer bead may then be surface mounted to the conductor pad on the printed circuit connected to the collector of transistor TR 1 .
  • the primary 29 and secondary 27 of the triggering transformer Tin may also be regarded as being interconnected by a capacitance 36 .
  • the emitter of the driver transistor TRin is connected by the capacitance 36 to ground.
  • This can produce an imbalance in the drive voltages generated by the driver transistor TRin and communicated via the capacitances 24 and 25 to the ends of the series connected primaries.
  • This imbalance in the drive signals produced by the driver transistor TRin may be counteracted by providing a capacitance of the same value as capacitance 36 , between the collector of driver transistor TRin and ground.
  • a convenient method of providing this capacitance is to form triggering transformer Tin with an additional secondary winding 37 .
  • the secondary windings 27 and 37 of transformer Tin are arranged to have the same capacitance with the primary winding 29 of the transformer. Additional secondary winding 37 then has one terminal connected to the collector of the driving transformer TRin. The other terminal may be left unconnected. In this way, a balancing capacitance 38 is provided having the same value as capacitance 36 .
  • FIGS. 3 and 5 illustrate a convenient method of providing the trimming capacitances 21 connected to the collectors of the avalanche transistors in the chain.
  • the metallisation of the contact pad for the collector of each of transistors TR 1 to TR 12 may be extended into the respective well 50 or 54 to form a plate region as illustrated at 43 , 44 and 45 for example under transistors TR 10 , TR 11 and TR 12 in FIG. 3 .
  • a ground plane metallisation 46 is formed on the underneath face of the PCB, at least under the wells 50 and 54 , so that the plate regions 43 to 45 form, with the ground plane 46 , respective capacitors.
  • the size of the plate region 43 , 44 and 45 may be selected to provide the desired value of capacitance according to the position of the respective transistor in the chain. If capacitance values are required which are larger than those that can be made with the above method, the metallisation from the collector pad of the respective transistor may be continued through the well to the outer side of the well to provide surface mount pads for discrete surface mounted trimming capacitances, such as illustrated at 47 and 48 in FIG. 3 .
  • the capacitance values required to achieve the desired matching of the characteristic impedance are graded, with the lowest value capacitance being connected to the transistors TR 1 and TR 12 at the ends of the chain, and the highest value capacitances connected to the transistors TR 6 and TR 7 at the centre of the chain. It should be appreciated that the capacitances for the transistors TR 1 to TR 6 should therefore be a mirror image of those shown for transistors TR 12 to TR 7 .
  • transistors in avalanche switching mode are sometimes referred to as avalanche transistors, but it will be understood that any transistor (normally NPN junction types) which can operate in avalanche switching mode when suitably biased is to be covered by this term.
  • avalanche switching is described in which the transistor is biased to collector-base breakdown with insufficient breakdown current to initiate avalanche switching. This is a preferred form which is desirably fast. However the transistors for this form of operation must be selected to be stable in collector-base breakdown condition without spontaneous avalanche breakdown.
  • the invention may be used with the other forms of avalanche switching, e.g. where the transistors are individually biased to below the collector-base breakdown voltage.
  • the described invention may be used with any appropriate load and is not limited to driving the sweep plates of a streak camera.
  • Some capacitance in the load is essential to ensure the transistors, especially those at the ends of the chain, saturate on avalanche switching, but unavoidable stray capacitance may often be sufficient for this purpose unless fully compensated by load inductance.

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  • Electronic Switches (AREA)
  • Generation Of Surge Voltage And Current (AREA)
  • Power Conversion In General (AREA)
  • Dc-Dc Converters (AREA)
US09/319,770 1996-12-12 1997-12-12 Converter with continuous currents flowing through secondary windings Expired - Lifetime US6198269B1 (en)

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GBGB9625821.5A GB9625821D0 (en) 1996-12-12 1996-12-12 Fast voltage ramp generator
GB9625821 1996-12-12
PCT/GB1997/003437 WO1998026505A1 (en) 1996-12-12 1997-12-12 High voltage ramp generator

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EP (1) EP0944958B1 (de)
JP (1) JP3848999B2 (de)
KR (1) KR20000057530A (de)
CA (1) CA2274856A1 (de)
DE (1) DE69713142T2 (de)
GB (2) GB9625821D0 (de)
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Cited By (3)

* Cited by examiner, † Cited by third party
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US20030090304A1 (en) * 2000-04-17 2003-05-15 Alfred Schaal Fast sweep voltage ramp generator and streak camera using same
US20080231337A1 (en) * 2007-03-23 2008-09-25 University Of Southern California Compact subnanosecond high voltage pulse generation system for cell electro-manipulation
US20150062982A1 (en) * 2012-05-10 2015-03-05 Sma Solar Technology Ag Circuit Arrangement and Method for Actuating at Least One Switching Element of a Voltage Converter

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DE102007014268A1 (de) * 2007-03-21 2008-10-02 Ltb Lasertechnik Berlin Gmbh Schaltanordnung mit zumindest zwei ausgangsseitig elektrisch in Reihe geschalteten Schaltstufen
CN108712162B (zh) * 2018-04-27 2022-05-06 湖北大学 一种雪崩晶体管串并联高压快沿开关电路

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US5434456A (en) 1993-02-09 1995-07-18 The Regents Of The University Of California Lumped transmission line avalanche pulser

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US3636476A (en) 1969-11-07 1972-01-18 Westinghouse Electric Corp Solid-state double resonant pulser
US3710147A (en) 1971-06-29 1973-01-09 Plessey Handel Investment Ag Transistor switches for high voltage applications
US3927365A (en) 1972-03-31 1975-12-16 Tokyo Shibaura Electric Co Switch operating device
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FR2632136A1 (fr) 1988-05-31 1989-12-01 Commissariat Energie Atomique Commutateur haute tension a semi-conducteurs cables en serie
US5099211A (en) * 1990-03-26 1992-03-24 Nowak Dieter K Battery voltage measurement system
US5434456A (en) 1993-02-09 1995-07-18 The Regents Of The University Of California Lumped transmission line avalanche pulser

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030090304A1 (en) * 2000-04-17 2003-05-15 Alfred Schaal Fast sweep voltage ramp generator and streak camera using same
US6809563B2 (en) * 2000-04-17 2004-10-26 Commissariat A L'energie Atomique Fast sweep voltage ramp generator and streak camera using same
US20080231337A1 (en) * 2007-03-23 2008-09-25 University Of Southern California Compact subnanosecond high voltage pulse generation system for cell electro-manipulation
US9493765B2 (en) * 2007-03-23 2016-11-15 University Of Southern California Compact subnanosecond high voltage pulse generation system for cell electro-manipulation
US10301587B2 (en) 2007-03-23 2019-05-28 University Of Southern California Compact subnanosecond high voltage pulse generation system for cell electro-manipulation
US20150062982A1 (en) * 2012-05-10 2015-03-05 Sma Solar Technology Ag Circuit Arrangement and Method for Actuating at Least One Switching Element of a Voltage Converter

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WO1998026505A1 (en) 1998-06-18
CA2274856A1 (en) 1998-06-18
DE69713142T2 (de) 2002-11-14
EP0944958B1 (de) 2002-06-05
JP2002501686A (ja) 2002-01-15
GB9625821D0 (en) 1997-01-29
GB2336959B (en) 2001-04-25
GB9913849D0 (en) 1999-08-11
EP0944958A1 (de) 1999-09-29
GB2336959A (en) 1999-11-03
DE69713142D1 (de) 2002-07-11
JP3848999B2 (ja) 2006-11-22
KR20000057530A (ko) 2000-09-25

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