US6105226A - Leadless ceramic chip carrier crosstalk suppression method - Google Patents

Leadless ceramic chip carrier crosstalk suppression method Download PDF

Info

Publication number
US6105226A
US6105226A US09/237,212 US23721299A US6105226A US 6105226 A US6105226 A US 6105226A US 23721299 A US23721299 A US 23721299A US 6105226 A US6105226 A US 6105226A
Authority
US
United States
Prior art keywords
layer
metalized
input
output
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/237,212
Inventor
John G. Gore
Neal J. Tolar
Roy B. Brown
Sunder Gopani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Triquint Inc
Original Assignee
Sawtek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sawtek Inc filed Critical Sawtek Inc
Priority to US09/237,212 priority Critical patent/US6105226A/en
Application granted granted Critical
Publication of US6105226A publication Critical patent/US6105226A/en
Assigned to TRIQUINT, INC. reassignment TRIQUINT, INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: SAWTEK INC.
Anticipated expiration legal-status Critical
Assigned to SAWTEK, INC. reassignment SAWTEK, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GORE, JOHN G., TOLAR, NEAL J., BROWN, ROY B., GOPANI, SUNDER
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/10Mounting in enclosures
    • H03H9/1064Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1071Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/42Piezoelectric device making
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49131Assembling to base an electrical component, e.g., capacitor, etc. by utilizing optical sighting device
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/53Means to assemble or disassemble
    • Y10T29/5313Means to assemble electrical device
    • Y10T29/53174Means to fasten electrical component to wiring board, base, or substrate
    • Y10T29/53178Chip component

Definitions

  • the invention relates to printed circuit board surface mounted electronic chip packaging and more particularly to decreasing crosstalk or electromagnetic feedthrough in leadless ceramic chip carriers for surface acoustic wave filters.
  • surface mount technology offers several advantages for electronic equipment manufacturers including the economic advantage of increased component packing density.
  • surface mount technology carries with it the problem of thermal mismatch between the surface mount package and the printed circuit (PC) board.
  • the thermal mismatch problems are especially acute for relatively large leadless chip carrier in which the distance between soldering pads is also relatively large.
  • crosstalk In addition to the thermal mismatch problems, electromagnetic feedthrough, also referred to as crosstalk, between input and output circuits create undesired effects and can be one of the most troublesome sources of interference in SAW devices.
  • Crosstalk or electromagnetic feedthrough in a SAW filter relates to the direct coupling of an input signal from input to output interdigital transducer, in the form of electromagnetic radiation.
  • crosstalk is suppressed by providing grounding and RF shielding between the input and output transducers to reduce and preferably prevent inductive or capacitive coupling in the SAW filter.
  • ground connections are made from the seal ring to the bottom side of the soldering ground pads through only the four corners of the carrier, by going through the two ceramic top layers and connecting to plated castellations on the bottom or final layer.
  • This series and parallel combination styled grounding path does not provide sufficient RF grounding for the SAW devices earlier described.
  • an embodiment of a multilayer ceramic chip carrier useful in surface mounting high performance surface acoustic wave (SAW) devices comprises a first ceramic layer having a metalized top surface, a bottom surface and an aperture formed within a center portion of the first layer for receiving a SAW device therein, the first layer aperture forming a first layer inside wall, the first layer having a protrusion extending into the aperture from an inside wall portion, a second ceramic layer having top and bottom surfaces and an aperture formed within a center portion of the second layer for receiving the SAW device therein, the second layer aperture forming a second layer inside wall, the second layer top surface having metalized surface portions for providing internal input, output and ground connections from the carrier second layer to SAW device input, output and grounds connections respectively, the second layer top surface attached to the first layer bottom surface wherein the second layer metalized surface portions are accessible for making wire bond connections thereto, the ground connections and protrusion positioned between the input and output connections, a third ceramic layer having a metalized top surface and a
  • the ground connecting means comprises the first layer having a hole passing from the first layer top surface to the first layer bottom surface within the protrusion, the second layer having a hole passing from the second layer top surface to the bottom surface within the metalized surface portion having the internal ground connection, the third layer having a hole passing through the third layer from the metalized third layer top surface to the external ground connection, the second layer hole connected between the first and third layer holes, the holes positioned between the input and output connection, and conductive refractory material filling the holes for providing the ground path between the first layer top metalized surface and the carrier external ground connection.
  • a first ceramic layer to which a package seal is placed comprises the protrusion to which the seal is brazed.
  • the protrusion is electrically connected to the metalized layers on the lower ceramic layers and ultimately to package ground pads through via holes which are filled with the electrically conductive material.
  • the via holes are strategically placed between input and output wire bond pads within the package for providing a barrier to crosstalk between input and output connections.
  • a central ground pad is provided on the bottom side of the package for electrical connection with metalized layers of the layered package for added crosstalk suppression.
  • input and output bond wire pads within the package are separated by a greater distance than their corresponding input and output pads on the bottom surface of the package.
  • FIG. 1a is a top right perspective view of an embodiment of the present invention illustrating bond wire connection of a SAW device within a package cavity;
  • FIG. 1b is a bottom perspective view of the package of FIG. 1a;
  • FIG. 2 is an exploded top right perspective view of a prior art multilayer leadless ceramic chip carrier
  • FIG. 3 is an exploded top right perspective view of a multilayer leadless ceramic chip carrier embodiment of the present invention.
  • FIG. 4 is a transverse and longitudinal fragmented perspective view of an embodiment of the present invention for a leadless ceramic chip carrier of FIGS. 1a and 1b;
  • FIGS. 5a and 5b are top and bottom plans views respectively of a metalized ceramic base layer for an embodiment of the present invention.
  • FIG. 5c is a top plan view of a metalized base ceramic layer illustrating an increased separation between carrier internal input and output pads
  • FIGS. 6a-6d are plan views illustrating metalized layers within an embodiment of a multilayer ceramic carrier of the present invention.
  • FIGS. 6e and 6f are plan views illustrating alternate embodiments of metalized ceramic layers using extended separations between input and output internal bond pads.
  • FIGS. 7a-7c are frequency response profiles of a SAW filter packaged within a typical surface mount package; a simulated package having enhanced grounding using metal filled via holes; and a package of a preferred embodiment of the present invention comprising filled via holes, protrusions and separation of bond pads, respectively.
  • a surface mount package 10 for mounting a SAW device 12 onto a printer circuit board 14.
  • the package 10 comprises a leadless ceramic chip carrier 16 having a cavity portion 18 for receiving the device 12.
  • input bond pads 20, 21, wire bonded to device input transducer 26, output bond pads 22, 23 wire bonded to output transducer 28, and ground bond pads 24, 25 wire bonded to center ground strip 27 are positioned for electrically connecting the device 12 to the package 10.
  • interchangeable use of input and output transducers is permitted.
  • the package 10 further comprises a seal ring 32 brazed to the carrier 16 and a cover 34 itself brazed to the seal ring 32 for hermetically sealing the device 12 within the package 10.
  • the cover 34 illustrated with reference to FIG. 1a is shown in fragmented form.
  • the seal ring 32 forms a metallic top surface peripheral portion of the carrier 16.
  • a Kovar seal ring 32 is used and has a material composition of 54% Fe, 17% Co, and 29% Ni.
  • Kovar is well known for its use in seal rings, lead frames, and input/output pins.
  • the cover 34 is placed onto the seal ring 32 and welded thereto. In typical configurations, the cover 34 is approximately 0.005 to 0.020 inches above bond wires 35, very close when considering detrimental electromagnetic field effects.
  • the typical package 11 and multilayer ceramic carrier 17, illustrated in an exploded view again with reference to FIG. 2, comprises three ceramic layers, a first layer 38 attached to a second layer 40 wherein each of the first and second layers 38, 40 have center apertures 44, 46 formed therein, and a third layer 42 which forms the base 48 is attached to the second layer 40.
  • the apertures 44, 46 and base 48 together cooperate to form the carrier cavity portion 18 described earlier with reference to the package 10 of FIGS. 1a and 1b for receiving the device 12 placed therein.
  • grounding from the seal ring 32 to ground pads 56 on the bottom side of the base 48 is through conductive material 50 on the four outside corners of the carrier 16.
  • the conductive material 50 is carried by corners of the layers 38, 40, and 42 and is electrically connected to a metalization surface 52 within the cavity portion 18 on the third layer 42 which forms the base 48 of the package 10.
  • the metalization surface 52 extend within the hermetically sealed cavity portion 18 to plated ground castellations 54 on outside surfaces of the carrier 16.
  • the castellations 54 are then electrically connected to the connection ground pads 56 on the bottom of the carrier 16 for connection to pads on a printed circuit board.
  • Such a series and parallel path for electrically grounding the seal ring 32 to the ground pads 56 typically does not provide an adequate RF ground and unacceptable levels of crosstalk between inputs and outputs of the device 12 exists.
  • the embodiment of the present invention includes the corner conductive material 50 and as illustrated with reference to FIGS. 1a and 3, also contains internal corner conductive material 51 on layer and seal ring corner portions.
  • the three layers 38, 40, and 42 are typically made from unsintered ceramic sheets. Each sheet is stacked and bonded to form the multilayer or laminated carrier construction.
  • the layers 38, 40 are punched to form the apertures 44, 46 which when laminated together with the third layer 42 form the carrier 16.
  • Metalization surface portions are formed on each layer.
  • the first layer 38 has a metalization surface portion formed generally on a top surface 58 to which the seal ring 32 is brazed as earlier described.
  • the second layer 40 has metalization surface portions which define the input 20, output 22 and ground 24 pads within the carrier cavity portion 18 to which the device bond wires 35 are attached as earlier described.
  • the base 48, the third layer 42 has the metalization surface 52 as earlier described and a metalization surface 60 on its bottom side described later in further detail.
  • the third layer 42 is the only ceramic layer with metalization surfaces on both top and bottom surfaces of the layer 42.
  • the electrical ground path from the seal ring 32 to the ground pads 56 for connection to printed circuit pads 15, is through the four corner conductive material 50, four corner metalized radii on the exterior of the carrier 17.
  • this metal is added by refractory metalization which is very thin.
  • some metalized surfaces are gold plated to improve electrical conductivity, typically these four corners are not.
  • the location of the corners relative to the SAW device 12 and wire bonds is remote.
  • the only conductive path from the seal ring 32 to the ground pad 62 on the metalized surface 52 of the third layer 42 is through the corner conductive material 50, the plated radii along the side of the carrier 16 that conduct from the metalized surface 52 to corresponding ground pads 56 on the bottom side of the carrier 16.
  • the result is a series and parallel path from seal ring 32 to ground pads 56 that is somewhat resistive and not strategically located relative to the SAW device 12 and the bond wires 35.
  • an object of the present invention is to provide a surface mount package with improved grounding and RF shield between the inputs and outputs of the SAW device for reducing electromagnetic feedthrough effects.
  • the leadless ceramic chip carrier 16 includes a first layer 38 having a protrusion 64 (part of the barrier 30 earlier described) which extends inwardly into the cavity portion 18.
  • the protrusion 64 is positioned for placement between the input pad 20 and output pad 22 and includes a metalized top surface 66 contiguous with the metalized surface 58 of the first layer 38.
  • the protrusion 64 extends sufficiently into the cavity portion 18 to permit via holes (described later in greater detail) filled with conductive refractory material to pass from contact with the conductive protrusion top metal surface 66 to ground pads 62 on the bottom surface of the carrier 16.
  • opposing protrusions 64, 65 extending into the cavity portion 18 are limited in size for permitting the device 12 selected for use to be placed therebetween and within the cavity portion 18 of the carrier 16.
  • the carrier internal ground pads 24, 25 are in electrical contact with the respective protrusion 64, 65 electrically conductive surface 66 through a metalized side surface 68 in addition to electrical contact through the conductive vias 70 as illustrated with reference to FIG. 4 of a transversely and longitudinally fragmented perspective view of an a carrier 16.
  • the protrusions 64, 66 thus provide an electrical shield between the input and output pads 20, 21, 22, 23 as illustrated again with reference to FIGS. 1a, 1b and 3.
  • the placement of the vias 70 as described, provides an excellent ground plane between device input and output channels and thus a strong barrier to crosstalk.
  • the vias 70 in an embodiment illustrated with reference to FIGS. 4 and 5a-5d are located approximately midway between an inner wall 80 and outer wall 82 of the first layer 38 as measured along a plane passing through the protrusion 64.
  • five conductively filled vias 70 provide the lowered resistance path (when compared to the four corners earlier described) from the first layer 38 through the second layer 40 and onto the bottom or third layer 42.
  • ground metalization that is part of second layer metalization surface portions 84 is positioned directly between the input 20, 21 and output 22, 23 internal connection pads and covers most of the metalized surface area between the input and output pads on both sides of the internal wire bond pad shelf 86 as illustrated again with reference to FIGS. 6b and 1a.
  • the separation 76 between carrier bottom side input 72, 73 and output 74, 75 pads are positioned for typical connection with pads of a printed circuit board, thus eliminating the need for PC board redesign.
  • well known problems associated with thermal mismatch are reduced.
  • crosstalk is sufficiently reduced for an effective operation of the SAW device 12, an object of the present invention.
  • An examples of the greater separation 77 of input and output pads 20e, 21e, 22e, 23e is also illustrated with reference to FIG.
  • bond wires connected between the SAW device and internal input and output pads will be positioned in a non-parallel, typically radially diverging orientation due to the increased separation between the internal input and output pads and device pads, an arrangement which further aids in crosstalk suppression.
  • twenty two conductive vias 71 within a matrix configuration are located in a central portion of the carrier base 48 and penetrate the third layer 42 for connecting the third layer internal ground plane metalized surface 52 with a rectangular central ground pad 88 located on the underside of the package 10.
  • Such an arrangement provides further RF shielding between the device input and output.
  • the straight line path between these hot connections is obstructed by the twenty two electrically conductive vias 71 while the "hot” input and output return connections are obstructed by the vias 70 that make connection to the ground pads 62 on each side of the package 10.
  • the vias 70, 71 and metalization surfaces herein described for the various ceramic layers 38, 40, 42 provide an effective crosstalk barrier.
  • FIG. 7a illustrates a measured frequency response 92 of a SAW device within a prior art package having the carrier 17 earlier described.
  • Crosstalk levels 94 of approximately -40 dB result in an inadequate side lobe performance for the device.
  • FIG. 7b illustrates a measured frequency response of the same SAW device in a surface mount package using bond wires or conductive epoxy to simulate the conductive vias through the ceramic layers, but in this example without the protrusion.
  • cross talk suppression 98 is improved by more than 10 dB.
  • the response 100 illustrated with reference to FIG. 7c is realized.
  • the reduction in crosstalk 102 for the SAW device by more than 25 dB is achieved over the package of the prior art.
  • Performance of operational devices within the package of the present invention show significant crosstalk suppression as well.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Acoustics & Sound (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

A leadless ceramic chip carrier useful in surface mounting of SAW devices includes electrically conductive vias and metalization between input and output bond pads for improved crosstalk suppression between input and output device connections. A protrusion extending from a top layer of a multilayer ceramic carrier provides additional electrical contact to a package seal brazed thereto. The vias are positioned between input and output bond pads and connect the metalized protrusion to package ground pads through contact with multiple metalized layers of the package for enhancing the electrical connection between the package Kovar seal ring and customer accessed ground pads. For further suppression of crosstalk, bond pads within the package for connection to the SAW device are spaced at a greater distance from each other than their corresponding pads on the package bottom surface thus maintaining an optimum spacing for package connection to printed circuit board pads for minimizing thermal mismatch effects.

Description

CROSS REFERENCE TO RELATED APPLICATION
This application is a divisional of application Ser. No. 08/648,662 filed May 16, 1996 and issuing as U.S. Pat. No. 5,864,092, all commonly owned and assigned with the present application.
BACKGROUND OF INVENTION
1. Field of Invention
The invention relates to printed circuit board surface mounted electronic chip packaging and more particularly to decreasing crosstalk or electromagnetic feedthrough in leadless ceramic chip carriers for surface acoustic wave filters.
2. Description of Background Art
Surface mount technology offers several advantages for electronic equipment manufacturers including the economic advantage of increased component packing density. As described in U.S. Pat. No. 5,369,551 to Gore et al., surface mount technology carries with it the problem of thermal mismatch between the surface mount package and the printed circuit (PC) board. In particular, the thermal mismatch problems are especially acute for relatively large leadless chip carrier in which the distance between soldering pads is also relatively large.
In addition to the thermal mismatch problems, electromagnetic feedthrough, also referred to as crosstalk, between input and output circuits create undesired effects and can be one of the most troublesome sources of interference in SAW devices. By way of example, if in a design of a SAW filter, crosstalk is not sufficiently suppressed, the desired frequency response of the filter will not be achieved. Crosstalk or electromagnetic feedthrough in a SAW filter relates to the direct coupling of an input signal from input to output interdigital transducer, in the form of electromagnetic radiation. Typically, in a SAW device, crosstalk is suppressed by providing grounding and RF shielding between the input and output transducers to reduce and preferably prevent inductive or capacitive coupling in the SAW filter.
With the typically tight arrangement of SAW device and package elements, conductors proximate to each other, yet not hard wired or intended to communicate with each other, will be coupled to a degree sufficient to disrupt the intended operation of the device. Further, in leadless chip ceramic carriers (LCCC) typical in the art, grounding between the seal ring at the upper end of a package and the customer common pads on the package bottom side does not provide a sufficient ground path to adequately suppress crosstalk and thus SAW device performance is adversely affected. In some cases, crosstalk is actually enhanced by an inadequate ground path. By way of example, in the manufacturing of well known multilayer ceramic chip carriers, ground connections are made from the seal ring to the bottom side of the soldering ground pads through only the four corners of the carrier, by going through the two ceramic top layers and connecting to plated castellations on the bottom or final layer. This series and parallel combination styled grounding path does not provide sufficient RF grounding for the SAW devices earlier described.
In spite of efforts made to date, there exists a need in the packaging art, especially for SAW device surface mount packages, to provide an improved surface mount package whereby crosstalk suppression is sufficient to obtain the desired performance from the SAW device being packaged.
SUMMARY OF INVENTION
It is a primary object of the invention to reduce electromagnetic signal effects or crosstalk between SAW device input and output connections. It is another object of the invention to provide improved grounding within a surface mount package for enhancing crosstalk suppression. It is an object to enhance crosstalk suppression while maintaining package size for optimum efficiency in circuit design and reduction of thermal mismatch effects. It is another object of the present invention to provide sufficient grounding of a surface mount package for enhancing the desired response of a SAW device carried by the package. It is yet another object of the invention to provide improved grounding between the seal ring of a surface mount package and common ground pads. It is further an object of the invention to provide sufficient separation between input and output bond connections within the surface mount package for reducing crosstalk while maintaining a bond pad configuration for connection to PC board pads that minimizes thermal expansion concerns.
To meet these and other objects of the invention, an embodiment of a multilayer ceramic chip carrier useful in surface mounting high performance surface acoustic wave (SAW) devices comprises a first ceramic layer having a metalized top surface, a bottom surface and an aperture formed within a center portion of the first layer for receiving a SAW device therein, the first layer aperture forming a first layer inside wall, the first layer having a protrusion extending into the aperture from an inside wall portion, a second ceramic layer having top and bottom surfaces and an aperture formed within a center portion of the second layer for receiving the SAW device therein, the second layer aperture forming a second layer inside wall, the second layer top surface having metalized surface portions for providing internal input, output and ground connections from the carrier second layer to SAW device input, output and grounds connections respectively, the second layer top surface attached to the first layer bottom surface wherein the second layer metalized surface portions are accessible for making wire bond connections thereto, the ground connections and protrusion positioned between the input and output connections, a third ceramic layer having a metalized top surface and a bottom surface, the third ceramic layer top surface receiving the second layer bottom surface for forming a cavity, the cavity having inside walls formed from the first and second layer inside walls and a bottom wall formed from the third layer top surface, the cavity sufficient for receiving the SAW device therein, the third layer bottom surface having metalized surface portions for providing external input, output and ground connections from the carrier to input, output and ground connections on a printed circuit board, the ground connections positioned between the input and output connections, and ground connecting means for providing an ground path from the first layer metalized top surface through the protrusion and the internal ground connection to the external ground connection, the ground path positioned between respective input and output connections for providing an electromagnetic shield therebetween. In one embodiment, the ground connecting means comprises the first layer having a hole passing from the first layer top surface to the first layer bottom surface within the protrusion, the second layer having a hole passing from the second layer top surface to the bottom surface within the metalized surface portion having the internal ground connection, the third layer having a hole passing through the third layer from the metalized third layer top surface to the external ground connection, the second layer hole connected between the first and third layer holes, the holes positioned between the input and output connection, and conductive refractory material filling the holes for providing the ground path between the first layer top metalized surface and the carrier external ground connection.
In a preferred embodiment of the multilayered ceramic chip carrier or package, a first ceramic layer to which a package seal is placed comprises the protrusion to which the seal is brazed. The protrusion is electrically connected to the metalized layers on the lower ceramic layers and ultimately to package ground pads through via holes which are filled with the electrically conductive material. The via holes are strategically placed between input and output wire bond pads within the package for providing a barrier to crosstalk between input and output connections. A central ground pad is provided on the bottom side of the package for electrical connection with metalized layers of the layered package for added crosstalk suppression. Further, input and output bond wire pads within the package are separated by a greater distance than their corresponding input and output pads on the bottom surface of the package. With such an arrangement, crosstalk suppression is further enhanced within the package while thermal mismatch, greater for greater separation of solder pads, is minimized by maintaining an optimum distance between pads on the package for connection to PC boards.
BRIEF DESCRIPTION OF DRAWINGS
A preferred embodiment of the invention as well as alternate embodiments are described by way of example with reference to the accompanying drawings in which:
FIG. 1a is a top right perspective view of an embodiment of the present invention illustrating bond wire connection of a SAW device within a package cavity;
FIG. 1b is a bottom perspective view of the package of FIG. 1a;
FIG. 2 is an exploded top right perspective view of a prior art multilayer leadless ceramic chip carrier;
FIG. 3 is an exploded top right perspective view of a multilayer leadless ceramic chip carrier embodiment of the present invention;
FIG. 4 is a transverse and longitudinal fragmented perspective view of an embodiment of the present invention for a leadless ceramic chip carrier of FIGS. 1a and 1b;
FIGS. 5a and 5b are top and bottom plans views respectively of a metalized ceramic base layer for an embodiment of the present invention;
FIG. 5c is a top plan view of a metalized base ceramic layer illustrating an increased separation between carrier internal input and output pads;
FIGS. 6a-6d are plan views illustrating metalized layers within an embodiment of a multilayer ceramic carrier of the present invention;
FIGS. 6e and 6f are plan views illustrating alternate embodiments of metalized ceramic layers using extended separations between input and output internal bond pads; and
FIGS. 7a-7c are frequency response profiles of a SAW filter packaged within a typical surface mount package; a simulated package having enhanced grounding using metal filled via holes; and a package of a preferred embodiment of the present invention comprising filled via holes, protrusions and separation of bond pads, respectively.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENT
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
Referring now to FIGS. 1a and 1b, a preferred embodiment of the present invention, a surface mount package 10 for mounting a SAW device 12 onto a printer circuit board 14. The package 10 comprises a leadless ceramic chip carrier 16 having a cavity portion 18 for receiving the device 12. Within the carrier cavity portion 18, input bond pads 20, 21, wire bonded to device input transducer 26, output bond pads 22, 23 wire bonded to output transducer 28, and ground bond pads 24, 25 wire bonded to center ground strip 27 are positioned for electrically connecting the device 12 to the package 10. As is well known in the SAW art, interchangeable use of input and output transducers is permitted. For reducing crosstalk between the SAW device input transducer 26 and output transducer 28, a conductive grounded barrier 30 is formed between the input pads 20, 21 of input transducer 26 and the output pads 22, 23 of output transducer 28. It has been determined through development and testing of the present invention, that an electrically conductive barrier not providing sufficient grounding can enhance crosstalk and actually increase the electrical coupling between inputs and outputs, a situation to avoid. Again with reference to FIG. 1a, the package 10 further comprises a seal ring 32 brazed to the carrier 16 and a cover 34 itself brazed to the seal ring 32 for hermetically sealing the device 12 within the package 10. The cover 34 illustrated with reference to FIG. 1a is shown in fragmented form.
In one embodiment of the present invention, well known multilayer ceramic packaging methods and devices are improved upon with a primary object of reducing crosstalk, as earlier described.
To describe such improvements, first consider a multilayer ceramic chip carrier 17 known in the art and described herein with reference to FIG. 2, illustrated in an exploded view. As is the case for the illustrated embodiment of the present invention, the seal ring 32 forms a metallic top surface peripheral portion of the carrier 16. Typically a Kovar seal ring 32 is used and has a material composition of 54% Fe, 17% Co, and 29% Ni. Kovar is well known for its use in seal rings, lead frames, and input/output pins. When the device 12, as illustrated in FIG. 1a, is in the package 10 and all connections (e.g. attached bond wires 35) between the device 12 and carrier 16 have been made, the cover 34 is placed onto the seal ring 32 and welded thereto. In typical configurations, the cover 34 is approximately 0.005 to 0.020 inches above bond wires 35, very close when considering detrimental electromagnetic field effects.
The typical package 11 and multilayer ceramic carrier 17, illustrated in an exploded view again with reference to FIG. 2, comprises three ceramic layers, a first layer 38 attached to a second layer 40 wherein each of the first and second layers 38, 40 have center apertures 44, 46 formed therein, and a third layer 42 which forms the base 48 is attached to the second layer 40. The apertures 44, 46 and base 48 together cooperate to form the carrier cavity portion 18 described earlier with reference to the package 10 of FIGS. 1a and 1b for receiving the device 12 placed therein. Typically, grounding from the seal ring 32 to ground pads 56 on the bottom side of the base 48 is through conductive material 50 on the four outside corners of the carrier 16. The conductive material 50 is carried by corners of the layers 38, 40, and 42 and is electrically connected to a metalization surface 52 within the cavity portion 18 on the third layer 42 which forms the base 48 of the package 10. The metalization surface 52 extend within the hermetically sealed cavity portion 18 to plated ground castellations 54 on outside surfaces of the carrier 16. The castellations 54 are then electrically connected to the connection ground pads 56 on the bottom of the carrier 16 for connection to pads on a printed circuit board. Such a series and parallel path for electrically grounding the seal ring 32 to the ground pads 56 typically does not provide an adequate RF ground and unacceptable levels of crosstalk between inputs and outputs of the device 12 exists. The embodiment of the present invention includes the corner conductive material 50 and as illustrated with reference to FIGS. 1a and 3, also contains internal corner conductive material 51 on layer and seal ring corner portions.
Again with reference to FIG. 2, in this type of leadless ceramic chip carrier, the three layers 38, 40, and 42 are typically made from unsintered ceramic sheets. Each sheet is stacked and bonded to form the multilayer or laminated carrier construction. The layers 38, 40 are punched to form the apertures 44, 46 which when laminated together with the third layer 42 form the carrier 16. Metalization surface portions are formed on each layer. The first layer 38 has a metalization surface portion formed generally on a top surface 58 to which the seal ring 32 is brazed as earlier described. The second layer 40 has metalization surface portions which define the input 20, output 22 and ground 24 pads within the carrier cavity portion 18 to which the device bond wires 35 are attached as earlier described. The base 48, the third layer 42, has the metalization surface 52 as earlier described and a metalization surface 60 on its bottom side described later in further detail. Typically the third layer 42 is the only ceramic layer with metalization surfaces on both top and bottom surfaces of the layer 42.
With ceramic and metalization multilayer carriers typical in the art, crosstalk is not adequately reduced, especially when using high performance SAW devices 12. As described earlier, the electrical ground path from the seal ring 32 to the ground pads 56 for connection to printed circuit pads 15, is through the four corner conductive material 50, four corner metalized radii on the exterior of the carrier 17. Typically, this metal is added by refractory metalization which is very thin. Although some metalized surfaces are gold plated to improve electrical conductivity, typically these four corners are not. Further, in addition to poor conductivity through the corner conductive material 50, the location of the corners relative to the SAW device 12 and wire bonds is remote. In addition, the only conductive path from the seal ring 32 to the ground pad 62 on the metalized surface 52 of the third layer 42 is through the corner conductive material 50, the plated radii along the side of the carrier 16 that conduct from the metalized surface 52 to corresponding ground pads 56 on the bottom side of the carrier 16. The result is a series and parallel path from seal ring 32 to ground pads 56 that is somewhat resistive and not strategically located relative to the SAW device 12 and the bond wires 35.
As earlier stated, an object of the present invention is to provide a surface mount package with improved grounding and RF shield between the inputs and outputs of the SAW device for reducing electromagnetic feedthrough effects. By constraining overall internal and external package configurations to those known and currently used in the art, the embodiment of the package 10 of the present invention satisfies an important need in the industry. With reference to similar elements as described with reference to FIG. 2, the package 10 described with reference to FIGS. 1a, 1b and 3 is further detailed.
With reference to FIG. 3 and again to FIG. 1a, the leadless ceramic chip carrier 16 includes a first layer 38 having a protrusion 64 (part of the barrier 30 earlier described) which extends inwardly into the cavity portion 18. The protrusion 64 is positioned for placement between the input pad 20 and output pad 22 and includes a metalized top surface 66 contiguous with the metalized surface 58 of the first layer 38. The protrusion 64 extends sufficiently into the cavity portion 18 to permit via holes (described later in greater detail) filled with conductive refractory material to pass from contact with the conductive protrusion top metal surface 66 to ground pads 62 on the bottom surface of the carrier 16. At the same time, opposing protrusions 64, 65 extending into the cavity portion 18 are limited in size for permitting the device 12 selected for use to be placed therebetween and within the cavity portion 18 of the carrier 16. When assembled, the carrier internal ground pads 24, 25 are in electrical contact with the respective protrusion 64, 65 electrically conductive surface 66 through a metalized side surface 68 in addition to electrical contact through the conductive vias 70 as illustrated with reference to FIG. 4 of a transversely and longitudinally fragmented perspective view of an a carrier 16. The protrusions 64, 66 thus provide an electrical shield between the input and output pads 20, 21, 22, 23 as illustrated again with reference to FIGS. 1a, 1b and 3. Through the brazing of the seal ring 32 to the first layer top surface 58, the increased surface area provided by the protrusion top metalized surface 66, and the conductive vias 70, an improved, direct, electrical path from the seal ring 32 to the ground pads 56 is provided.
The placement of the vias 70 as described, provides an excellent ground plane between device input and output channels and thus a strong barrier to crosstalk. The vias 70 in an embodiment illustrated with reference to FIGS. 4 and 5a-5d are located approximately midway between an inner wall 80 and outer wall 82 of the first layer 38 as measured along a plane passing through the protrusion 64. As illustrated with reference to FIGS. 1b, 4, 6a-6d, five conductively filled vias 70 provide the lowered resistance path (when compared to the four corners earlier described) from the first layer 38 through the second layer 40 and onto the bottom or third layer 42. In addition to the vias 70 within the second layer 40, the ground metalization that is part of second layer metalization surface portions 84 is positioned directly between the input 20, 21 and output 22, 23 internal connection pads and covers most of the metalized surface area between the input and output pads on both sides of the internal wire bond pad shelf 86 as illustrated again with reference to FIGS. 6b and 1a.
Further, and as illustrated with reference to FIGS. 5a-5c, the separation 76 between carrier bottom side input 72, 73 and output 74, 75 pads are positioned for typical connection with pads of a printed circuit board, thus eliminating the need for PC board redesign. In addition, by maintaining as small a distance between bottom side input 72 73 and output 74, 75 pads as possible, well known problems associated with thermal mismatch are reduced. However, by having a greater separation 77 between internal input 20, 21 and output 22, 23 pads, as illustrated again with reference to FIG. 6f, crosstalk is sufficiently reduced for an effective operation of the SAW device 12, an object of the present invention. An examples of the greater separation 77 of input and output pads 20e, 21e, 22e, 23e is also illustrated with reference to FIG. 5c, a plan view of a metalized ceramic layer. Further, bond wires connected between the SAW device and internal input and output pads will be positioned in a non-parallel, typically radially diverging orientation due to the increased separation between the internal input and output pads and device pads, an arrangement which further aids in crosstalk suppression.
Again with reference to FIGS. 4, 5a-5c, and 6d-6re in the package 10 illustrated by way of example for the present invention, twenty two conductive vias 71 within a matrix configuration are located in a central portion of the carrier base 48 and penetrate the third layer 42 for connecting the third layer internal ground plane metalized surface 52 with a rectangular central ground pad 88 located on the underside of the package 10. Such an arrangement provides further RF shielding between the device input and output. By way of example, when "hot" input and "hot" output connections are on opposing sides of a package 10, the straight line path between these hot connections is obstructed by the twenty two electrically conductive vias 71 while the "hot" input and output return connections are obstructed by the vias 70 that make connection to the ground pads 62 on each side of the package 10. Thus, the vias 70, 71 and metalization surfaces herein described for the various ceramic layers 38, 40, 42 provide an effective crosstalk barrier.
By way of example, and with reference to FIGS. 7a-7c, the embodiment of the package 10 herein described provides significant improvement in crosstalk suppression. FIG. 7a illustrates a measured frequency response 92 of a SAW device within a prior art package having the carrier 17 earlier described. Crosstalk levels 94 of approximately -40 dB result in an inadequate side lobe performance for the device. FIG. 7b illustrates a measured frequency response of the same SAW device in a surface mount package using bond wires or conductive epoxy to simulate the conductive vias through the ceramic layers, but in this example without the protrusion. As illustrated with reference to FIG. 7b, cross talk suppression 98 is improved by more than 10 dB. However, by including the vias, the protrusions, and the increased separation between internal input and output pads, the response 100 illustrated with reference to FIG. 7c is realized. As illustrated, the reduction in crosstalk 102 for the SAW device by more than 25 dB is achieved over the package of the prior art. Performance of operational devices within the package of the present invention show significant crosstalk suppression as well.
Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and alternate embodiments are intended to be included within the scope of the appended claims.

Claims (12)

What is claimed is:
1. A method for suppressing crosstalk between inputs and outputs of a SAW device surface mounted for operation with a printed circuit board, the method comprising the steps of:
laminating a first ceramic layer to a second ceramic layer wherein the first ceramic layer comprises a metalized top surface, a bottom surface and an aperture formed within a center portion of the first layer for receiving a SAW device therein, the first layer aperture forming a first layer inside wall, the first layer further having a protrusion extending into the aperture from an inside wall portion, and wherein the second ceramic layer comprises top and bottom surfaces and an aperture formed within a center portion of the second layer for receiving the SAW device therein, the second layer aperture forming a second layer inside wall, the second layer top surface having metalized surface portions for providing internal input, output and ground connections from the carrier second layer to SAW device input, output and grounds connections respectively, the second layer top surface attached to the first layer bottom surface wherein the second layer metalized surface portions are accessible for making wire bond connections thereto, the ground connections and protrusion positioned between the input and output connections;
forming a cavity for receiving the SAW package by laminating a third ceramic layer to the second layer, the third layer comprising a metalized top surface and a bottom surface, the third ceramic layer top surface receiving the second layer bottom surface for forming the cavity, the cavity having inside walls formed from the first and second layer inside walls and a bottom wall formed from the third layer top surface, the third layer bottom surface having metalized surface portions for providing external input, output and ground connections from the carrier to input, output and ground connections on a printed circuit board, the ground connections positioned between the input and output connections; and
electrically connecting the first layer metalized top surface through the protrusion and the internal ground connection to the external ground connection, the electrical connecting having a path positioned between respective input and output connections for providing an electromagnetic shield therebetween.
2. A method according to claim 1 wherein the electrically connecting step comprises the steps of:
forming a hole through the first layer while passing the hole from the first layer top surface to the first layer bottom surface within the protrusion;
forming a hole through the second layer while passing the hole from the second layer top surface to the bottom surface within the metalized surface portion having the internal ground connection;
forming a hole through the third layer while passing the hole through the third layer from the metalized third layer top surface to the external ground connection, the second layer hole connected between the first and third layer holes, the holes positioned between the input and output connection; and
filling the holes with conductive refractory material for providing the electrical path between the first layer top metalized surface and the carrier external ground connection.
3. A method according to claim 1 further comprising the step of attaching a seal ring to the first layer metalized top surface for providing an electrical connection therebetween.
4. A method according to claim 1 further comprising the steps of:
placing a conductive seal ring onto the metalized top surface;
placing a conductive cover onto the seal ring; and
brazing the seal ring between the cover and first layer top surface for hermetically sealing the device within the carrier.
5. A carrier according to claim 1 further comprising the step of separating the internal input and output connections on the second layer top surface to a greater separation that between the external input and output connections on the third layer bottom surface.
6. A method according to claim 1 further comprising the steps of:
attaching an external central ground pad to the third layer bottom surface; and
electrically connecting the external ground pad to the third layer metalized surface.
7. A method according to claim 6 wherein the electrical connecting step comprises the steps of:
forming a hole in the third layer and passing the hole between the first layer top metalized surface and the central ground pad; and
filling the hole with conductive refractory material passing therethrough for electrically connecting the external ground pad to the metalized top surface.
8. A method according to claim 1 further comprising the step of attaching metalized material along inside wall portions for providing electrical connection between the internal ground connection and the first layer metalized top surface.
9. A method according to claim 1 wherein the external ground connecting step comprises the step of connecting multiple ground pads by forming electrically conductive vias between each ground pad and the first layer metalized surface, the vias passing within the protrusion, the conductive vias further in electrical contact with the metalized third layer top surface and the second layer ground connection metalized surface portion.
10. A method for suppressing crosstalk in surface acoustic wave (SAW) devices held within a surface mount package, the method comprising the steps of:
placing a SAW device within a cavity of a leadless chip carrier, the carrier having a metalized top portion attached to a seal ring, the carrier further having a protrusion extending into the cavity, the protrusion having a top metalized surface within electrical connection to the seal ring, the protrusion positioned between internal input and output pads within the cavity, the protrusion further having an electrical connection to an external ground pad positioned between corresponding external input and output pads, the electrical path passing between respective input and output pads for providing an electromagnetic shield therebetween.
attaching bond wires from the SAW device to the internal input, output and ground pads within the cavity; and
attaching a conductive cover onto the seal ring for hermetically sealing the SAW device within the carrier.
11. A method according to claim 10, further comprising the step of electrically connecting pads of a printed circuit board to cooperating external input, output and ground pads on a carrier bottom surface, the external ground pad positioned between the external input and output pads.
12. A method according to claim 10 wherein the attaching step comprises the step of brazing the conductive cover onto the carrier top portion.
US09/237,212 1996-05-16 1999-01-25 Leadless ceramic chip carrier crosstalk suppression method Expired - Lifetime US6105226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/237,212 US6105226A (en) 1996-05-16 1999-01-25 Leadless ceramic chip carrier crosstalk suppression method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/648,662 US5864092A (en) 1996-05-16 1996-05-16 Leadless ceramic chip carrier crosstalk suppression apparatus
US09/237,212 US6105226A (en) 1996-05-16 1999-01-25 Leadless ceramic chip carrier crosstalk suppression method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/648,662 Division US5864092A (en) 1996-05-16 1996-05-16 Leadless ceramic chip carrier crosstalk suppression apparatus

Publications (1)

Publication Number Publication Date
US6105226A true US6105226A (en) 2000-08-22

Family

ID=24601699

Family Applications (2)

Application Number Title Priority Date Filing Date
US08/648,662 Expired - Lifetime US5864092A (en) 1996-05-16 1996-05-16 Leadless ceramic chip carrier crosstalk suppression apparatus
US09/237,212 Expired - Lifetime US6105226A (en) 1996-05-16 1999-01-25 Leadless ceramic chip carrier crosstalk suppression method

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US08/648,662 Expired - Lifetime US5864092A (en) 1996-05-16 1996-05-16 Leadless ceramic chip carrier crosstalk suppression apparatus

Country Status (1)

Country Link
US (2) US5864092A (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6487087B1 (en) * 1999-01-28 2002-11-26 Bookham Technology Plc Optical interface arrangement
US6537849B1 (en) 2001-08-22 2003-03-25 Taiwan Semiconductor Manufacturing Company Seal ring structure for radio frequency integrated circuits
US20030138986A1 (en) * 2001-09-13 2003-07-24 Mike Bruner Microelectronic mechanical system and methods
US20030222332A1 (en) * 2002-05-29 2003-12-04 Intel Corporation High-power lga socket
US20040026778A1 (en) * 2000-01-12 2004-02-12 International Rectifier Corporation Low cost power semiconductor module without substate
US6717241B1 (en) * 2000-08-31 2004-04-06 Micron Technology, Inc. Magnetic shielding for integrated circuits
US20040082100A1 (en) * 2001-11-02 2004-04-29 Norihito Tsukahara Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component
US20040195683A1 (en) * 2003-04-03 2004-10-07 Fujitsu Media Devices Limited Compact electronic device and package used therefor
US20040217477A1 (en) * 2001-11-20 2004-11-04 Taiwan Semiconductor Manufacturing Company RF seal ring structure
US20040238928A1 (en) * 2003-05-30 2004-12-02 Naoyuki Mishima Electronic component and package
US6846423B1 (en) 2002-08-28 2005-01-25 Silicon Light Machines Corporation Wafer-level seal for non-silicon-based devices
US6877209B1 (en) 2002-08-28 2005-04-12 Silicon Light Machines, Inc. Method for sealing an active area of a surface acoustic wave device on a wafer
US20050093181A1 (en) * 2003-11-04 2005-05-05 Brandenburg Scott D. Heat sinkable package
US20050214974A1 (en) * 2004-03-26 2005-09-29 Field Dean L Integrated circuit having one or more conductive devices formed over a SAW and/or MEMS device
US20050250252A1 (en) * 2003-07-09 2005-11-10 Yuan Li Low warpage flip chip package solution-channel heat spreader
US20060081994A1 (en) * 2004-10-19 2006-04-20 Craig David M Assembly
JP2015159243A (en) * 2014-02-25 2015-09-03 京セラ株式会社 wiring board

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100259359B1 (en) * 1998-02-10 2000-06-15 김영환 Substrate for semiconductor device package, semiconductor device package using the same and manufacturing method thereof
JP3509532B2 (en) * 1998-02-17 2004-03-22 セイコーエプソン株式会社 Semiconductor device substrate, semiconductor device, method of manufacturing the same, and electronic device
US6014319A (en) * 1998-05-21 2000-01-11 International Business Machines Corporation Multi-part concurrently maintainable electronic circuit card assembly
JP3286917B2 (en) * 1999-05-06 2002-05-27 株式会社村田製作所 Electronic component packages and electronic components
EP1058307A1 (en) * 1999-06-03 2000-12-06 Alps Electric Co., Ltd. Electronic unit effectively utilizing circuit board surface
US6262479B1 (en) * 1999-10-05 2001-07-17 Pan Pacific Semiconductor Co., Ltd. Semiconductor packaging structure
US6506671B1 (en) * 2000-06-08 2003-01-14 Micron Technology, Inc. Ring positionable about a periphery of a contact pad, semiconductor device components including same, and methods for positioning the ring around a contact pad
US6472613B1 (en) * 2000-09-29 2002-10-29 American Superconductor Corporation Low-inductance connector for printed-circuit board
JP3888263B2 (en) * 2001-10-05 2007-02-28 株式会社村田製作所 Manufacturing method of multilayer ceramic electronic component
US6975035B2 (en) 2002-03-04 2005-12-13 Micron Technology, Inc. Method and apparatus for dielectric filling of flip chip on interposer assembly
JP2003316913A (en) * 2002-04-23 2003-11-07 Canon Inc Service providing method, information processing system, control program thereof and recording medium
FR2849346B1 (en) * 2002-12-20 2006-12-08 Thales Sa SURFACE MOUNTING HYPERFREQUENCY HOUSING AND CORRESPONDING MOUNTING WITH A MULTILAYER CIRCUIT.
KR100699488B1 (en) * 2005-07-19 2007-03-26 삼성전자주식회사 Packaging chip comprising inductor
US8628518B2 (en) 2005-12-30 2014-01-14 Intuitive Surgical Operations, Inc. Wireless force sensor on a distal portion of a surgical instrument and method
CN101483418B (en) * 2008-01-10 2011-08-17 佛山市顺德区顺达电脑厂有限公司 Filter wire laying and design method thereof
US8966747B2 (en) * 2011-05-11 2015-03-03 Vlt, Inc. Method of forming an electrical contact
US9402319B2 (en) 2011-05-11 2016-07-26 Vlt, Inc. Panel-molded electronic assemblies
US9666498B2 (en) * 2014-06-02 2017-05-30 Qorvo Us, Inc. Ring-frame power package
US10008473B2 (en) 2014-06-02 2018-06-26 Qorvo Us, Inc. Power package lid
US10199313B2 (en) * 2014-06-02 2019-02-05 Qorvo Us, Inc. Ring-frame power package
US9967984B1 (en) * 2015-01-14 2018-05-08 Vlt, Inc. Power adapter packaging
US9936580B1 (en) 2015-01-14 2018-04-03 Vlt, Inc. Method of forming an electrical connection to an electronic module
US10014189B2 (en) * 2015-06-02 2018-07-03 Ngk Spark Plug Co., Ltd. Ceramic package with brazing material near seal member
US10264664B1 (en) 2015-06-04 2019-04-16 Vlt, Inc. Method of electrically interconnecting circuit assemblies
CN105977215B (en) * 2016-06-30 2018-06-19 中国电子科技集团公司第十三研究所 Can parallel seam welding high-frequency high-speed ceramic leadless shell
CN109150134B (en) * 2018-08-24 2022-06-03 象朵创芯微电子(苏州)有限公司 Acoustic meter chip packaging method and acoustic meter device
US10629518B2 (en) * 2018-08-29 2020-04-21 Nxp Usa, Inc. Internally-shielded microelectronic packages and methods for the fabrication thereof
US11910530B2 (en) 2022-03-25 2024-02-20 Tactotek Oy Method for manufacturing electronics assembly and electronics assembly

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3520054A (en) * 1967-11-13 1970-07-14 Mitronics Inc Method of making multilevel metallized ceramic bodies for semiconductor packages
US3835531A (en) * 1971-06-10 1974-09-17 Int Computers Ltd Methods of forming circuit interconnections
US3872331A (en) * 1973-06-04 1975-03-18 Zenith Radio Corp Packaged surface wave selective circuit device and method of making the same
US4417392A (en) * 1980-05-15 1983-11-29 Cts Corporation Process of making multi-layer ceramic package
US4551747A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing for a transmission line environment and improved heat dissipation
US4608592A (en) * 1982-07-09 1986-08-26 Nec Corporation Semiconductor device provided with a package for a semiconductor element having a plurality of electrodes to be applied with substantially same voltage
US4658332A (en) * 1983-04-04 1987-04-14 Raytheon Company Compliant layer printed circuit board
US4847136A (en) * 1988-03-21 1989-07-11 Hughes Aircraft Company Thermal expansion mismatch forgivable printed wiring board for ceramic leadless chip carrier
US5135890A (en) * 1989-06-16 1992-08-04 General Electric Company Method of forming a hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
US5155905A (en) * 1991-05-03 1992-10-20 Ltv Aerospace And Defense Company Method and apparatus for attaching a circuit component to a printed circuit board
US5177326A (en) * 1991-10-21 1993-01-05 Gec-Marconi Electronic Systems Corp. Lead wire array for a leadless chip carrier
US5369551A (en) * 1993-11-08 1994-11-29 Sawtek, Inc. Surface mount stress relief interface system and method
US5418688A (en) * 1993-03-29 1995-05-23 Motorola, Inc. Cardlike electronic device
US5455385A (en) * 1993-06-28 1995-10-03 Harris Corporation Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses
US5461196A (en) * 1992-12-02 1995-10-24 Hughes Aircraft Company Low temperature co-fired ceramic (LTCC) high density interconnect package with circuitry within the cavity walls
US5477933A (en) * 1994-10-24 1995-12-26 At&T Corp. Electronic device interconnection techniques

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3520054A (en) * 1967-11-13 1970-07-14 Mitronics Inc Method of making multilevel metallized ceramic bodies for semiconductor packages
US3835531A (en) * 1971-06-10 1974-09-17 Int Computers Ltd Methods of forming circuit interconnections
US3872331A (en) * 1973-06-04 1975-03-18 Zenith Radio Corp Packaged surface wave selective circuit device and method of making the same
US4417392A (en) * 1980-05-15 1983-11-29 Cts Corporation Process of making multi-layer ceramic package
US4608592A (en) * 1982-07-09 1986-08-26 Nec Corporation Semiconductor device provided with a package for a semiconductor element having a plurality of electrodes to be applied with substantially same voltage
US4551747A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing for a transmission line environment and improved heat dissipation
US4658332A (en) * 1983-04-04 1987-04-14 Raytheon Company Compliant layer printed circuit board
US4847136A (en) * 1988-03-21 1989-07-11 Hughes Aircraft Company Thermal expansion mismatch forgivable printed wiring board for ceramic leadless chip carrier
US5135890A (en) * 1989-06-16 1992-08-04 General Electric Company Method of forming a hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
US5155905A (en) * 1991-05-03 1992-10-20 Ltv Aerospace And Defense Company Method and apparatus for attaching a circuit component to a printed circuit board
US5177326A (en) * 1991-10-21 1993-01-05 Gec-Marconi Electronic Systems Corp. Lead wire array for a leadless chip carrier
US5461196A (en) * 1992-12-02 1995-10-24 Hughes Aircraft Company Low temperature co-fired ceramic (LTCC) high density interconnect package with circuitry within the cavity walls
US5418688A (en) * 1993-03-29 1995-05-23 Motorola, Inc. Cardlike electronic device
US5455385A (en) * 1993-06-28 1995-10-03 Harris Corporation Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses
US5369551A (en) * 1993-11-08 1994-11-29 Sawtek, Inc. Surface mount stress relief interface system and method
US5477933A (en) * 1994-10-24 1995-12-26 At&T Corp. Electronic device interconnection techniques

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Low Cost Surface Mount Packaging for SAWs , J. Gore, B. Horine, J. Phillips, R. Hoffman and J. Dodge, Oct. 1992, 1992 Ultrasonic Symposium Proceedings, vol. 1 of 2, pp. 129 138. *
Low-Cost Surface Mount Packaging for SAWs, J. Gore, B. Horine, J. Phillips, R. Hoffman and J. Dodge, Oct. 1992, 1992 Ultrasonic Symposium Proceedings, vol. 1 of 2, pp. 129-138.
Mulitlayer Ceramics Catalog, Kyocera Corporation, Corporate Semiconductor Parts Division, 1992. *
Surface Moung Package Catalog, Kyocera Corporation, Corporate Semiconductor Parts Division, 1991. *

Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6487087B1 (en) * 1999-01-28 2002-11-26 Bookham Technology Plc Optical interface arrangement
US6703703B2 (en) * 2000-01-12 2004-03-09 International Rectifier Corporation Low cost power semiconductor module without substrate
US20040026778A1 (en) * 2000-01-12 2004-02-12 International Rectifier Corporation Low cost power semiconductor module without substate
US7545033B2 (en) 2000-01-12 2009-06-09 International Rectifier Corporation Low cost power semiconductor module without substrate
US20060261463A1 (en) * 2000-01-12 2006-11-23 International Rectifier Corporation Low cost power semiconductor module without substrate
US7122890B2 (en) 2000-01-12 2006-10-17 International Rectifier Corporation Low cost power semiconductor module without substrate
US6717241B1 (en) * 2000-08-31 2004-04-06 Micron Technology, Inc. Magnetic shielding for integrated circuits
US20030122235A1 (en) * 2001-08-22 2003-07-03 Taiwan Semiconductor Manufacturing Company Seal ring structure for radio frequency integrated circuits
USRE41668E1 (en) * 2001-08-22 2010-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structure for radio frequency integrated circuits
US6537849B1 (en) 2001-08-22 2003-03-25 Taiwan Semiconductor Manufacturing Company Seal ring structure for radio frequency integrated circuits
US6967392B2 (en) 2001-08-22 2005-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structure for radio frequency integrated circuits
US20030138986A1 (en) * 2001-09-13 2003-07-24 Mike Bruner Microelectronic mechanical system and methods
US6930364B2 (en) 2001-09-13 2005-08-16 Silicon Light Machines Corporation Microelectronic mechanical system and methods
US20040053434A1 (en) * 2001-09-13 2004-03-18 Silicon Light Machines Microelectronic mechanical system and methods
US20040082100A1 (en) * 2001-11-02 2004-04-29 Norihito Tsukahara Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component
US7176055B2 (en) * 2001-11-02 2007-02-13 Matsushita Electric Industrial Co., Ltd. Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component
US20070200217A1 (en) * 2001-11-02 2007-08-30 Norihito Tsukahara Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component
US6943063B2 (en) 2001-11-20 2005-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. RF seal ring structure
US20050248025A1 (en) * 2001-11-20 2005-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. RF seal ring structure
US7265438B2 (en) 2001-11-20 2007-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. RF seal ring structure
US20040217477A1 (en) * 2001-11-20 2004-11-04 Taiwan Semiconductor Manufacturing Company RF seal ring structure
US20030222332A1 (en) * 2002-05-29 2003-12-04 Intel Corporation High-power lga socket
US6870251B2 (en) * 2002-05-29 2005-03-22 Intel Corporation High-power LGA socket
US7402182B2 (en) 2002-05-29 2008-07-22 Intel Corporation High-power LGA socket
US20050164529A1 (en) * 2002-05-29 2005-07-28 Intel Corporation High-power LGA socket
US6877209B1 (en) 2002-08-28 2005-04-12 Silicon Light Machines, Inc. Method for sealing an active area of a surface acoustic wave device on a wafer
US6846423B1 (en) 2002-08-28 2005-01-25 Silicon Light Machines Corporation Wafer-level seal for non-silicon-based devices
US20040195683A1 (en) * 2003-04-03 2004-10-07 Fujitsu Media Devices Limited Compact electronic device and package used therefor
US20040238928A1 (en) * 2003-05-30 2004-12-02 Naoyuki Mishima Electronic component and package
US6864424B2 (en) * 2003-05-30 2005-03-08 Fujitsu Media Devices Limited Electronic component and package
US20050250252A1 (en) * 2003-07-09 2005-11-10 Yuan Li Low warpage flip chip package solution-channel heat spreader
US20050093181A1 (en) * 2003-11-04 2005-05-05 Brandenburg Scott D. Heat sinkable package
US20050214974A1 (en) * 2004-03-26 2005-09-29 Field Dean L Integrated circuit having one or more conductive devices formed over a SAW and/or MEMS device
US7750420B2 (en) 2004-03-26 2010-07-06 Cypress Semiconductor Corporation Integrated circuit having one or more conductive devices formed over a SAW and/or MEMS device
US7262498B2 (en) * 2004-10-19 2007-08-28 Hewlett-Packard Development Company, L.P. Assembly with a ring and bonding pads formed of a same material on a substrate
US20060081994A1 (en) * 2004-10-19 2006-04-20 Craig David M Assembly
JP2015159243A (en) * 2014-02-25 2015-09-03 京セラ株式会社 wiring board

Also Published As

Publication number Publication date
US5864092A (en) 1999-01-26

Similar Documents

Publication Publication Date Title
US6105226A (en) Leadless ceramic chip carrier crosstalk suppression method
JP3222072B2 (en) Demultiplexer package
US5294751A (en) High frequency signal transmission line structure having shielding conductor unit
US5602421A (en) Microwave monolithic integrated circuit package with improved RF ports
US5162822A (en) Saw filter chip mounted on a substrate with shielded conductors on opposite surfaces
US6815869B2 (en) Surface acoustic wave device
US5225709A (en) Package having a structure for stabilizing and/or impedance-matching a semiconductor IC device accommodated therein
GB2431512A (en) Piezoelectric device
US6897740B2 (en) Duplexer and composite module having a package with an electroconductive lid electrically connected to a shield
JP3500335B2 (en) High frequency circuit device
US20020109561A1 (en) Saw filter duplexer device wtih optimal location of a phase matching line pattern and wire bonding pads
JP3493301B2 (en) High frequency input / output terminals and high frequency semiconductor element storage package
US5523621A (en) Semiconductor device having a multilayer ceramic wiring substrate
US6140698A (en) Package for microwave and mm-wave integrated circuits
JP2603310B2 (en) High frequency integrated circuit package
JPH0864983A (en) Shield case
JP2002359340A (en) Multilayer circuit board
JPH02179018A (en) Surface mount type surface acoustic wave device
JP2006203542A (en) Branching filter
JP2853074B2 (en) Mounting structure of feedthrough capacitor
JPH04183001A (en) Package for microwave ic
JPH0818001A (en) Ic package
JP4404460B2 (en) Multi-cavity wiring board, wiring board, multi-cavity semiconductor element storage package and semiconductor element storage package
JPH0314295A (en) High-frequency circuit container
JPS6037753A (en) Package for semiconductor device

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: TRIQUINT, INC., OREGON

Free format text: CHANGE OF NAME;ASSIGNOR:SAWTEK INC.;REEL/FRAME:032301/0792

Effective date: 20060926

AS Assignment

Owner name: SAWTEK, INC., OREGON

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GORE, JOHN G.;TOLAR, NEAL J.;BROWN, ROY B.;AND OTHERS;SIGNING DATES FROM 19960515 TO 19960520;REEL/FRAME:039058/0713