US6074886A - Electrical characterization of an insulating layer covering a conducting or semiconducting substrate - Google Patents

Electrical characterization of an insulating layer covering a conducting or semiconducting substrate Download PDF

Info

Publication number
US6074886A
US6074886A US09/156,127 US15612798A US6074886A US 6074886 A US6074886 A US 6074886A US 15612798 A US15612798 A US 15612798A US 6074886 A US6074886 A US 6074886A
Authority
US
United States
Prior art keywords
insulating layer
electrical
area
substrate
major defect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/156,127
Other languages
English (en)
Inventor
Stephane Henaux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE reassignment COMMISSARIAT A L'ENERGIE ATOMIQUE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HENAUX, STEPHANE
Application granted granted Critical
Publication of US6074886A publication Critical patent/US6074886A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
    • G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
    • G01R31/1263—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
    • G01R31/129—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation of components or parts made of semiconducting materials; of LV components or parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • This invention relates to a process for electrical characterization of an insulating layer covering a conducting or semiconducting substrate. It also relates to a device for embodiment of this characterization process.
  • grid oxide is an essential element in MOS (Metal Oxide Semiconductor) integrated circuits. The quality of this oxide depends very much on the initial semiconducting substrate.
  • One known process for achieving this result is to deposit an oxide layer (subsequently called a thin oxide) of the same type as the required grid oxide on one entire surface (or the front surface) of a control substrate and electrically testing this thin oxide between a front contact and a back contact.
  • the back contact is normally a conducting metal plate located on the back surface of the control substrate. Manufacturing of the front contact must not degrade the thin oxide deposited on the front surface of the substrate. This front contact has a given contact area that defines the oxide portion being tested.
  • FIG. 1 illustrates the principle used applied to a silicon substrate 1 covered by a silica layer 2 on its front surface 3.
  • a metal plate 5 connected to the ground.
  • the front contact, with the free surface of thin oxide 2, is made by a mercury electrode 6 that applies a voltage V with respect to the ground.
  • the simplest test consists of detecting major defects, in other words local short circuits in the thin oxide. For example, these short circuits may be due to a silicon excroissance projecting from the substrate.
  • the test takes place by moving the mercury electrode across the free surface of the thin oxide 2. If the front contact is placed on an oxide portion containing a major defect, a leakage current I is measured even at low values of the voltage V.
  • V bd is called the breakdown voltage of the thin oxide in the oxide portion being tested.
  • the insulating layer was placed on a semiconducting material forming a substrate, and the back contact comes into contact with the back surface of this substrate.
  • This test proves to be impossible to carry out in some cases, for example an SOI (Silicon On Insulator) substrate as shown in FIG. 2.
  • This substrate comprises a silicon ground 10 forming the initial substrate and with a back surface 11.
  • An oxide layer 12, called the buried oxide layer was grown on the opposite surface and a silicon layer 13 was then added.
  • This SOI substrate formed in this way is then covered by a thin oxide layer 14, that has to be tested.
  • this type of structure cannot be tested in the same way as before, since the buried oxide 12 opposes current passing between the thin oxide 14 and its back surface 11 even if there is a defect in the thin oxide portion being tested.
  • a first method would consist of keeping the thin oxide over the entire surface of the substrate. In this case, a high current I would only be measured if there is a defect in the thin oxide in each of the two contacted oxide portions. A defect present in one of the two portions would not be detected if the other oxide portion was intact.
  • a second method would consist of eliminating the thin oxide locally so as to place one of the two front contacts on the silicon film. This represents a technological step that can degrade the thin oxide to be tested. Furthermore, it is very difficult to optically distinguish between areas covered with thin oxide and areas not covered, since the thin oxide is practically transparent. Therefore it would be difficult to position the contacts.
  • this invention proposes a solution based on the following principle. Firstly, a major defect is created artificially in the insulating layer to be tested, forming a short circuit under one of the contacts of the measurement device. An electrical conduction test is then carried out between the contact placed on the major defect and another test contact placed on the portion of the insulating layer to be tested.
  • the purpose of the invention is a process for characterization of an insulating layer, the first surface of which covers a conducting or semiconducting surface of the substrate, the second surface of the insulating layer being electrically accessible, the characterization consisting of verifying the quality of electrical insulation presented by at least one area of the insulating layer by means of an electrical test, characterized in that it comprises the following steps:
  • the major defect may be obtained by application of an electrical voltage with a sufficiently high value to cause breakdown of the insulating layer.
  • This electrical voltage may be applied by means of two electrodes put into electrical contact with the second surface of the insulating layer, thus creating two major defects in the insulating layer, one or both of these major defects being used for application of the electrical test.
  • the major defect may also be obtained mechanically, by crossing through the insulating layer.
  • the major defect may be created in an annular shaped area centered on the area of the insulating layer to be tested.
  • the electrical test consists of applying an electrical voltage between the said electrodes and then recording the current, if any, passing between the said electrodes.
  • the electrical voltage applied between the electrodes can then be a voltage ramp.
  • this semiconducting substrate may be a Silicon-On-Insulator substrate, in which the buried layer is a silicon oxide layer and the surface insulating layer is also a silicon oxide layer.
  • the silicon subjacent to the surface oxide layer is maintained under strong illumination during application of the electrical test in order to facilitate the generation of minority carriers.
  • Another way of favoring generation of minority carriers is to increase the temperature of the silicon subjacent to the surface oxygen layer so that it exceeds the ambient temperature while the electrical test is being carried out.
  • Another purpose of the invention is a device for characterization of an insulating layer, in which the first surface covers a conducting or semiconducting surface of a substrate, the second surface of the insulating layer being electrically accessible, the characterization consisting of verifying the quality of the electrical insulation presented by at least one area of the insulating layer by means of an electrical test, characterized in that it comprises:
  • the device may comprise at least three electrodes that can be put into contact with the second surface of the insulating layer, two of these electrodes being used to apply a breakdown voltage to the insulating layer in order to create two major defects, the third electrode being used to apply the said electrical test, with at least one of the other two electrodes.
  • the means of creating at least one major defect may also be mechanical means operating through the insulating layer.
  • the electrode used to jointly apply the breakdown voltage and the electrical test may have an annular contact area, the electrode that can be put into contact with the area to be tested being centered on the annular contact area.
  • the electrical test application electrodes may be mercury electrodes.
  • the means of applying the electrical test output an electrical signal in the shape of a ramp between the major defect and the said area to be tested.
  • the means of applying the electrical test comprise means capable of accessing the measurement of the current circulating between electrodes used for application of the electrical test.
  • FIG. 1 illustrates a process for electrical characterization of a silica layer covering a silicon substrate according to known art
  • FIG. 2 illustrates a Silicon-On-Insulator substrate covered by a silica oxide layer
  • FIG. 3 illustrates the electrical characterization process according to this invention applied to a substrate of the type shown in FIG. 2,
  • FIGS. 4, 5 and 6 represent current-voltage curves
  • FIG. 7 shows an electrode layout for a characterization device according to this invention
  • FIG. 8 shows details of an electrical contact between an electrode and a variable thickness insulating layer.
  • FIG. 3 illustrates the process according to this invention in the case of the substrate shown in FIG. 2.
  • the characterization device used comprises a mercury probe with three or more contacts.
  • the back surface 11 is grounded by means of a plate electrode 20.
  • the thin oxide surface opposite the surface that is in contact with the silicon layer 13 and which has a thickness of between 3 and 1000 nm, is put into contact with three mercury electrodes 21, 22 and 23.
  • the first step is to make the major defects in the thin oxide 14 by electrical breakdown. This is done by grounding electrode 21, leaving electrode 22 at a floating potential and applying a high voltage V 3 , for example -100V, to electrode 23. Oxide portions 31 and 33, each containing a major defect, are then obtained in the thin oxide facing electrodes 21 and 23 respectively. The current I 3 circulating between electrodes 21 and 23 through the silicon layer 13 is measured, to ensure that these major defects have actually been created. For example, current I 3 will exceed 1 mA.
  • the electrical test can then be put into application for the thin oxide portion 32 facing electrode 22. This is done by applying a voltage ramp V 2 to electrode 22, electrode 23 being grounded, plate electrode 20 and electrode 21 also being grounded.
  • the current I 2 passing through electrode 22 increases strongly even for very small values of V 2 . If there is no major defect, and there is simply a minor defect or no defect at all, the current I 2 is firstly very low and only starts to increase suddenly above a certain value of V 2 , called the breakdown voltage V bd .
  • the front surface of the substrate is strongly illuminated at all times while the process is in use.
  • the purpose of this illumination is to maximize the current in major defects which can be simply described as Schottky mercury-silicon junctions.
  • Schottky mercury-silicon junctions When this type of junction is polarized directly, it does not oppose current passing. However, when it is inversely polarized, it only allows a low current called the leakage current to pass. Light facilitates the generation of minority carriers and maximizes the leakage current in the inverted junction(s).
  • Another solution for maximizing the current in major defects consists of increasing the temperature in major defects under electrodes 21 and 23.
  • the substrate on the front surface can be illuminated without any difficulty if the substrate support, in which vertical mercury channels are perforated for electrodes 21, 22 and 23, is made of a transparent material.
  • the illumination must be sufficiently strong to significantly increase the leakage current.
  • a 100 W halogen lamp (white) may be used focused on less than 1 cm 2 .
  • FIGS. 4, 5 and 6 give examples of the results obtained on different SOI substrates. These diagrams show the current I 2 in nA in the ordinate, and the voltage V 2 in volts in the abscissa.
  • FIG. 4 presents the results obtained for a 15 nm thick thin oxide covering an SOI substrate, the subjacent silicon having n type doping at 10 17 atoms/cm 3 .
  • Curve 41 is typical of intact sites.
  • Curve 42 shows a site with a major defect.
  • FIG. 5 presents the results obtained for a 7.5 nm thick thin oxide covering an SOI substrate, the subjacent silicon not being doped.
  • Curve 51 is typical of intact sites.
  • Curves 52 and 53 correspond to sites with a major defect.
  • FIG. 6 presents the results obtained for a 15 nm thick thin oxide covering an SOI substrate, the subjacent silicon not being doped.
  • Curve 61 is typical of intact sites.
  • Curves 62 and 63 correspond to sites with a major defect.
  • the process according to the invention is applicable to doped or undoped SOI substrates.
  • Doped substrates have the highest currents on defective oxide portions since the resistance of the silicon film subjacent to the oxide is lower.
  • the process according to the invention may be extended to characterization devices (or probes) with more than three mercury electrodes.
  • Each additional electrode can be used to test an additional oxide portion on each site.
  • a probe with four mercury electrodes can be used to test the thin oxide in two portions. Furthermore if these two contacts have different surfaces, defect studies can be carried out as a function of the tested surface.
  • FIG. 7 shows this type of layout. There is a central test electrode 71, a first electrode 72 to obtain a first major defect by breakdown and a second electrode 73 to obtain a second major defect by breakdown, all laid out concentrically.
  • the process according to this invention may be implemented using solid conducting contacts (metal pads, conducting polymer deposits) obtained by evaporation, deposition and etching or by any other method that does not degrade the thin oxide to be tested, depending on the case.
  • solid conducting contacts metal pads, conducting polymer deposits
  • the cost and time to make these conducting contacts may be an obstacle to their use.
  • the insulating layer to be characterized may have a free surface or may be covered by a structure providing electrical access to this layer as shown in FIG. 8.
  • the substrate 80 comprises a conducting or semiconducting part 81 covered by an insulating layer 82 with thickness variations.
  • the insulating layer 82 may be a silicon oxide layer with relatively thin portions 83 separated by thicker portions of LOCOS type oxide 84.
  • Conducting pads 85 are placed on portions 83 and between portions 84.
  • the electrodes in the characterization device for example the mercury electrode 22, can then maintain electrical contact with the thin portions 83 of the oxide layer through conducting pads 85.
  • the invention is applicable to substrates other than SOI substrates, for example SiC on insulator substrates.
  • This invention can be used with various manufacturing variants.
  • the same electrode can be used to form several major defects, so that a higher current can be used.
  • the electrical test may consist of applying an AC voltage to the area to be tested, and starting from the measurement of the circulating AC current, determining the impedance of the insulating layer (for example the silicon oxide layer) and of the subjacent material (for example the silicon) by analyzing its phase and amplitude.
  • the oxide quality may be expressed in the form of a measurement of the resistance and capacitance, conductance and capacitance, inductance and resistance, inductance and impedance.
  • the electrical test can be carried out by measuring the current passing between the electrodes.
  • the voltage may be measured instead of the current.
  • the voltage may be servocontrolled such that the current obtained remains constant.
  • the time after which the oxide breaks down is recorded, and the product of the current and the time is calculated to determine Q bd which is the charge that passed through the oxide during this time.
  • the value Of Q bd can be used to characterize the oxide.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
US09/156,127 1997-10-09 1998-09-17 Electrical characterization of an insulating layer covering a conducting or semiconducting substrate Expired - Lifetime US6074886A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9712604 1997-10-09
FR9712604A FR2769753B1 (fr) 1997-10-09 1997-10-09 Caracterisation electrique d'une couche isolante recouvrant un substrat conducteur ou semiconducteur

Publications (1)

Publication Number Publication Date
US6074886A true US6074886A (en) 2000-06-13

Family

ID=9512015

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/156,127 Expired - Lifetime US6074886A (en) 1997-10-09 1998-09-17 Electrical characterization of an insulating layer covering a conducting or semiconducting substrate

Country Status (3)

Country Link
US (1) US6074886A (fr)
EP (1) EP0908944B1 (fr)
FR (1) FR2769753B1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6458634B1 (en) * 2001-04-18 2002-10-01 International Business Machines Corporation Reduction of induced charge in SOI devices during focused ion beam processing
US6528335B2 (en) * 2001-02-14 2003-03-04 International Business Machines Corporation Electrical method for assessing yield-limiting asperities in silicon-on-insulator wafers
US7011980B1 (en) * 2005-05-09 2006-03-14 International Business Machines Corporation Method and structures for measuring gate tunneling leakage parameters of field effect transistors
WO2009133501A1 (fr) * 2008-04-29 2009-11-05 Philips Intellectual Property & Standards Gmbh Dispositif de diode électroluminescente organique (delo) à couche de limitation de courant
WO2012116119A1 (fr) * 2011-02-22 2012-08-30 Qualcomm Incorporated Circuit et procédé d'essai de matériau isolant
CN113702450A (zh) * 2020-05-22 2021-11-26 新疆金风科技股份有限公司 磁极覆层缺陷的检测方法及装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008099316A1 (fr) 2007-02-13 2008-08-21 Philips Intellectual Property & Standards Gmbh Appareil de traitement de défaut

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63142826A (ja) * 1986-12-05 1988-06-15 Tokyo Electron Ltd プロ−ブカ−ド
JPH02275364A (ja) * 1989-04-15 1990-11-09 Matsushita Electric Works Ltd 抵抗測定装置
EP0581703A1 (fr) * 1992-07-30 1994-02-02 STMicroelectronics S.A. Procédé de test de la résistance par carré de couches diffusées
WO1996023319A2 (fr) * 1995-01-20 1996-08-01 Vlsi Technology, Inc. Prediction de la fiabilite de couches minces d'oxyde au niveau de la plaquette
US5907764A (en) * 1995-11-13 1999-05-25 Advanced Micro Devices, Inc. In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers
US6014034A (en) * 1996-10-24 2000-01-11 Texas Instruments Incorporated Method for testing semiconductor thin gate oxide

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63142826A (ja) * 1986-12-05 1988-06-15 Tokyo Electron Ltd プロ−ブカ−ド
JPH02275364A (ja) * 1989-04-15 1990-11-09 Matsushita Electric Works Ltd 抵抗測定装置
EP0581703A1 (fr) * 1992-07-30 1994-02-02 STMicroelectronics S.A. Procédé de test de la résistance par carré de couches diffusées
WO1996023319A2 (fr) * 1995-01-20 1996-08-01 Vlsi Technology, Inc. Prediction de la fiabilite de couches minces d'oxyde au niveau de la plaquette
US5907764A (en) * 1995-11-13 1999-05-25 Advanced Micro Devices, Inc. In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers
US6014034A (en) * 1996-10-24 2000-01-11 Texas Instruments Incorporated Method for testing semiconductor thin gate oxide

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Characterizing Weak Spots in Dielectric Layers, Sep. 1991, vol. 34, No. 4B, p. 98 99. *
IBM Technical Disclosure Bulletin, Characterizing Weak Spots in Dielectric Layers, Sep. 1991, vol. 34, No. 4B, p. 98-99.
Wang H et al, An Optimized Gate Oxide Breakdown Test By Activating Oxide Traps at Low Fields, Dec. 13, 1992, pp. 143 146. *
Wang H et al, An Optimized Gate Oxide Breakdown Test By Activating Oxide Traps at Low Fields, Dec. 13, 1992, pp. 143-146.

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528335B2 (en) * 2001-02-14 2003-03-04 International Business Machines Corporation Electrical method for assessing yield-limiting asperities in silicon-on-insulator wafers
US6458634B1 (en) * 2001-04-18 2002-10-01 International Business Machines Corporation Reduction of induced charge in SOI devices during focused ion beam processing
US7011980B1 (en) * 2005-05-09 2006-03-14 International Business Machines Corporation Method and structures for measuring gate tunneling leakage parameters of field effect transistors
WO2009133501A1 (fr) * 2008-04-29 2009-11-05 Philips Intellectual Property & Standards Gmbh Dispositif de diode électroluminescente organique (delo) à couche de limitation de courant
WO2012116119A1 (fr) * 2011-02-22 2012-08-30 Qualcomm Incorporated Circuit et procédé d'essai de matériau isolant
CN113702450A (zh) * 2020-05-22 2021-11-26 新疆金风科技股份有限公司 磁极覆层缺陷的检测方法及装置

Also Published As

Publication number Publication date
EP0908944B1 (fr) 2011-11-30
FR2769753A1 (fr) 1999-04-16
FR2769753B1 (fr) 1999-12-03
EP0908944A1 (fr) 1999-04-14

Similar Documents

Publication Publication Date Title
US6246075B1 (en) Test structures for monitoring gate oxide defect densities and the plasma antenna effect
US6617180B1 (en) Test structure for detecting bridging of DRAM capacitors
US5972725A (en) Device analysis for face down chip
US5786231A (en) Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer
US6074886A (en) Electrical characterization of an insulating layer covering a conducting or semiconducting substrate
US5391502A (en) Per-wafer method for globally stressing gate oxide during device fabrication
US6991948B2 (en) Method of electrical characterization of a silicon-on-insulator (SOI) wafer
US6528335B2 (en) Electrical method for assessing yield-limiting asperities in silicon-on-insulator wafers
JP2965176B2 (ja) 静電チャックの過渡特性評価方法
US4520312A (en) Method for determining the integrity of passivant coverage over rectifying junctions in semiconductor devices
JP2000068345A (ja) 半導体装置のコンタクト開口検査方法
JP2001305194A (ja) 半導体装置およびそのショート欠陥箇所の検出方法
US7106049B2 (en) Zero-temperature-gradient zero-bias thermally stimulated current technique to characterize defects in semiconductors or insulators
EP1610373A2 (fr) Méthode et dispositif pour détermination de la durée de vie de production des porteurs
US20080290889A1 (en) Method of destructive testing the dielectric layer of a semiconductor wafer or sample
Schroder et al. Frequency domain lifetime characterization
KR101515719B1 (ko) 프로브 스테이션
Kern et al. New methods for detecting structural defects in glass passivation films
CN117476604A (zh) 一种半导体测试结构及测试方法
US7135868B1 (en) Method and apparatus for testing gate oxide with fuse
Benstetter et al. A review of ULSI failure analysis techniques for DRAMs 1. Defect localization and verification
JP2005331241A (ja) 導電性試料の評価方法及び導電性試料の評価装置
Comizzoli CORONA DISCHARGE APPLICATIONS IN THE SEMICONDUCTOR INDUSTRY
JPH01140638A (ja) 半導体装置
Henaux et al. Gate oxide integrity testing on SOI wafers without test structure fabrication

Legal Events

Date Code Title Description
AS Assignment

Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE, FRANCE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HENAUX, STEPHANE;REEL/FRAME:009469/0495

Effective date: 19980904

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 12