US5504925A - Apparatus and method for implementing interrupts in pipelined processors - Google Patents

Apparatus and method for implementing interrupts in pipelined processors Download PDF

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Publication number
US5504925A
US5504925A US08/348,786 US34878694A US5504925A US 5504925 A US5504925 A US 5504925A US 34878694 A US34878694 A US 34878694A US 5504925 A US5504925 A US 5504925A
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operand
operand address
circuit
storage elements
instruction
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Paul V. Jeffs
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Intergraph Corp
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Intergraph Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Definitions

  • pipelined processors were constructed wherein several instructions could be in some phase of execution at the same time.
  • pipelined instructions may modify the process state in an order different from that defined by the sequential architectural model.
  • the process state usually does not correspond to the state that would exist if all instructions executed sequentially. That makes restarting the process very difficult, if not impossible.
  • an instruction can modify the process state only when all previously issued instructions are known to be free of exception conditions.
  • an N-stage result shift register is used to control instruction execution, where N represents the maximum number of clock periods that an instruction may require to complete.
  • An instruction that takes i clock periods to execute places control information in stage i of the result shift register at the time it issues. During each clock period, the control information is shifted down one stage towards stage one. When the control information reaches stage one, it is used during the next clock period to control the hardware so that the result data generated by the instruction is stored at that time in the correct result register.
  • both the result data and any exception conditions are stored in the reorder buffer.
  • the entry at the head of the reorder buffer contains valid results (its corresponding instruction has completed)
  • the exception data is checked. If no exception conditions are detected, the result data is written into the registers. If an exception is detected, instruction issuing stops, and all further writes into the register file are inhibited.
  • a third disclosed method attempts to overcome the disadvantages of both the result shift register method and the reorder buffer method.
  • computed results are placed in a working register file, but enough state information is stored in a history buffer so that a precise state can be restored if an exception occurs.
  • the history buffer is organized and functions in a manner very similar to the reorder buffer.
  • a history buffer entry is loaded with control information, and the current value of the destination register (to be overwritten by the issuing instruction) is also read from the register file and written into the buffer entry.
  • the result data generated by the instruction are written directly into the register file when an instruction completes. Exception data are written into the history buffer.
  • the history buffer contains an entry at the head that is known to have finished without exceptions, the history buffer entry is no longer needed and that buffer location can be reused.
  • An instruction executing circuit performs a function designated by the first instruction on the operand data output from the floating point register and generates result data.
  • the instruction executing circuit includes an exception circuit for generating exception data indicating whether an exception occurred when the function was performed.
  • all instructions except a floating point divide instruction may be executed in seven clock cycles or less.
  • the floating point divide instruction takes, e.g., 30 clock cycles to execute.
  • the B operand address for the floating point divide instruction is stored in shift register stage 80H and maintained there by delay element 81 until seven clock cycles remain in the execution cycle. Thereafter, the B operand address is shifted into shift register stage 80G, and shifting proceeds as with the other B operand addresses.
  • the B operand address of the instruction together with its corresponding control information is shifted one shift register stage per clock cycle until they are shifted into shift register stages 80A and 98A.
  • storage control circuit 104 evaluates the control information and communicates the B operand address to the SBIN terminal of floating point register 30. Additionally, the result data for the first instruction should be communicated to the RIN terminal of floating point register via communication path 62.
  • a signal is then provided on communication path 112 to the SCTL terminal of floating point register 30 for storing the result data at the location addressed by the B operand address on communication path 111.
  • exception data appears on communication path 66 and is communicated to storage control circuit 104 and to the shift register stage corresponding to the B operand address of the instruction.
  • storage control circuit 104 issues a signal on communication path 112 to SCTL terminal of floating point register 30 for inhibiting the storing of the result data in floating point register 30.
  • the operand queue address stored in shift register stage 98A is communicated via communication path 136 to operand queue 114 for addressing the A operand corresponding to the instruction which generated the exception.
  • the addressed A operand (and optional program counter value) is communicated to trap queue 118 through communication path 150 wherein it is stored at the address generated by M counter 138. If this is the first time an exception is generated, then M count initialize circuit 142 initializes M counter 138 before the A operand is stored in trap queue 118. Otherwise the M counter is incremented before the A operand is stored in trap queue 118.
  • storage control circuit 104 evaluates the control information and communicates the load/store address through communication path 115 to the SLSIN terminal of floating point register 30. If a load operation was specified, the memory data should be communicated to the MDIN terminal of floating point register 30 via communication path 42. A signal is then provided on communication path 113 to the SLSCTL terminal of floating point register 30 for storing the memory data at the location addressed by the load/store address on communication path 113. If a store operation was specified, a signal is then provided on communication path 113 to the SLSCTL terminal of floating point register 30 for providing the addressed memory data on communication path 46.
  • Load/store instructions typically do not require saving the old value designated. That is why they are allowed to execute concurrently with instructions that use functional units 50. However, if for some reason a load/store instruction is to be aborted, control information to that effect is stored in shift register stage 99A or 99B through communication path 101. When the control information is shifted into shift register stage 99A, storage control circuit 104 issues a signal on communication path 113 to the LSCTL terminal of floating point register 30 for inhibiting the load/store operation.
  • K count initialize circuit 154 initializes K counter 146, and the stored A operands are read from trap register 118, communicated through communication paths 184 and 192 to the RIN terminal of floating point register 30, and restored therein.
  • the instructions which caused the exception conditions then may be reexecuted using the program counter value saved in either trap register 118 or the CPU or simulated with the appropriate software to update floating point register 30 to correspond with a sequential architectural model.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
US08/348,786 1992-09-18 1994-12-02 Apparatus and method for implementing interrupts in pipelined processors Expired - Fee Related US5504925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/348,786 US5504925A (en) 1992-09-18 1994-12-02 Apparatus and method for implementing interrupts in pipelined processors

Applications Claiming Priority (2)

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US94721592A 1992-09-18 1992-09-18
US08/348,786 US5504925A (en) 1992-09-18 1994-12-02 Apparatus and method for implementing interrupts in pipelined processors

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US94721592A Continuation 1992-09-18 1992-09-18

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EP (1) EP0588252B1 (de)
JP (1) JP3556246B2 (de)
CA (1) CA2105806C (de)
DE (1) DE69318914T2 (de)

Cited By (13)

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US5649088A (en) * 1994-12-27 1997-07-15 Lucent Technologies Inc. System and method for recording sufficient data from parallel execution stages in a central processing unit for complete fault recovery
US5778220A (en) * 1996-11-18 1998-07-07 Intel Corporation Method and apparatus for disabling interrupts in a highly pipelined processor
US6006033A (en) * 1994-08-15 1999-12-21 International Business Machines Corporation Method and system for reordering the instructions of a computer program to optimize its execution
US6108767A (en) * 1998-07-24 2000-08-22 Sun Microsystems, Inc. Method, apparatus and computer program product for selecting a predictor to minimize exception traps from a top-of-stack cache
US6609190B1 (en) * 2000-01-06 2003-08-19 International Business Machines Corporation Microprocessor with primary and secondary issue queue
US20030212915A1 (en) * 2002-05-09 2003-11-13 International Business Machines Corporation Register file write power reduction mechanism
US6697939B1 (en) * 2000-01-06 2004-02-24 International Business Machines Corporation Basic block cache microprocessor with instruction history information
US20110153983A1 (en) * 2009-12-22 2011-06-23 Hughes Christopher J Gathering and Scattering Multiple Data Elements
US8972697B2 (en) 2012-06-02 2015-03-03 Intel Corporation Gather using index array and finite state machine
US9626333B2 (en) 2012-06-02 2017-04-18 Intel Corporation Scatter using index array and finite state machine
US10042814B2 (en) 2007-12-31 2018-08-07 Intel Corporation System and method for using a mask register to track progress of gathering and scattering elements between data registers and memory
US10114651B2 (en) 2009-12-22 2018-10-30 Intel Corporation Gathering and scattering multiple data elements
US10387151B2 (en) 2007-12-31 2019-08-20 Intel Corporation Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks

Families Citing this family (4)

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SG48907A1 (en) * 1993-12-01 1998-05-18 Intel Corp Exception handling in a processor that performs speculative out-of-order instruction execution
US5893930A (en) * 1996-07-12 1999-04-13 International Business Machines Corporation Predictive translation of a data address utilizing sets of associative entries stored consecutively in a translation lookaside buffer
US6216222B1 (en) 1998-05-14 2001-04-10 Arm Limited Handling exceptions in a pipelined data processing apparatus
JP2006039874A (ja) * 2004-07-26 2006-02-09 Fujitsu Ltd 情報処理装置

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JP2858140B2 (ja) * 1988-10-19 1999-02-17 アポロ・コンピューター・インコーポレーテッド パイプラインプロセッサ装置および方法

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US4484259A (en) * 1980-02-13 1984-11-20 Intel Corporation Fraction bus for use in a numeric data processor
US4760519A (en) * 1983-07-11 1988-07-26 Prime Computer, Inc. Data processing apparatus and method employing collision detection and prediction
US5201057A (en) * 1987-01-22 1993-04-06 Uht Augustus K System for extracting low level concurrency from serial instruction streams
US5072364A (en) * 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel

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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6006033A (en) * 1994-08-15 1999-12-21 International Business Machines Corporation Method and system for reordering the instructions of a computer program to optimize its execution
US5649088A (en) * 1994-12-27 1997-07-15 Lucent Technologies Inc. System and method for recording sufficient data from parallel execution stages in a central processing unit for complete fault recovery
US5778220A (en) * 1996-11-18 1998-07-07 Intel Corporation Method and apparatus for disabling interrupts in a highly pipelined processor
US6108767A (en) * 1998-07-24 2000-08-22 Sun Microsystems, Inc. Method, apparatus and computer program product for selecting a predictor to minimize exception traps from a top-of-stack cache
US6609190B1 (en) * 2000-01-06 2003-08-19 International Business Machines Corporation Microprocessor with primary and secondary issue queue
US6697939B1 (en) * 2000-01-06 2004-02-24 International Business Machines Corporation Basic block cache microprocessor with instruction history information
US20030212915A1 (en) * 2002-05-09 2003-11-13 International Business Machines Corporation Register file write power reduction mechanism
US7085940B2 (en) * 2002-05-09 2006-08-01 International Business Machines Corporation Floating point unit power reduction via inhibiting register file write during tight loop execution
US10042814B2 (en) 2007-12-31 2018-08-07 Intel Corporation System and method for using a mask register to track progress of gathering and scattering elements between data registers and memory
US10387151B2 (en) 2007-12-31 2019-08-20 Intel Corporation Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks
US20110153983A1 (en) * 2009-12-22 2011-06-23 Hughes Christopher J Gathering and Scattering Multiple Data Elements
US10114651B2 (en) 2009-12-22 2018-10-30 Intel Corporation Gathering and scattering multiple data elements
US10175990B2 (en) 2009-12-22 2019-01-08 Intel Corporation Gathering and scattering multiple data elements
US8447962B2 (en) 2009-12-22 2013-05-21 Intel Corporation Gathering and scattering multiple data elements
US9626333B2 (en) 2012-06-02 2017-04-18 Intel Corporation Scatter using index array and finite state machine
US9753889B2 (en) 2012-06-02 2017-09-05 Intel Corporation Gather using index array and finite state machine
US8972697B2 (en) 2012-06-02 2015-03-03 Intel Corporation Gather using index array and finite state machine
US10146737B2 (en) 2012-06-02 2018-12-04 Intel Corporation Gather using index array and finite state machine
US10152451B2 (en) 2012-06-02 2018-12-11 Intel Corporation Scatter using index array and finite state machine

Also Published As

Publication number Publication date
CA2105806C (en) 2001-11-20
EP0588252B1 (de) 1998-06-03
JP3556246B2 (ja) 2004-08-18
DE69318914T2 (de) 1999-01-14
CA2105806A1 (en) 1994-03-19
EP0588252A3 (de) 1995-01-04
EP0588252A2 (de) 1994-03-23
JPH06195229A (ja) 1994-07-15
DE69318914D1 (de) 1998-07-09

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