US5493562A - Apparatus and method for selectively storing error statistics - Google Patents

Apparatus and method for selectively storing error statistics Download PDF

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Publication number
US5493562A
US5493562A US08/337,635 US33763594A US5493562A US 5493562 A US5493562 A US 5493562A US 33763594 A US33763594 A US 33763594A US 5493562 A US5493562 A US 5493562A
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error
signal
data
memory
data packet
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US08/337,635
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William Lo
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Advanced Micro Devices Inc
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Assigned to ADVANCED MICRO DEVICES INC. reassignment ADVANCED MICRO DEVICES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LO, WILLIAM
Priority to TW084102694A priority patent/TW313725B/zh
Priority to JP51606696A priority patent/JP3600876B2/ja
Priority to PCT/US1995/013498 priority patent/WO1996015606A1/en
Priority to EP95937542A priority patent/EP0739561B1/de
Priority to DE69530282T priority patent/DE69530282T2/de
Priority to AT95937542T priority patent/ATE237207T1/de
Priority to KR1019960703705A priority patent/KR100354326B1/ko
Publication of US5493562A publication Critical patent/US5493562A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823—Errors, e.g. transmission errors
    • H04L43/0847—Transmission error

Definitions

  • the present invention relates to gathering error statistics in a computer network, and more particularly to a circuit and method useful in network management that selectively stores error statistics of data packets transmitted in a computer network.
  • a network implementing automatic monitoring and management is referred to as a managed network.
  • a managed network In such a network, an ability to obtain particularized information on various error statistics is invaluable in troubleshooting problems on the network.
  • a data packet transmitted by one data terminal equipment (DTE), e.g., an end station, to another DTE passes through at least one repeater. Because all data packets pass through a repeater, the repeater is a convenient place to gather error statistics for network management.
  • DTE data terminal equipment
  • a repeater with a management unit is referred to as a managed repeater.
  • the repeater When the managed repeater receives a data packet, the repeater transmits the data packet to the management unit which performs various functions on the data packet. Some of the management unit functions include formatting the data packet upon receipt, performing error detection, and flagging error conditions.
  • One way to accumulate error statistics at the managed repeater is to use a first type of management unit (type-I) that includes internal hardware to detect errors, to count the number of occurrences of different error conditions, and to store those counts in an internal random access memory (RAM) of the management unit.
  • type-I first type of management unit
  • RAM internal random access memory
  • the hardware within the management unit detects and flags the error, and then increments an appropriate register.
  • a microprocessor is able to simply read the various registers within the type-I management unit and obtain a total count of the various types of errors.
  • IMR+/HIMIB chip set P/Ns AM79C981 (IMR) and AM79C987 (HIMIB) produced by Advanced Micro Devices of Sunnyvale, Calif.
  • a type-I managed repeater is sufficient for many tasks, but for some applications, performance is not optimum in that the statistics reflect only an aggregate number of errors accumulated over many data packets. Error statistics on a packet-by-packet basis are not available. In some cases, it is desirable to know error statistics for particular data packets.
  • a type-II management unit consists of a media access controller (MAC), a RAM, and a microprocessor.
  • a data packet from an end station is received by the repeater, which then passes the data packet to the MAC.
  • the MAC strips the preamble and the start frame delimiter from the data packet, and then formats the remaining frame of the data packet from a serial data stream to a parallel data stream.
  • the MAC writes the entire content of the frame of the data packet into the RAM.
  • the microprocessor reads the content of the RAM and processes it according to the user's programmed software. This software implements error detection and extracts the desired error statistics from the data packets.
  • the type-II management unit is inefficient and expensive, because all data packets, even error-free packets, are stored and processed. It is possible for thousands of data packets to pass through the network every second.
  • the type-II managed repeater requires both a large RAM to store the large quantity of data generated bytes rapidly incoming data packets, and a fast, powerful microprocessor to process all the data and gather error statistics.
  • the type-II management unit is inefficient in gathering some types of sophisticated error statistics. For example, if a user desires to know the error condition of a particular data packet, as well as a corresponding physical port of that data packet, the type-II management performs partly, if at all. Even assuming that the management unit uses a MAC that is equipped to flag different error conditions, the management unit must still store and process every data packet. Because of the speed at which data packets flow into the MAC and then into the RAM, by the time the MAC flags a particular error, the microprocessor cannot determine the physical port of the data packet associated with the flagged error.
  • the microprocessor In order to determine what physical port is associated with a certain error, the microprocessor must read and process the contents of all the data packets in the RAM in real-time. Thus, a type-II management unit is inefficient and expensive in gathering more sophisticated error statistics. Often external hardware is needed in addition to the repeater and management unit to determine the physical port information.
  • the present invention provides apparatus and method for selectively storing error statistics for only those data packets having an error.
  • the invention has various advantages over the prior art, including being more efficient and economic in gathering error statistics of data packets, as well as providing an increased capability to determine sophisticated error statistics on a packet-by-packet basis.
  • the invention provides a circuit including a data formatter for receiving desired information associated with a data packet and arranging the bits into a format for transfer to a memory, a memory for storing the desired information for later access by a microprocessor, and a controller for selectively transferring and writing the desired information from the data formatter to the memory.
  • the preferred embodiment provides improved performance by storing only the desired information for those data packets having an error. That is, information internal to the data packet itself, such as the source address, and information external to the data packet, such as the repeater port number, in addition to data packet error information, such as error conditions, are stored as an error statistic in a memory for a microprocessor to read at the convenience of the microprocessor.
  • the invention reduces processing requirements for a microprocessor, thereby allowing use of a slower, less expensive microprocessor. Additional advantages of the invention are that it dispenses with a MAC and does not require a very large memory that would be necessary to save all the data packets indiscriminately.
  • FIG. 1 is a detailed schematic block diagram of a preferred embodiment of the present invention.
  • FIG. 1 is a detailed schematic block diagram of a managed repeater 10, a microprocessor 20 and a plurality of data terminal equipment (DTE) 30 i .
  • Managed repeater 10 includes a repeater front end 40 having a plurality of ports 41 i , a management unit 50, and a microprocessor interface 60.
  • One DTE 30 1 passes a data packet through managed repeater 10 to another DTE 30 2 .
  • repeater front end 40 receives the data packet at one port 41 1 and broadcasts the data packet from other ports 41 i .
  • Repeater front end 40 also processes the data packet to generate a plurality of error statistic signals, with each of the signals containing either some data, an error condition, or status control information.
  • the error statistic signals are used for use by management unit 50 in extracting and storing an error statistic of the data packet.
  • the error statistic signals containing the constituent parts of the error statistic of the data packet include a series of bits which may require some formatting prior to storage.
  • Management unit 50 receives the error statistic signals and formats the error statistic of the data packet for storage, and later access by microprocessor 20. Microprocessor 20 accesses the error statistic via microprocessor interface 60.
  • the repeater front end 40 incorporates a core of the Advanced Micro Devices' IMR+/HIMIB chip set.
  • the management hardware circuitry produces the management information base (MIB) or statistics according to the incorporated IEEE standard 802.3.
  • MIB management information base
  • a repeater with a management unit generating the desired error statistic signals could be modified to incorporate the present invention.
  • Management unit 50 includes a data formatter 70, a memory 80, and a controller 90.
  • Data formatter 70 receives the error statistic signals of interest from repeater front end 40.
  • Data formatter 70 arranges the bits of the error statistic into a format for transfer into storage.
  • Memory 80 coupled to data formatter 70 stores the error statistic.
  • Controller 90 controls a transfer of the error statistic from data formatter 70 into memory 80.
  • Controller 90 is responsive to a particular error status signal, called the error signal, from repeater front end 40, that indicates that the data packet has an error.
  • controller 90 synchronously transfers and writes the error statistic from data formatter 70 into memory 80.
  • management unit 50 stores an error statistic only for a data packet with an error. Synchronously, in the preferred embodiment, refers to coordinating data transfer out of data formatter 70 and writes into memory 80.
  • management unit 50 stores an error statistic with constituent parts including: the source address of the data packet; a port number identifying the physical port that received the data packet; and error conditions of the data packet, such as frame check sequence (FCS) error, alignment error, long frame, short event, runt, data rate error, and jabber.
  • FCS frame check sequence
  • Other embodiments of the present invention may store other statistics in addition to or in place of some or all of those listed, depending upon a specific implementation.
  • repeater front end 40 generates the following error statistic signals: a data signal containing a portion of the data packet, a port signal identifying the port number of the source port, an error status signal containing an error condition associated with the data packet, a shift signal for identifying the portion, an end-of-packet signal indicating an end of the data packet, and an error signal indicating when the data packet contains an error.
  • Data formatter 70 includes a shift register 100 and a multiplexer 110 having eight 1-byte inputs and a select input for successively routing each byte at one of the inputs to an output 111.
  • Shift register 100 receives the data signal containing the desired portion of the data packet and the shift signal.
  • the shift signal provided from repeater front end 40, controls storage of the desired data packet portion into shift register 100.
  • the repeater front end 40 transmits the entire data packet in a serial bit stream to shift register 100.
  • Shift register 100 arranges the serial input into six 1-byte parallel outputs.
  • Repeater front end 40 shifts the serial bit stream into shift register 100 until the repeater front end 40 deasserts the shift signal.
  • Repeater front end 40 deasserts the shift signal once the desired portion of the data packet has been completely shifted into shift register 100.
  • a data packet's frame starts with a destination address field (a fixed length of 48 bits), followed by a source address field (a fixed length of 48 bits). Because the desired portion of the data packet is the source address field, the repeater front end 40 merely asserts the shift signal to shift in the serial bit stream until 96 bits beyond the SFD have been counted. Shift register 100 only stores 48 bits (six bytes at eight bits/byte), therefore, only the last 48 bits (i.e., the source address) is stored prior to deassertion of the shift signal. At this point, the repeater front end 40 has stored the source address field into shift register 100 in a format ready for transfer to storage.
  • SFD start frame delimiter
  • managed repeater 10 includes the capability for storing just those internal portions of the data packet of interest, rather than storing the entire frame of a data packet as in the prior art.
  • the user is able to alter the size of shift register 100 and the shift signal assertion timing, among other obvious modifications.
  • the particular portion stored is a design choice that is not central to the present invention. In the preferred embodiment, it is desirable to store a particular portion, though other portions or several portions could be stored.
  • managed repeater 10 could be programmed to select particular portions for storage depending upon various control signals, as well known in the art.
  • Multiplexer 110 successively routes the bytes at the eight inputs to an output 111.
  • Output 111 is coupled to memory 80.
  • Multiplexer 110 responsive to a series of select signals asserted at a select input 112, transfers the bytes one at a time to memory 80.
  • the bits of the source address field that have been formatted by shift register 100 are on six of the inputs to multiplexer 110.
  • the port signal is present at one input to multiplexer 110 and contains a 4 bit value that represents a port number of the managed repeater 10.
  • the port number identifies a physical port of the repeater receiving the data packet.
  • the error status signal is present at another input to multiplexer 110 and contains bits indicating error conditions associated with the data packet.
  • Memory 80 coupled to multiplexer 110, stores the error statistics in response to write signals from controller 90.
  • memory 80 is implemented as a 4 byte-wide first-in-first-out memory.
  • implementation of memory 80 is a design choice that is not central to the invention.
  • memory 80 may also be implemented otherwise, such as with a RAM, with the appropriate modifications to the controller being obvious to one skilled in the art.
  • Controller 90 receives an error signal and an end-of-packet signal from repeater front end 40.
  • repeater front end 40 When repeater front end 40 reaches the end of the data packet and has completed processing of the data packet so that the statistics on the error status signal, as well as the port signal, are valid, repeater front end 40 asserts the end-of-packet signal.
  • repeater front end 40 Upon detecting an error associated with the data packet, repeater front end 40 asserts the error signal.
  • controller 90 When repeater front end 40 asserts concurrently the error signal and the end-of-packet signal, controller 90 asserts a series of select signals to the select input 112 of the multiplexer 110 and synchronously asserts a series of write signals to the memory 80. However, if the error signal is not asserted concurrently with the end-of-packet signal, controller 90 does not assert the select signals or the write signals.
  • controller 90 When controller 90 asserts a select signal, multiplexer 110 routes the least significant byte from shift register 10 to output 111. Controller 90 then asserts a write signal to memory 80 so the byte on output 111 of multiplexer 110 is written into memory 80, thereby storing the byte value. Controller 90 continues to assert select signals and write signals until all bytes in shift register 10 as well as the in the port signal and the error status signal are written into memory 80.
  • microprocessor 20 may then read the error statistics stored in memory 80 when convenient.
  • Microprocessor 20 reads the error statistics via a microprocessor interface 60.
  • Microprocessor 20 asserts a read signal to access the error statistics. It is also possible for controller 90 to assert a status flag to microprocessor 20 to signify that the memory 80 contains an error statistic available for access.
  • microprocessor 40 simply reads the error statistics for data packets with errors that have been stored in memory 80, rather than being overburdened with the task of quickly processing massive quantities of data packets for errors.

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  • Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
US08/337,635 1994-11-10 1994-11-10 Apparatus and method for selectively storing error statistics Expired - Lifetime US5493562A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US08/337,635 US5493562A (en) 1994-11-10 1994-11-10 Apparatus and method for selectively storing error statistics
TW084102694A TW313725B (de) 1994-11-10 1995-03-21
EP95937542A EP0739561B1 (de) 1994-11-10 1995-10-11 Vorrichtung und verfahren zur selektiven speicherung von fehlerstatistiken
PCT/US1995/013498 WO1996015606A1 (en) 1994-11-10 1995-10-11 Apparatus and method for selectively storing error statistics
JP51606696A JP3600876B2 (ja) 1994-11-10 1995-10-11 エラー統計を選択的に記憶するための装置および方法
DE69530282T DE69530282T2 (de) 1994-11-10 1995-10-11 Vorrichtung und verfahren zur selektiven speicherung von fehlerstatistiken
AT95937542T ATE237207T1 (de) 1994-11-10 1995-10-11 Vorrichtung und verfahren zur selektiven speicherung von fehlerstatistiken
KR1019960703705A KR100354326B1 (ko) 1994-11-10 1995-10-11 에러통계를선택적으로저장하는장치및방법

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US08/337,635 US5493562A (en) 1994-11-10 1994-11-10 Apparatus and method for selectively storing error statistics

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US5493562A true US5493562A (en) 1996-02-20

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EP (1) EP0739561B1 (de)
JP (1) JP3600876B2 (de)
KR (1) KR100354326B1 (de)
AT (1) ATE237207T1 (de)
DE (1) DE69530282T2 (de)
TW (1) TW313725B (de)
WO (1) WO1996015606A1 (de)

Cited By (8)

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Publication number Priority date Publication date Assignee Title
US5793421A (en) * 1994-12-30 1998-08-11 Hyundai Electronics Industries Co., Ltd. Apparatus for testing ordered type video terminal by using computer and testing method therefor
US5848058A (en) * 1994-07-28 1998-12-08 Fujitsu Limited Frame relay switching node
US5887050A (en) * 1997-05-09 1999-03-23 Siemens Building Technologies, Inc. Repeater apparatus having isolation circuit
US6381706B1 (en) * 1998-10-20 2002-04-30 Ecrix Corporation Fine granularity rewrite method and apparatus for data storage device
US6463478B1 (en) * 1999-05-21 2002-10-08 Advanced Micro Devices, Inc. Method and apparatus for identifying runt data frames received by a network switch
US20030172326A1 (en) * 2002-03-08 2003-09-11 Coffin Louis F. Error/status information management
US20030169686A1 (en) * 2002-03-06 2003-09-11 Broadcom Corporation Optimized data path structure for multi-channel management information base (MIB) event generation
US7254738B1 (en) * 1998-12-28 2007-08-07 Samsung Electronics Co., Ltd. Method for processing error of received packet in ethernet MAC layer

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Cited By (13)

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Publication number Priority date Publication date Assignee Title
US5848058A (en) * 1994-07-28 1998-12-08 Fujitsu Limited Frame relay switching node
US5793421A (en) * 1994-12-30 1998-08-11 Hyundai Electronics Industries Co., Ltd. Apparatus for testing ordered type video terminal by using computer and testing method therefor
US5887050A (en) * 1997-05-09 1999-03-23 Siemens Building Technologies, Inc. Repeater apparatus having isolation circuit
AU733110B2 (en) * 1997-05-09 2001-05-10 Siemens Building Technologies, Inc. Repeater apparatus having isolation circuit
US6381706B1 (en) * 1998-10-20 2002-04-30 Ecrix Corporation Fine granularity rewrite method and apparatus for data storage device
US7254738B1 (en) * 1998-12-28 2007-08-07 Samsung Electronics Co., Ltd. Method for processing error of received packet in ethernet MAC layer
US6463478B1 (en) * 1999-05-21 2002-10-08 Advanced Micro Devices, Inc. Method and apparatus for identifying runt data frames received by a network switch
US7039010B2 (en) * 2002-03-06 2006-05-02 Broadcom Corporation Optimized data path structure for multi-channel management information base (MIB) event generation
US20030169686A1 (en) * 2002-03-06 2003-09-11 Broadcom Corporation Optimized data path structure for multi-channel management information base (MIB) event generation
US20030172326A1 (en) * 2002-03-08 2003-09-11 Coffin Louis F. Error/status information management
US6983408B2 (en) * 2002-03-08 2006-01-03 Microsoft Corporation Managing error/status information generated during video processing
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Also Published As

Publication number Publication date
TW313725B (de) 1997-08-21
DE69530282D1 (de) 2003-05-15
WO1996015606A1 (en) 1996-05-23
DE69530282T2 (de) 2004-01-29
EP0739561B1 (de) 2003-04-09
KR100354326B1 (ko) 2003-01-06
EP0739561A1 (de) 1996-10-30
JP3600876B2 (ja) 2004-12-15
JPH09507994A (ja) 1997-08-12
ATE237207T1 (de) 2003-04-15

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