US5400740A - Method of preparing compound semiconductor - Google Patents

Method of preparing compound semiconductor Download PDF

Info

Publication number
US5400740A
US5400740A US08/069,729 US6972993A US5400740A US 5400740 A US5400740 A US 5400740A US 6972993 A US6972993 A US 6972993A US 5400740 A US5400740 A US 5400740A
Authority
US
United States
Prior art keywords
gas
group
compound semiconductor
etching
iii
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/069,729
Inventor
Hideki Goto
Kenji Shimoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Chemical Corp
Original Assignee
Mitsubishi Chemical Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP14180792A external-priority patent/JP3158651B2/en
Application filed by Mitsubishi Chemical Corp filed Critical Mitsubishi Chemical Corp
Assigned to MITSUBISHI CHEMICAL CORPORATION reassignment MITSUBISHI CHEMICAL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GOTO, HIDEKI, SHIMOYAMA, KENJI
Assigned to MITSUBISHI CHEMICAL CORPORATION reassignment MITSUBISHI CHEMICAL CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: MITSUBISHI KASEI CORPORATION
Application granted granted Critical
Publication of US5400740A publication Critical patent/US5400740A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02019—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching

Definitions

  • the present invention relates to a method of preparing a compound semiconductor having a carrier-injection layer or an electrode-drawing layer, which is formed by a crystal regrowth method and a selective crystal growth method.
  • the structure suitable for the shortening tendency of a channel has been investigated in an electron device, and also the side-joint structure fitted for the OEIC (Optoelectronic Integrated Circuit) has been investigated in a semiconductor laser.
  • OEIC Optoelectronic Integrated Circuit
  • the surface of a substrate or an epitaxial growth layer is subjected to an impurity pollution or a physical damage, during the processes of exposure in the air, etching, washing and the like. Then, in case where a crystal regrowth is directly effected on these surfaces as they are, the performance or the life time of a device will be exceedingly deteriorated. For that reason, the cleaning of the surface and the removal of the damaged layer have been executed in a crystal growth chamber by a vapor phase etching method, successively followed by effecting the crystal regrowth procedure.
  • the compound semiconductor device prepared by such method poses a problem that the carrier will be stored on the regrowth surface as shown in FIG. 1, though the purity of the surface will be improved.
  • the inventors assumed that in case of a usual compound semiconductor, for example, the III-V group compound semiconductor, the chlorides of III-group and V-group elements would be formed on the surface by introducing, for example, a chlorine-series etching gas, and the etching would be proceeded by an evaporation of these chlorides into a vapor phase, and then, a stoichiometric discrepancy between III-group and V-group would occur on the gas-etched surface, thereby bringing about a carrier storing in the crystal regrowth interface.
  • a chlorine-series etching gas for example, a chlorine-series etching gas
  • the inventors found out that a plain profile without the carrier storing on the regrowth interface could be obtained, by flowing the III-group organic metals gas and/or hydrides containing V-group elements, or the V-group organic metals gas during the gas-etching, in order to solve the above carrier storing.
  • the object in accordance with the present invention, can be achieved, by a method of preparing a compound semiconductor which comprises introducing the hydrides III-group organic metals gas and/or hydrides containing V-group elements, or the V-group organic metals gas into a crystal growth chamber, in addition to the carrier gas and the etching gas, in a method of preparing a III-V group compound semiconductor including the process to effect the gas etching of a single crystal substrate surface and a single crystal thin-film surface in the crystal growth chamber, just before the vapor phase growth of a compound semiconductor thin-film is carried out, using the hydrides and the organic metals gas.
  • the object can be preferably achieved, by the above method of preparing a compound semiconductor crystal, wherein a compound semiconductor thin-film will be allowed to be regrown or selectively grown, on the mesa-shape substrate or the epitaxial layer formed by a gas-etching in the growth chamber. Further, the object can be preferably achieved, by the above method of preparing a compound semiconductor crystal and by the compound semiconductor obtained thereby, wherein a gas containing halogen elements will be used, as the gas used in the vapor phase etching.
  • III-V group compound semiconductors to be used in the present invention are not specifically limited, if these are conventionally used as a semiconductor device, and GaAs, GaAlAs, InP, InAsP, InSaAsP and the like are concretely used.
  • the hydrides and the organic metals gas are not also particularly limited, and these may be selected from the ones with which a desired compound semiconductor will be obtained.
  • TMG trimethyl gallium
  • TAG triethyl gallium
  • TMA trimethyl aluminum
  • TMA triethyl aluminum
  • TMI trimethyl indium
  • the III-group organic metals gas and/or hydrides containing V-group elements, or the V-group organic metals gas will be flowed cocurrently with a carrier gas and an etching gas, at the time the etching for the cleaning of growth surface is effected in a crystal growth chamber, immediately before the vapor phase growth of the compound semiconductor thin-film, using the aforementioned hydrides and organic metals gas.
  • the organic metals gas and/or the hydrides used at this time are not specially limited, provided that these contain the III-group and/or the V-group elements composing the compound to be grown by a vapor phase growth method.
  • the III-group organic metals gas will be introduced, when the dopants to enter the III-group site are employed, and also the hydrides containing the V-group elements or the V-group organic metals gas will be introduced, when the dopants to enter the V-group site are employed.
  • the storing of dopant in a hetero junction interface will be decreased.
  • the III-group organic metals gas is preferably used and TMG or TEG is concretely used.
  • the hydrides containing the V-group elements or the V-group organic metals gas are preferably used and arsine is concretely used.
  • the carrier gas is not especially limited providing that it bas been commonly used so far, and hydrogen is concretely used.
  • the etching gas is not limited if it has been usually used.
  • a gas containing halogen elements is preferable, a chlorine series reactive gas is more preferable, and at least one member selected from the group consisting of HCl, CCl 2 F 2 , AsCl 3 , and Cl 2 is most preferable.
  • the etching condition is not limited, but 500°-800° C. of temperature is usually used so as to enhance the etching speed.
  • the introducing amount of the etching gas and the organic gas varies to a great extent, according to the size of crystal growth chamber and the performance of desired semiconductor device, and in general, more etching gas than the organic metals gas will be introduced. Also, since the etching speed will be lowered according to the reduction of temperature, the amount of the etching gas may be increased in case of low temperatures.
  • the total pressure of the gas to be flowed is preferably at normal pressure or less.
  • FIG. 1 is a carrier-concentration profile around the regrowth surface in the case where TMG was not flowed together with an etching gas during a vapor etching process.
  • FIG. 2 is a carrier-concentration profile around the regrowth surface in the case where TMG was flowed together with an etching gas during a vapor etching process.
  • FIG. 3 is a carrier-concentration profile around the regrowth surface in the case where the regrowth was effected without the etching operation after an atmosphere exposure.
  • FIG. 4 is a result of the SIMS (Secondary Ion Mass Spectrometer) analysis in the case where the regrowth was effected without the etching after an atmosphere exposure.
  • FIG. 5 is a result of the SIMS analysis, in the case where the gas etching operation was effected after an atmosphere exposure and then the regrowth was executed.
  • MOVPE Metal-Organic Vapor Phase Epitaxial growth
  • TMG trimethyl gallium
  • AsH 3 arsine
  • HCl hydrogen chloride
  • the vapor phase etching by 0.3 ⁇ m in thickness of the wafer surface was conducted with hydrogen chloride gas in the MOVPE reaction-furnace. Si the dopant entered the III-group site, and then, TMG of the III-group organic metal gas was used together with an etching gas.
  • the carrier-concentration distribution in the direction of depth was measured by C--V method, regarding the regrown wafer in both cases where TMG was flowed A) and TMG was not flowed (sample B) during the vapor etching, and the measurement result is shown in FIG. 1 and FIG. 2.
  • the impurity pollution, the oxide film, the thermometamorphism layer and the like in the interface between a single crystal substrate and an epitaxial layer, and also in the regrown interface, which have been the problem up to this time, can be removed by effecting a vapor etching, flowing the hydrides containing III-group organic metals gas and/or V-group elements, or the V-group organic metals gas, immediately before a compound semiconductor thin-film is grown.
  • a high quality regrown interface having the purified surface and causing no storing or no shortage of the carrier can be obtained, thus making it possible to greatly improve the performance as compared with the device prepared by a conventional method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method of preparing a compound semiconductor is carried out, by introducing the group III organic metals gas and/or the hydrides containing group V elements, or group V organic metals gas into a growth chamber, in addition to a carrier gas and an etching gas, in a method of preparing a group III-V compound semiconductor including the process to effect the gas etching of a single crystal sustrate surface and/or a single crystal thin-film surface in the growth chamber, just before a vapor phase growth of a compound semiconductor thin-film is performed, using the hydrides and the organic metals gas.
According to the present invention, the impurity pollution, the oxide film, the thermometamorphism and the hike, in an interface between the single crystal substrate and the epitaxial layer as well as in the regrown interface can be removed, thereby making it possible to get a clean surface of the interface and to restrain the accumulation or the depletion of carrier-concentration which has not been intended. As a result, the quality of the device can be greatly improved as compared with that of the one obtained by a usual preparing method.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of preparing a compound semiconductor having a carrier-injection layer or an electrode-drawing layer, which is formed by a crystal regrowth method and a selective crystal growth method.
2. Description of the Related Art
For the purpose of improving the performance of a compound semiconductor device, the structure suitable for the shortening tendency of a channel has been investigated in an electron device, and also the side-joint structure fitted for the OEIC (Optoelectronic Integrated Circuit) has been investigated in a semiconductor laser. As an effective method to realize these structures, a self-alignment method of forming a carrier-injection layer or an electrode-drawing layer, by a crystal regrowth and a selective crystal growth methods, has been generally used.
In this case, the surface of a substrate or an epitaxial growth layer is subjected to an impurity pollution or a physical damage, during the processes of exposure in the air, etching, washing and the like. Then, in case where a crystal regrowth is directly effected on these surfaces as they are, the performance or the life time of a device will be exceedingly deteriorated. For that reason, the cleaning of the surface and the removal of the damaged layer have been executed in a crystal growth chamber by a vapor phase etching method, successively followed by effecting the crystal regrowth procedure. The compound semiconductor device prepared by such method, however, poses a problem that the carrier will be stored on the regrowth surface as shown in FIG. 1, though the purity of the surface will be improved.
SUMMARY OF THE INVENTION
Then, the inventors have devoted themselves to overcome the above problem, and have reached the present invention as will be explained in the following steps:
Firstly, the inventors assumed that in case of a usual compound semiconductor, for example, the III-V group compound semiconductor, the chlorides of III-group and V-group elements would be formed on the surface by introducing, for example, a chlorine-series etching gas, and the etching would be proceeded by an evaporation of these chlorides into a vapor phase, and then, a stoichiometric discrepancy between III-group and V-group would occur on the gas-etched surface, thereby bringing about a carrier storing in the crystal regrowth interface.
Secondly, the inventors found out that a plain profile without the carrier storing on the regrowth interface could be obtained, by flowing the III-group organic metals gas and/or hydrides containing V-group elements, or the V-group organic metals gas during the gas-etching, in order to solve the above carrier storing.
Accordingly, it is an object of the present invention to provide a method of preparing a semiconductor device, which gives at the same time both performances in an improved purity of the recrystallization-interface and in the stabilization of the carrier-concentration disorder.
The object, in accordance with the present invention, can be achieved, by a method of preparing a compound semiconductor which comprises introducing the hydrides III-group organic metals gas and/or hydrides containing V-group elements, or the V-group organic metals gas into a crystal growth chamber, in addition to the carrier gas and the etching gas, in a method of preparing a III-V group compound semiconductor including the process to effect the gas etching of a single crystal substrate surface and a single crystal thin-film surface in the crystal growth chamber, just before the vapor phase growth of a compound semiconductor thin-film is carried out, using the hydrides and the organic metals gas.
Also, the object can be preferably achieved, by the above method of preparing a compound semiconductor crystal, wherein a compound semiconductor thin-film will be allowed to be regrown or selectively grown, on the mesa-shape substrate or the epitaxial layer formed by a gas-etching in the growth chamber. Further, the object can be preferably achieved, by the above method of preparing a compound semiconductor crystal and by the compound semiconductor obtained thereby, wherein a gas containing halogen elements will be used, as the gas used in the vapor phase etching.
The present invention will be explained in detail below. The III-V group compound semiconductors to be used in the present invention are not specifically limited, if these are conventionally used as a semiconductor device, and GaAs, GaAlAs, InP, InAsP, InSaAsP and the like are concretely used. The hydrides and the organic metals gas are not also particularly limited, and these may be selected from the ones with which a desired compound semiconductor will be obtained. For example, in case of GaAs, arsine (AsH3) or phosphine (PH3) are used as the hydride, and trimethyl gallium (TMG), triethyl gallium (TEG), trimethyl aluminum (TMA), triethyl aluminum (TEA), trimethyl indium (TMI) and the like are usually used as the organic metals gas.
In accordance with the present invention, it is featured that the III-group organic metals gas and/or hydrides containing V-group elements, or the V-group organic metals gas will be flowed cocurrently with a carrier gas and an etching gas, at the time the etching for the cleaning of growth surface is effected in a crystal growth chamber, immediately before the vapor phase growth of the compound semiconductor thin-film, using the aforementioned hydrides and organic metals gas. The organic metals gas and/or the hydrides used at this time are not specially limited, provided that these contain the III-group and/or the V-group elements composing the compound to be grown by a vapor phase growth method.
As a more preferable mode for working the instant invention, especially in case of the doping immediately after the gas-etching, the III-group organic metals gas will be introduced, when the dopants to enter the III-group site are employed, and also the hydrides containing the V-group elements or the V-group organic metals gas will be introduced, when the dopants to enter the V-group site are employed. By this operation, the storing of dopant in a hetero junction interface will be decreased. For instance, in case of the silicon doping, the III-group organic metals gas is preferably used and TMG or TEG is concretely used. In case of the selenium doping, the hydrides containing the V-group elements or the V-group organic metals gas are preferably used and arsine is concretely used.
The carrier gas is not especially limited providing that it bas been commonly used so far, and hydrogen is concretely used. Also, the etching gas is not limited if it has been usually used. A gas containing halogen elements is preferable, a chlorine series reactive gas is more preferable, and at least one member selected from the group consisting of HCl, CCl2 F2, AsCl3, and Cl2 is most preferable.
The etching condition is not limited, but 500°-800° C. of temperature is usually used so as to enhance the etching speed. The introducing amount of the etching gas and the organic gas varies to a great extent, according to the size of crystal growth chamber and the performance of desired semiconductor device, and in general, more etching gas than the organic metals gas will be introduced. Also, since the etching speed will be lowered according to the reduction of temperature, the amount of the etching gas may be increased in case of low temperatures. The total pressure of the gas to be flowed is preferably at normal pressure or less.
BRIEF DESCRIPTION OF DRAWING
The objects, features, and advantages of the present invention will become more apparent from the following description of the preferred embodiment taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a carrier-concentration profile around the regrowth surface in the case where TMG was not flowed together with an etching gas during a vapor etching process.
FIG. 2 is a carrier-concentration profile around the regrowth surface in the case where TMG was flowed together with an etching gas during a vapor etching process.
FIG. 3 is a carrier-concentration profile around the regrowth surface in the case where the regrowth was effected without the etching operation after an atmosphere exposure.
FIG. 4 is a result of the SIMS (Secondary Ion Mass Spectrometer) analysis in the case where the regrowth was effected without the etching after an atmosphere exposure.
FIG. 5 is a result of the SIMS analysis, in the case where the gas etching operation was effected after an atmosphere exposure and then the regrowth was executed.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention will be explained in more detail, by reference to the following Example in connection with the drawings. The present invention is by no means limited to the Example, without departing from the spirit and the scope thereof.
EXAMPLE
In this Example, as a raw material in the case where the growth is effected using a Metal-Organic Vapor Phase Epitaxial growth (hereinafter refer to as MOVPE) method, TMG (trimethyl gallium) and AsH3 (arsine) were used, and as an etching gas, HCl (hydrogen chloride) was used. On the Si-dope GaAs substrate [100], 0.5 μm of Si-dope GaAs layer (n=1×1018 cm-3) and 1.5 μm of Si-dope GaAs layer (n=1×1017 cm-3) were epitaxially grown by using a reduced pressure (76 Torr) MOVPE method. This wafer was drawn out of the MOVPE reaction-furnace, and left exposed in an atmosphere for 12 hours. Then the wafer was returned back to the reaction-furnace, and 0.5 μm of Si-dope GaAs layer (n=1×1017 cm-3) was regrown.
Before the regrowth, the vapor phase etching by 0.3 μm in thickness of the wafer surface was conducted with hydrogen chloride gas in the MOVPE reaction-furnace. Si the dopant entered the III-group site, and then, TMG of the III-group organic metal gas was used together with an etching gas. The carrier-concentration distribution in the direction of depth was measured by C--V method, regarding the regrown wafer in both cases where TMG was flowed A) and TMG was not flowed (sample B) during the vapor etching, and the measurement result is shown in FIG. 1 and FIG. 2.
In the case of sample C, when the growth was effected as it was, without the vapor etching in the reaction-furnace prior to the regrowth, a large depletion of the carrier-concentration on the regrowth interface was noticed as shown in FIG. 3. This depletion part was a high resistant layer, which exerted such large effect as caused a thyristor phenomenon on a device performance. In case where TMG was not flowed during the vapor etching, the storing of carrier was noticed on the regrown interface. To the contrary, in case where TMG was flowed, a flat profile was obtained. The flowing of AsH3 during this etching gave the decreasing of etching grade, along with the increasing of the AsH3 flowing amount, but the storing of carrier-concentration was not dependent on the AsH3 flowing amount. The flowing gave no change of the etching grade, but gave an effect to the suppression of the carrier storing.
Also, a profile of the mobility in the direction of depth was measured on the samples A and B. In the sample B, the mobility was greatly lowered, but in the sample A, the mobility nearby the regrown interface was noticed to be lowered. The planarization of carrier profile in the sample A was not due to the compensation of p-type impurities, but a high-quality regrown interface was found to be formed.
Further, the SINS analysis of these samples was run. As shown in FIG. 4 and FIG. 5, the impurity peaks of oxygen, carbon, silicon and the like, which were noticed in the sample C regrown without a vapor etching, were not found. But it was recognized that a pure regrown interface was obtained by effecting a vapor etching, though TMG was not flowed during the vapor etching.
It can be considered, from the fact mentioned above, that whether the carrier will be stored or not, in case of the vapor etching, is related to the discrepancy of the stoichiometry on the vapor etching surface.
As stated above, in accordance with the present invention, the impurity pollution, the oxide film, the thermometamorphism layer and the like in the interface between a single crystal substrate and an epitaxial layer, and also in the regrown interface, which have been the problem up to this time, can be removed by effecting a vapor etching, flowing the hydrides containing III-group organic metals gas and/or V-group elements, or the V-group organic metals gas, immediately before a compound semiconductor thin-film is grown. As a result, a high quality regrown interface having the purified surface and causing no storing or no shortage of the carrier can be obtained, thus making it possible to greatly improve the performance as compared with the device prepared by a conventional method.

Claims (5)

What is claimed is:
1. In a method of preparing a III-V group compound semiconductor including a process of effecting gas etching of a single crystal substrate surface and/or a single crystal thin-film surface in a crystal growth chamber, just before vapor phase growth of a compound semiconductor thin-film is carried out using hydrides and an organic metals gas, the improvement comprises introducing the hydrides containing III-group organic metals gas and/or V-group elements, or V-group organic metals gas into the crystal growth chamber, in addition to a carrier gas and a etching gas.
2. A method of preparing a III-V group compound semiconductor according to claim 1, wherein the III-group organic metals gas is introduced when a dopant to enter the III-group site is used, and the hydrides containing V-group elements or the V-group organic metals gas is introduced when a dopant to enter the V-group site is used, in case where doping is effected just after gas etching.
3. A method of preparing a III-V group compound semiconductor according to claim 1, wherein the compound semiconductor thin-film is regrown or selectively grown on a mesa shape substrate or on an epitaxial layer formed by a gas etching in a crystal growth chamber.
4. A method of preparing III-V group compound semiconductor according to claim 1, wherein the etching gas contains a halogens gas.
5. A method of preparing a III-V group compound semiconductor according to claim 1, wherein the etching gas contains at least one chlorine-series reaction gas selected from the group consisting of HCl, CCl2 F2, AsCl3, and Cl2.
US08/069,729 1992-02-06 1993-06-01 Method of preparing compound semiconductor Expired - Lifetime US5400740A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4-141807 1992-02-06
JP14180792A JP3158651B2 (en) 1991-07-04 1992-06-02 Compound semiconductor and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US5400740A true US5400740A (en) 1995-03-28

Family

ID=15300589

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/069,729 Expired - Lifetime US5400740A (en) 1992-02-06 1993-06-01 Method of preparing compound semiconductor

Country Status (3)

Country Link
US (1) US5400740A (en)
EP (1) EP0573270B1 (en)
DE (1) DE69320540T2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5756374A (en) * 1995-03-27 1998-05-26 Sumitomo Electric Industries, Ltd. Compound semiconductor light emitting device and method of preparing the same
US5888294A (en) * 1995-03-09 1999-03-30 Korea Institute Of Science And Technology Epitaxial growth rate varying method for side surface of semiconductor pattern
US20030124817A1 (en) * 2000-04-27 2003-07-03 Sumitomo Electric Industries, Ltd. Apparatus for fabricating compound semiconductor device
US20040140477A1 (en) * 2002-07-23 2004-07-22 Kentaro Tani Semiconductor light emitting device and method for producing the same
WO2005031829A1 (en) * 2003-09-24 2005-04-07 Nec Corporation Method of cleaning treatment and method for manufacturing semiconductor device
US20090087966A1 (en) * 2007-09-28 2009-04-02 Mitsubishi Electric Corporation Method for manufacturing semiconductor device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5346581A (en) * 1993-04-01 1994-09-13 At&T Bell Laboratories Method of making a compound semiconductor device
JPH07211692A (en) * 1994-01-12 1995-08-11 Sumitomo Electric Ind Ltd Micromachining method for inp based compound semiconductor
JP2005005727A (en) * 2001-11-19 2005-01-06 Sanyo Electric Co Ltd Compound semiconductor light emitting device
JP2004343139A (en) * 2001-11-19 2004-12-02 Sanyo Electric Co Ltd Compound semiconductor light emitting element
US7276742B2 (en) 2001-11-19 2007-10-02 Sanyo Electric Co., Ltd. Compound semiconductor light emitting device and its manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4147571A (en) * 1977-07-11 1979-04-03 Hewlett-Packard Company Method for vapor epitaxial deposition of III/V materials utilizing organometallic compounds and a halogen or halide in a hot wall system
US4488914A (en) * 1982-10-29 1984-12-18 The United States Of America As Represented By The Secretary Of The Air Force Process for the epitaxial deposition of III-V compounds utilizing a continuous in-situ hydrogen chloride etch

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5670630A (en) * 1979-11-14 1981-06-12 Mitsubishi Monsanto Chem Co Manufacture of compound semiconductor by gas phase epitaxial growth
US4671847A (en) * 1985-11-18 1987-06-09 The United States Of America As Represented By The Secretary Of The Navy Thermally-activated vapor etchant for InP
JP2735190B2 (en) * 1987-04-02 1998-04-02 日本電気株式会社 Molecular beam epitaxy growth method and growth apparatus
US5068007A (en) * 1990-09-24 1991-11-26 Motorola, Inc. Etching of materials in a noncorrosive environment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4147571A (en) * 1977-07-11 1979-04-03 Hewlett-Packard Company Method for vapor epitaxial deposition of III/V materials utilizing organometallic compounds and a halogen or halide in a hot wall system
US4488914A (en) * 1982-10-29 1984-12-18 The United States Of America As Represented By The Secretary Of The Air Force Process for the epitaxial deposition of III-V compounds utilizing a continuous in-situ hydrogen chloride etch

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5888294A (en) * 1995-03-09 1999-03-30 Korea Institute Of Science And Technology Epitaxial growth rate varying method for side surface of semiconductor pattern
US5756374A (en) * 1995-03-27 1998-05-26 Sumitomo Electric Industries, Ltd. Compound semiconductor light emitting device and method of preparing the same
US20030124817A1 (en) * 2000-04-27 2003-07-03 Sumitomo Electric Industries, Ltd. Apparatus for fabricating compound semiconductor device
US6815316B2 (en) 2000-04-27 2004-11-09 Sumitomo Electric Industries, Ltd. Apparatus for fabricating compound semiconductor device
US20040140477A1 (en) * 2002-07-23 2004-07-22 Kentaro Tani Semiconductor light emitting device and method for producing the same
US7042023B2 (en) * 2002-07-23 2006-05-09 Sharp Kabushiki Kaisha Semiconductor light emitting device and method for producing the same
WO2005031829A1 (en) * 2003-09-24 2005-04-07 Nec Corporation Method of cleaning treatment and method for manufacturing semiconductor device
US20070020933A1 (en) * 2003-09-24 2007-01-25 Koichi Naniwae Method of cleaning treatment and method for manufacturing semiconductor device
US20100252914A1 (en) * 2003-09-24 2010-10-07 Nec Corporation Optical semiconductor device with a concentration of residual silicon
US20090087966A1 (en) * 2007-09-28 2009-04-02 Mitsubishi Electric Corporation Method for manufacturing semiconductor device
US7855096B2 (en) 2007-09-28 2010-12-21 Mitsubishi Electric Corporation Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
EP0573270B1 (en) 1998-08-26
EP0573270A3 (en) 1994-02-16
EP0573270A2 (en) 1993-12-08
DE69320540D1 (en) 1998-10-01
DE69320540T2 (en) 1999-02-18

Similar Documents

Publication Publication Date Title
EP0390552B1 (en) Method of manufacturing compound semiconductor thin film
Olsen et al. Crystal growth and properties of binary, ternary and quaternary (In, Ga)(As, P) alloys grown by the hydride vapor phase epitaxy technique
USRE41310E1 (en) Methods for growing semiconductors and devices thereof the alloy semiconductor gainnas
US5400740A (en) Method of preparing compound semiconductor
KR19980080216A (en) Epitaxial Wafers and Manufacturing Methods Thereof
US5332451A (en) Epitaxially grown compound-semiconductor crystal
CA1041646A (en) Semiconductor-liquid phase epitaxial growth method
US5837056A (en) Method for growing III-V group compound semiconductor crystal
JP3158651B2 (en) Compound semiconductor and method of manufacturing the same
EP0524817B1 (en) Crystal growth method of III - V compound semiconductor
JP3399642B2 (en) Method for forming semiconductor light emitting element layer
JP3242571B2 (en) Vapor growth method
US5441913A (en) Process of making a semiconductor epitaxial substrate
GB2253304A (en) Selective growth of InP in semiconductor fabrication
US6036769A (en) Preparation of semiconductor substrates
Abernathy Growth of heterojunction bipolar transistors by metalorganic molecular beam epitaxy
JP2735190B2 (en) Molecular beam epitaxy growth method and growth apparatus
JP2661155B2 (en) Vapor phase epitaxial growth method
JP3213551B2 (en) Method and apparatus for vapor phase growth of III-V compound semiconductors
JP3648521B2 (en) Metal organic vapor phase growth apparatus and metal organic vapor phase growth method
JPH06112517A (en) Crystal growing method
KR960004904B1 (en) Growing method for ga-as on the porous silicon substrate
JP2590728B2 (en) Selective growth method of compound semiconductor
JPH06267867A (en) Crystal growing method of compound semiconductor and formation of ohmic contact using same
JPH0897442A (en) Compound semiconductor epitaxial wafer and semiconductor device

Legal Events

Date Code Title Description
STPP Information on status: patent application and granting procedure in general

Free format text: APPLICATION UNDERGOING PREEXAM PROCESSING

AS Assignment

Owner name: MITSUBISHI CHEMICAL CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GOTO, HIDEKI;SHIMOYAMA, KENJI;REEL/FRAME:007228/0383

Effective date: 19941121

AS Assignment

Owner name: MITSUBISHI CHEMICAL CORPORATION, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:MITSUBISHI KASEI CORPORATION;REEL/FRAME:007332/0577

Effective date: 19941001

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12