US5301284A - Mixed-resolution, N-dimensional object space method and apparatus - Google Patents

Mixed-resolution, N-dimensional object space method and apparatus Download PDF

Info

Publication number
US5301284A
US5301284A US07/642,508 US64250891A US5301284A US 5301284 A US5301284 A US 5301284A US 64250891 A US64250891 A US 64250891A US 5301284 A US5301284 A US 5301284A
Authority
US
United States
Prior art keywords
dimensional
resolution
mixed
space
computing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US07/642,508
Other languages
English (en)
Inventor
Mark D. Estes
John P. Walker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Walker Estes Corp
Original Assignee
Walker Estes Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Walker Estes Corp filed Critical Walker Estes Corp
Assigned to WALKER-ESTES CORPORATION reassignment WALKER-ESTES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: ESTES, MARK D., WALKER, JOHN P.
Priority to US07/642,508 priority Critical patent/US5301284A/en
Priority to IL100462A priority patent/IL100462A/xx
Priority to DE69230334T priority patent/DE69230334T2/de
Priority to AT92904389T priority patent/ATE187002T1/de
Priority to JP50451592A priority patent/JP3385019B2/ja
Priority to CA002100359A priority patent/CA2100359C/en
Priority to ES92904389T priority patent/ES2142313T3/es
Priority to AU12393/92A priority patent/AU647247B2/en
Priority to KR1019930701860A priority patent/KR100236493B1/ko
Priority to BR9205572-9A priority patent/BR9205572A/pt
Priority to SG1996003653A priority patent/SG43876A1/en
Priority to EP92904389A priority patent/EP0567563B1/de
Priority to PCT/US1992/000218 priority patent/WO1992013313A1/en
Priority to CN92100094A priority patent/CN1041568C/zh
Priority to MX9200189A priority patent/MX9200189A/es
Priority to TW081101757A priority patent/TW287341B/zh
Priority to US08/218,333 priority patent/US5680634A/en
Publication of US5301284A publication Critical patent/US5301284A/en
Application granted granted Critical
Priority to US08/951,057 priority patent/US5852740A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T17/00Three dimensional [3D] modelling, e.g. data description of 3D objects
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S715/00Data processing: presentation processing of document, operator interface processing, and screen saver display processing
    • Y10S715/961Operator interface with visual structure or function dictated by intended use
    • Y10S715/965Operator interface with visual structure or function dictated by intended use for process control and configuration
    • Y10S715/966Computer process, e.g. operation of computer

Definitions

  • This invention relates to an apparatus and method for transforming an object description into mixed-resolution, N-dimensional object spaces.
  • This invention also relates to an apparatus and method for visualizing mixed-resolution, N-dimensional object spaces, by projecting a bit-interleaved object descriptor onto a plane. More particularly, this invention relates to an apparatus and method for encoding attribute names corresponding to spatial locations with a novel k-ary reflected code.
  • MCC Microelectronics and Computer Consortium
  • Karnaugh describes a method for mapping abstract representations of circuit inputs into visual space.
  • the Karnaugh map often called a k-map, is a widely known technique for visualizing logical expressions based on a two-valued Boolean algebra. Entries representing circuit inputs correspond to a position in a k-map derived from visualizing the codes as points in a binary n-space.
  • the k-map is a two-dimensional representation of this space mapped onto the Cartesian plane by labeling each axis with a binary Gray code. Inferences drawn from this visual representation of logic expressions usually result in a reduction of the canonical expression. It has long been known that Karnaugh's graphical method of representing all possible combinations of N switching variables on a plane breaks down for problems with a large number of switching variables.
  • Gray codes differ in only one quantum interval, that is, one bit position in the case of binary Gray codes.
  • a Gray code is said to cycle if its first and last codewords differ in only one quantum interval, otherwise it describes a path.
  • Each consecutive codeword in a binary Gray code can be represented by the bit position that changes. Given an initial codeword and a transition sequence the entire set of codewords can be generated.
  • U.S. Pat. No. 2,632,058 issued to Frank Gray distinguishes between a primary form and secondary variants of the reflected binary code:
  • this code in its primary form may be built up from the conventional binary code by sort of a reflection process and because other forms may in turn be built up from the primary form in similar fashion, the code in question, which has as yet no recognized name, is designated in this specification and in the claims as the ⁇ reflected binary code. ⁇
  • FIGS. 1A-1E show a prior art method of unfolding a binary 3-cube onto a plane as a k-map, described by Clare in Designing Logic System Using State Machines, 1973, McGraw-Hill, N.Y., pp. 14-15.
  • FIG. 2 is a prior art representation of binary n-cubes as k-maps, showing a 0-cube k-map 200, a 1-cube k-map 201, a 2-cube k-map 202, a 2-cube k-map 203, a 3-cube k-map 204, and a 4-cube k-map 205.
  • the 2-cube k-maps 202, 203 are different representations for a two-variable k-map shown by Karnaugh in the article referenced above. Such alternate spatial representations are inconsistent with each other.
  • region identifiers A 206, B 207, and C 208 in the 3-cube k-map 204 of FIG. 2 are located in a manner inconsistent with the diagram of the 2-cube k-map 202.
  • FIG. 3A shows a four-variable Karnaugh map encoded by labeling each axis with a binary Gray code.
  • Map cells 300 of FIG. 3A correspond to the grid cells 301 of FIG. 3B.
  • the labeling method of FIG. 3B is a simplification of the method of FIG. 3A.
  • Grid cells 301 in FIG. 3B are distinguished by region identifiers 302.
  • Grid cells 301 in FIG. 3B within a particular region 302 have a logical value of one for the bit position in corresponding map cell 300 names of FIG. 3A.
  • FIGS. 4A-4B are a prior art method of visualizing the binary 5-cube and the binary 6-cube as k-maps. Clare, in the reference cited above, shows the 5-cube 400 and the 6-cube 402 copied and translated to the right 401 and downward 403, respectively.
  • FIG. 5 shows a device proposed by Karnaugh, to visualize the synthesis of a network of six variables:
  • the three-dimensional cube]. . . consists of four 6-inch plexiglass sheets supported at 11/2-inch intervals by rods . . . In using it we employ movable markers . . . The extension to seven variables is probably best accomplished by placing two cubes side by side . . . Eight variables can be handled with a set of four cubes, and nine variables require eight cubes. In the latter case it is convenient to make them so as to stack easily into two layers of four each. Beyond nine variables, the mental gymnastics required for synthesis will, in general, be daunting.
  • Images that are produced by sensing objects through a form of radiant energy, for example, . . . are inherently continuous.
  • Computer representation of 3D images requires a sampling of the volume to extract a discrete set of values . . .
  • the cubic space is subdivided into eight subcubes (octants) of equal volume. Each of these octants will either be homogeneous (e.g., uniform attenuation) or have some nonuniformity.
  • the heterogeneous octants are further divided into suboctants. This procedure is repeated as long as necessary until we obtain blocks (possibly single voxels) of uniform properties.
  • 2N processors are consecutively numbered (or tagged) by binary integers (e.g., bit strings of length N) from 0 through 2n-1.
  • Each processor is connected to all of the other processors whose binary tags differ from its own by exactly one bit. Topologically, this arrangement places processors at the vertices (corners) of an N-dimensional cube.
  • the actual layout of the processors is a linear arrangement in a card cage or a planar arrangement on a printed circuit board; the cube connections are made by wires, conducting layers, or a backplane.
  • FIGS. 6A-6D are diagrams of a binary 6-cube encoded in accordance with prior art h-cube replication methods.
  • Seitz in the article, "The Cosmic Cube," Communications of the ACM, Vol. 28, No. 1, January 1985, p. 22, describes 64 computers ". . . connected by a network of communication channels in the plan, of a binary 6-cube.”
  • the interconnection pattern of FIG. 6A is similar to that used by Seitz.
  • Each node of FIG. 6B is linked by arcs to six other nodes.
  • FIGS. 10A-10B show a diagram of a four-dimensional hypercube, called a binary 4-cube. Each element of FIG. 10A is referred to as a node 1000. The dimensions of FIG. 10A are represented as a link 1001 connecting nodes 1000. The binary 4-cube is shown partitioned 1004 in FIG. 10B as two subspaces: subspace 0CBA 1002 and subspace 1CBA 1003.
  • Hypercubes of arbitrary dimension can be made using a linear arrangement with connecting wires (FIG. 2).
  • the cube of each dimension is obtained by replicating the one of next lower dimension, then connecting corresponding nodes.
  • the node names resulting from such hypercube interconnection schemes correspond to prior art two-dimensional recursive indexing methods, similar to the method described by Srihari in his article referenced above.
  • Recursive indexing has been independently discovered by practitioners in diverse fields. Recursive indexing is not extendable to generalized N-dimensional resolution, where the resolution of each dimension is permitted to differ.
  • a hypercube, when projected onto a plane using the method of recursive indexing is routinely referred to in prior art literature as a binary n-cube.
  • Such topological ambiguity frustrates the mechanized visualization of higher-order, N-dimensional spaces.
  • Marihugh and Anderson in their article describe a geometric model which is intended to visually aid the analysis of binary functions. Their method is based on geometrically transforming the coordinates of a hypercube onto a plane.
  • the H diagram method of visualizing the coordinates of a binary hypercube by transforming its coordinates onto a plane is not extendable to generalized N-dimensional space, where the resolution of each dimension is permitted to differ.
  • Sivilotti in a paper "A Dynamically Configurable Architecture For Prototyping Analog Circuits," in Advanced Research in VLSI, Proceedings of the Fifth MIT Conference, 1988, MIT, p.
  • Sivilotti also refers to indirect element name (switch address) transformation as the ". . . mapping between hierarchical interconnect matrix coordinates and flat Cartesian coordinates performed by the embedding compiler.”
  • Colorimetry is a perceptual science which studies and attempts to quantify how the human visual system perceives color. This study of perception has resulted in various systems of color representation, each intending to reduce problems associated with subjective color selection and reproduction.
  • Six color systems often used in association with computer-related information display include: the Munsell color system, HSV hexcone, HSL double hexcone, HSL double cone, HSL cylinder, and the RGB color cube.
  • the RGB color cube represents the red, green, and blue monitor primaries as orthogonal axes.
  • the colors that are displayable on the monitor are within the cube from (0, 0, 0) to (1, 1, 1).
  • the neutral axis is a (diagonal) line from the black point (0, 0, 0) to the white point (1, 1, 1).
  • the color cube has been referred to in the literature as a "natural" coordinate system in the sense that the three color components are mapped into an orthogonal coordinate system in the same fashion as three-dimensional geometry.
  • Color representations used in computer graphics are closely linked to both the color reproduction device and to a method of color selection. Uniform color spaces can be used to decide at what level of resolution the color information should be encoded. Two-dimensional data plots, for example, require uniform color spaces to select color scales.
  • the pigment gamut used to derive color spaces is generally smaller than the gamut of a color monitor and the pigment gamut is irregular. According to Meyer and Greenburg, referenced above (p. 260), ". . . this makes it difficult to find color scales that incorporate the most brilliant monitor colors.”
  • CTR electronic display device technology presents a detailed description of CRT electronic display device technology.
  • the number of colors that can be produced on a CRT display depends on the number of steps of gray level obtainable for each phosphor (compounds that emit light when bombarded by electrons). If the electron gun can be stepped over four levels (2 bits), the resulting palette has sixty-four colors.
  • Some systems currently available are capable of 1024 steps of gray from each gun (10 bits). Systems capable of 256 steps of gray from each gun (8 bits) are more common, however. Such systems can produce a palette of over 16 million unique combinations.
  • a total of about three million discriminable colors can be produced in a visual display; that is, colors that are recognizably different when placed adjacent to one another.
  • the palette shrinks to about 7000 when colors located at different screen areas must be immediately recognized as different from one another. . . .
  • the obtainable level of saturation for additively-mixed colors can be extended by increasing the number of primaries . . .
  • a diffraction grating 701 is used to spread out a spectrum of light from the input fiber 700 and focus specific wavelengths in that spectrum onto fibers in a linear array 702-706. Conversely, if the outputs were reversed, the grating 701 would combine the five wavelengths 702-706 into a single output at the top fiber 700.
  • FIG. 8 shows prior art prism input coupling 800 and grating output coupling 803 of an external light beam 80 into a thin-film waveguide 802. By reversing the incident 80 and output 804 beam directions the roles of the prism 800 and grating 803 couplers are interchanged. Streifer further describes optical integrated circuit (OIC) switching and modulation applications:
  • Both lithium niobate and gallium arsenide belong to the family of electro-optically active crystals. When an electric field is applied to these materials, their refractive indices are modified. . . . If the waveguides are voltages to the electrodes will cause the transfer of optical power from one waveguide to its neighbor with high efficiency and little residual power in the initial guide.
  • FIG. 9 shows a prior art "4 by 4" directional coupler switching network in which each of four input optical signals 900 may be switched to any one of four output ports 904.
  • Such an optical integrated circuit serves to interconnect four computers through optical fibers.
  • Switches are in effect modulators.
  • Prior art modulation is a process in which information is encoded onto an optical wave. According to Streifer, referenced above, ". . . Pulse modulation results simply by interrupting or connecting a light wave in a manner intelligible to a receiver. By transferring light into or out of a waveguide in response to an electric signal at a switching electrode, the output optical wave becomes modulated; that is the switch acts as a modulator.”
  • the separation of problem space formulation and formulation of solution strategies which navigate problem space relationships requires a mechanized method which can be visualized.
  • the invention disclosed herein permits a problem characterized by attributes comprising an object description to be transformed into a mixed-resolution, N-dimensional object space of encoded attribute relationships which can be visualized. Accordingly, the foregoing discussion of the prior art is representative of the problem of representing mixed-resolution, N-dimensional objects and spaces.
  • An object of the invention is to mechanize the generation of mixed-resolution, N-dimensional object spaces related to complex problems with a large number of variables, where the number of variables is not limited by the method.
  • An additional object of the invention is to mechanize the visualization of mixed-resolution, N-dimensional object spaces related to complex problems with a large number of variables, where the number of variables is not limited by the method.
  • Another object of the invention is to represent logical objects visually such as logical color specifications and visual color sensations.
  • a further object of the invention is concurrent control of a plurality of views of one or more object spaces.
  • a still further object of the invention is an apparatus described herein as the kernel of a modular object description system.
  • An object of the invention is to dynamically control the logical representation and the visual expression of object descriptions in an object space.
  • Another object of the invention is concurrent control of a plurality of transition paths in an object space.
  • An object of the invention is concurrent control of a plurality of element relations in an object space.
  • a further object of the invention is concurrent control of a plurality of regions in an object space.
  • Object spaces representing very simple object descriptions can be formed manually and, in a few instances, mentally; however, description spaces of actual systems quickly exceed the feasible limits of mental visualization and manual procedures.
  • the present invention therefore, mechanizes higher order relationships between attributes which describe a particular problem domain.
  • the novel method and apparatus disclosed herein transforms an abstract object description defined by a set of attributes and their corresponding values into a mixed-resolution, N-dimensional object space.
  • the mixed-resolution, N-dimensional object space represents a mechanized, logically encoded expression of attribute relationships that can be visualized. Therefore, an illustrative embodiment of the present invention is an apparatus that is part virtual machine, providing an appropriate level of application independence and device transparency.
  • a process for generating and visualizing mixed-resolution, N-dimensional object spaces using a computing device such as a computer
  • the computing device may be of the type comprising means for inputting, storing and processing data and commands, means for generating a logical representation of the N-dimensional object space in response to the stored data and commands, display logic for generating a virtual image representing the N-dimensional object space in response to the stored data and commands, and display means for displaying a visible representation of the virtual image.
  • the process starts with the user inputting to the computing device the attributes and the computing device generating from the attributes a frame for the N-dimensional object space.
  • the bits of the frame are then interleaved to generate an object descriptor.
  • the computing device From the frame and the object descriptor, the computing device generates dimensional-spatial locations of the N-dimensional object space.
  • the computing device also generates object selectors which correspond to interleaved frame data for each dimensional-spatial location in the N-dimensional object space.
  • the computing device generates a virtual image of the N-dimensional object space from the dimensional-spatial locations and the object selectors.
  • a user or an application procedure selects a logical region of the virtual image.
  • the process may further include the step of displaying the selected logical region of the virtual image of the N-dimensional object space on the display means.
  • the process further includes having the computing device generate, from the frame and the object descriptor, resolution-spatial locations for resolution levels of each of the N dimensions for a mixed-resolution, N-dimensional object space. Subsequently an object selector is generated from the frame data for each spatial location in the mixed-resolution, N-dimensional object space. A virtual image of the N-dimensional object space is generated from the resolution-spatial locations and the dimensional-spatial locations. A user or an application procedure selects a logical region of the virtual image. The process may including using the computing device for displaying the selected logical region of the virtual image of the mixed-resolution, N-dimensional object space on the display means.
  • the present invention alternatively may be embodied as an apparatus for generation and visualization of mixed-resolution, N-dimensional object spaces.
  • a user specifies a particular set of attributes defining dimensions and resolution levels.
  • an application procedure specifies a particular set of attributes defining dimensions and resolution levels.
  • the apparatus transforms analog signals into a digital form which specifies a particular set of attributes defining dimensions and resolution levels.
  • the apparatus includes means for generating a frame from the specified attributes for the N-dimensional object space.
  • Means for interleaving bits generates an object descriptor which corresponds to interleaved frame data.
  • the present invention uses means for generating dimensional-spatial locations of the N-dimensional object space.
  • the frame data is used to generate an object selector for each dimensional-spatial location in the N-dimensional object space.
  • the dimensional-spatial locations and the object selectors are used to generate a virtual image of the N-dimensional object space. A logical region or related of the virtual image is selected.
  • Display means may display the selected logical region of the virtual image of the N-dimensional object space.
  • the apparatus of the present invention additionally may include means for generating resolution-spatial locations for resolution levels of each of the N dimensions for a mixed-resolution, N-dimensional object space using the frame and the object descriptor.
  • the frame and object descriptor are used to generate an object selector for each resolution-spatial location in the mixed-resolution, N-dimensional object space.
  • a virtual image of the N-dimensional object space is generated, and means is provided for selecting a logical region of the virtual image.
  • Frame data for a particular object are used to generate a single object selector to reference a particular location in the mixed-resolution, N-dimensional object space.
  • An illustrative example of the present invention relates to color perception, color specification, and color spaces; and, in particular, to the production and visualization of uniform color spaces.
  • a color naming method for controlling RGB values by indirectly specifying RGB signal voltages and visualizing the resulting distribution of perceivable colors in the RGB color space is presented in accordance with the method disclosed herein.
  • the color naming method used in accordance with the present invention is the process by which the name of a particular color experience is encoded for both the purpose of uniform color selection and the purpose of reproduction on an electronic display.
  • the system of color representation used to form a uniform color space is to name colors in terms of the additive relations of red, green and blue.
  • the resultant RGB system specifies a trio of values ranging from 0 to 1 or 0% to 100% for each of the three primaries.
  • the color relationships that result form a cube.
  • the RGB system is a simple and direct approach to the problem of color description that incorporates the principles of additive color mixture; that is, the user specifies color directly in terms of the electrical activity that the specification will induce. In the reference by Murch, cited in the Description of the Prior Art, the difficulty of specifying additive color relationships is discussed:
  • the novel method for generating, controlling and visualizing the distribution of perceivable colors in a RGB color space is described below.
  • a primary aspect of the method disclosed herein is that the encoded pattern of bits which specifies (physical) RGB signal voltages also (logically) names a particular location in a displayable uniform color space.
  • Another aspect of the method disclosed herein is that the logical naming method of invention illustrated by the color space example may be generalized to include a novel method for optical modulation.
  • FIGS. 1A-1E are diagrams of the binary 3-cube "unfolded" in accordance with prior art methods
  • FIGS. 2A-2F are a prior art representation of n-cubes as k-maps
  • FIGS. 3A-3B are a prior art representations of a four-variable Karnaugh map
  • FIGS. 4A-4B are a prior art representation of a binary 5-cube and a binary 6-cube
  • FIG. 5 shows a prior art device for extending the binary 6-cube to visualize higher order spaces
  • FIGS. 6A-6D are a diagrams of a binary 6-cube encoded in accordance with prior art two-dimensional recursive indexing methods
  • FIG. 7 shows prior art distribution of multiple wavelengths to separate fibers
  • FIG. 8 shows prior art prism input coupling and grating output coupling of an external light beam into a thin-film waveguide
  • FIG. 9 shows a prior art "4 by 4" directional coupler switch
  • FIGS. 10A-10B are prior art diagrams of a four-dimensional hypercube
  • FIGS. 11A-11C show an intuitive procedure for generating spaces, spatial element linkage, and a binary 4-cube projected onto a plane
  • FIG. 12 is a flow chart for the case of user-specified attributes which shows the process of the invention.
  • FIGS. 13A-13C show expressions of a zero-cube
  • FIGS. 14A-14C show expressions of a one-dimensional, object space
  • FIGS. 15A-15C show expressions of a two-dimensional, object space
  • FIGS. 16A-16C show expressions of a three-dimensional, object space
  • FIGS. 17A-16C show expressions of a four-dimensional, object space
  • FIGS. 18A-16C show expressions of a five-dimensional, object space
  • FIGS. 19A-19C show expressions of a six-dimensional, object space
  • FIGS. 20A-20C are diagrams of a k-ary one-dimensional, object space
  • FIGS. 21A-21B are diagrams of 4-dimensional object spaces
  • FIGS. 22A-22C are diagrams of a mixed-resolution, 4-dimensional object space derived from a binary, 4-dimensional object space;
  • FIG. 23 is a functional diagram of the object description process
  • FIGS. 24A-24B show block diagrams of physical modules in an object description system
  • FIG. 25 shows a functional module of an object description system
  • FIG. 26A-26H show the object space configurations formed by the 4-bit frame logic module
  • FIGS. 27A-27C are diagrams of an eight-element RGB color space
  • FIGS. 28A-28C are diagrams of a sixty-four-element RGB color space
  • FIG. 29A-29C show relationships between three-dimensional spaces with different resolutions
  • FIGS. 30 shows a graph of matching curves for 445 nm, 535 nm, and 630 nm control sources.
  • FIGS. 31A-31C show how percentages of spectral intensities over a range of values for each primary are determined in a sixty-four element RGB color space.
  • the present invention mechanizes a novel representation of that system's description.
  • Object descriptions have meaning, that is, they refer to or describe some system with certain physical or conceptual properties.
  • the objects may be particular color sensations described in terms of attributes such as: red; green; blue; which define a color space.
  • the objects may be a particular coherent light source described in terms of its lightwave components, which define a signal space.
  • the significant aspect of system description is that the actual description is one selected from a set possible descriptions.
  • the invention is a general apparatus and method, designed to operate for each possible problem selection, not just the one which will actually be chosen since this is unknown at the time of design.
  • the process of the present invention enables representing sensed physical phenomena logically and logical objects visually.
  • Most of the prior art methods referred to in Description of the Prior Art sought to visualize some aspect of a problem-solving process by mapping logical object descriptions onto visual space.
  • the process which transforms an object description into an object space is directed by object descriptions in accordance with the method of the present invention.
  • Object expressions are represented by a unique binary-coded name which directly correspond to a position in the object space of the present invention.
  • the present invention is first described as the method of reflecting binary N-dimensional object spaces. Then the present invention is described as the generalized method of reflecting mixed-resolution, N-dimensional object spaces.
  • the process of the present invention results in an interleaving of the N-dimensions. Bit interleaving is often employed in structuring data, as well as part of the data representation itself. Samet in his book, The Design and Analysis of Spatial Data Structures, 1989, Addison Wesley, N.Y., p. 109, states:
  • bit interleaving makes it possible to balance a data base of multidimensional point data dynamically. It leads to logarithmic insertion, deletion and search algorithms. It does have drawbacks, however. First, and most serious, is that bit interleaving is not performed efficiently on general computers. Its complexity depends on the total number of bits in the keys.
  • Object a structural and/or behavioral expression of some real-world or imaginary phenomenon.
  • Object descriptor a collection of interleaved logically encoded attributes which describes a schema for a particular kind of object expression describing the object space.
  • Object selector a collection of interleaved logically encoded attribute values associated with the descriptor of a specific object expression, defining a location in the object space which names a specific attribute relation.
  • Object An expression of bit-interleaved names for the set of possible relationship between a plurality of attributes which describe source real-world or imaginary phenomenon.
  • Object name a logically encoded representation of an object selector in an object space.
  • Visual space a graphical expression for a logical space or object names projected onto a plane.
  • Quantization assigning a logical name to a range of values.
  • Object Frame describes the format of an object descriptor, where each attribute (dimension) is denoted by a “1” followed by "Os" representing the additional bits of binary resolution.
  • Frame Data a collection of concatenated attribute values corresponding to their respective bit positions in an object frame.
  • the present invention provides a process for visualizing N-dimensional, object space using a computing device such as a computer.
  • the computing device may be of the type comprising means for inputting storing and processing data and commands, means for generating a logical representation of the N-dimensional object space in response to the stored data and commands, frame logic for generating a virtual image representing the N-dimensional, object space in response to the stored data and commands, and display means for displaying a visible representation of the virtual image.
  • the process uses the computing device.
  • FIGS. 11A-11C show an intuitive procedure for reflecting a mixed-resolution, 4-dimensional, object space onto a plane
  • the attributes describe the problem.
  • a color display for example, may have the attributes of three primary colors: red; green; and blue. Each attribute corresponds to a dimension of the problem.
  • the computer generates 1202, from the user specified attributes, a frame for the N-dimensional object space.
  • the frame is a coded representation of attribute descriptions for a particular problem domain.
  • each attribute corresponding to a primary hue is described by a bitfield in the frame.
  • the first bit of each bitfield is always a logical one.
  • Subsequent bits in a given bitfield are logical zeros. Each logical zero represents an additional bit of resolution.
  • a three-dimensional object space with two bits resolution on each dimension would have a frame (0, 1, 0, 1, 0, 1).
  • Each 1-bit represents each dimension, and the 0-bit placed before the corresponding 1-bit indicates a second bit of resolution.
  • two bits of resolution on each of three dimensions might correspond to four levels of intensity for each of the primary colors.
  • a three-dimensional, object space with three bits of resolution on the first dimension, one bit of resolution on the second dimension, and two bits of resolution on the third dimension would have the frame: (0, 1, 1, 0, 0, 1).
  • the right three bits might represent eight levels of resolution or saturation of the red attribute; the center bit might represent two levels resolution or saturation of the green attribute; and the left two bits might represent four levels of resolution or saturation of the blue attribute.
  • object space with one bit resolution on each dimension would have a frame (1, 1, 1).
  • Each bit, from right to left, might represent the red attribute, the green attribute and the blue attribute, respectively.
  • the frame is a positional notation which denotes the number of attributes and the resolution of each attribute.
  • the frame data are the values or sense of each bit position in a given frame.
  • the bits of the frame are interleaved 1203 to generate an object descriptor.
  • the object descriptor is (0, 0, 0, 1, 1, 1) for the frame (0, 1, 0, 1, 0, 1).
  • the object descriptor is (0, 0, 0, 1, 1, 1) for the frame (0, 1, 1, 0, 0, 1).
  • the object descriptor is (1, 1, 1) for the frame (1, 1, 1).
  • the computing device generates 1204 from the frame and the object descriptor, dimensional-spatial locations of the N-dimensional object space. For each 1-bit from the object description, the computing device generates a dimension of dimensional-spatial locations. The dimensional-spatial locations correspond to the attributes of the problem.
  • FIGS. 13 through 19 illustrate n-cube projection in accordance with methods of the invention now further described as a process to mechanize and visualize reflected N-dimensional-object spaces for any N, where N is a positive integer. It should be noted that each of the FIGS. 13 through 19 show three expressions of n-cube element configurations.
  • the 1-d, 1-bit object space of FIGS. 14A-14C can be visualized as a linear region comprising two elements "named" logical zero and logical one, respectively.
  • the linear region of FIGS. 14A-14C is generated by reflecting a first 0-dimensional object space named "0" to the right. Thereby, a second 0-dimensional object space named "0" is produced.
  • the name of a dimensional-spatial location is called an object selector.
  • FIGS. 15 through 19 show the progressive projection of reflected binary n-cubes, where N varies from two to six.
  • each dimensional-spatial location is represented as a cell, which is drawn as a square.
  • N-dimensional object spaces are reflected as regions in an orthogonal direction determined by control signals from an apparatus described below.
  • the values of the n-1 rightmost object selector bits in a second (reflected) region are the same as the n-1 rightmost object selector bits of the corresponding object selectors which comprise a first region (i.e, where N is the number of bits in an object selector).
  • the value of the leftmost object selector bit of a first region is always a logical zero, and the leftmost selector bit of a second region is always a logical one.
  • the 2-dimensional, 1-bit object space of FIGS. 15A-15C can be visualized as two linear regions comprising four elements "named" in accordance with a reflected binary Gray code (e.g., 00, 01, 11, 10).
  • the object space of FIGS. 15A-15C is generated by reflecting a first linear region upward. Thereby, producing a second (reflected) linear region. The resulting object space can be visualized as a square region.
  • the corresponding object selectors in each linear region have the same value in the rightmost bit position; however, the values differ in the leftmost bit position.
  • the leftmost bit of the first linear region's object selectors is a logical zero.
  • the leftmost bit of the second (reflected) linear region's object selectors is a logical one.
  • the 3-dimensional, 1-bit object space of FIGS. 16A-16C can be visualized as two square regions, each comprising four elements. These eight elements are named in accordance with a reflected binary Gray code (e.g., 000, 001, 011, 010, 110, 111, 101, 100).
  • the object space of FIGS. 16A-16C is generated by reflecting a first square region comprising four elements to the left. Thereby, a second square (reflected) region is produced.
  • the values of the two rightmost object selector bits in the second (reflected) square region are the same as the two rightmost bits of the corresponding object selectors, which comprise the first square region.
  • the value of the leftmost object selector bit of the first square region is a logical zero.
  • the value of the leftmost object selector bit of the second square region is a logical one.
  • the 4-dimensional, 1-bit object space of FIGS. 17A-17C can be visualized as two rectangular regions, each comprising eight elements. These sixteen elements are named in accordance with a reflected binary Gray code.
  • the object space of FIGS. 17A-17C is generated by reflecting a first rectangular region comprising eight elements downward. Thereby, a second rectangular (reflected) region is produced.
  • the 5-dimensional, 1-bit object space of FIGS. 18A-18C can be visualized as two square regions, each comprising sixteen elements. These thirty-two elements are named as described above in accordance with a reflected binary Gray code.
  • the object space of FIGS. 18A-18C is generated by reflecting a first square region comprising sixteen elements to the right. Thereby, a second square (reflected) region is produced.
  • FIGS. 19A-19C The binary 6-cube is FIGS. 19A-19C is referred to herein as a 6-dimensional object space with one bit of resolution.
  • the 6-dimensional, 1-bit object space of FIGS. 19A-19C can be visualized as two rectangular regions, each comprising thirty-two elements. These sixty-four elements are named in accordance with a reflected binary Gray code as described above.
  • the object space of FIGS. 19A-19C by reflecting a first rectangular region comprising thirty-two elements upward. Thereby, a second rectangular (reflected) region is produced.
  • the process of naming spatial elements for any N-dimensional space is intuitively understood as a "function" of reflecting its subspaces.
  • the novel method of the present invention can be used for visualizing progressive space generation for any N-dimensional, object space.
  • the dimensional-spatial locations can be produced by reflecting cells right, up, left, down, right, up, left, down, etc., in what is considered a counter-clockwise direction.
  • the dimensional-spatial locations can be produced by reflecting cells to the left, up, right, down, left, up, right, down, etc., in what is considered a clockwise direction.
  • the dimensional-spatial locations may be reflected in a clockwise or counter-clockwise direction.
  • the dimensional-spatial locations can be produced by reflecting cells in a single direction or selected direction.
  • the counter-clockwise embodiment for producing dimensional-spatial locations is used throughout this disclosure, with the understanding that the alternative embodiments produce semantically equivalent dimensional-spatial locations.
  • the computing device gets 1206 the first attribute bitfield in the frame. From this bitfield, the computing device determines 1207 whether resolution-spatial locations need to be generated from this bitfield. If no resolution-spatial locations are to be generated, then the computing device determines 1206 whether this is the last bitfield of the frame. If yes, then the computing device checks 1211 if there are any additional resolution-spatial locations to be generated for any bitfield. If no resolution levels are required, then the computing device generates 1212 an object selector which corresponds to interleaved frame data for each dimensional-spatial location in the N-dimensional object space. The object selectors are an interleaved bitfield of the frame data. The object selectors define a location in the cells representing the dimensional-spatial locations.
  • the computing device If all object selectors have been generated 1213 for all the dimensional-spatial locations for the N-dimensional, object space, then the computing device generates 1214 a virtual image of the N-dimensional, object space from the dimensional-spatial locations and the object selectors.
  • a user or application procedure may select 1215 a logical region of the virtual image for machine control, display, or other application-driven function.
  • the process further may include using the computing device for displaying the selected logical region of the virtual image of the N-dimensional, object space on the display means.
  • the process additionally may use the computing device for generating 1208, from the frame and the object descriptor, resolution-spatial locations for resolution levels of each of the N dimensions for a mixed-resolution, N-dimensional, object space.
  • FIGS. 20-22 illustratively show the generation of resolution-spatial locations.
  • the number of elements in a k-ary 1-cube is determined by the number of bits of resolution as a power of two.
  • a 4-ary 1-cube with two bits of resolution has four elements and an 8-ary 1-cube with three bits of resolution has eight elements.
  • the element transition sequences correspond to the primary form of the reflected binary code, but may be interpreted as a reflected k-ary code.
  • FIG. 20A shows a binary 1-cube referred to herein as a 1-dimensional object space with one bit of resolution.
  • the 1-dimensional, 1-bit object space of FIG. 20A comprises two object selectors named "0" and "1" respectively.
  • the object selectors of a 1-dimensional, 1-bit object space represent dimensional-spatial locations.
  • FIG. 20B illustrates a 1-dimensional object space with two bits of resolutions.
  • the original dimensional-spatial locations of FIG. 20A have been reflected to the right to increase the resolution in the direction of the first dimension. Note that the reflection for increased resolution is in the same direction as the reflection which generated the dimension.
  • the object selectors of the original dimensional-spatial locations have a 0-bit placed in front of them, and the newly generated resolution-spatial locations have the original object selectors reflected therein with a 1-bit placed in front of them.
  • FIG. 20C shows a 1-dimensional object space with three bits of resolution, which has been generated from the 1-dimensional, 2-bit object space of FIG. 20B.
  • object selectors from the 1-dimensional, 2-bit object space (2-ary 1-cube) have a 0-bit placed in front of them, and the object selectors generated by reflection have a 1-bit placed in front of them.
  • FIGS. 21A-21C are diagrams of 4-dimensional object spaces.
  • FIGS. 21A-21B shows a 4-dimensional object space with one bit of resolution.
  • FIG. 21C shows a 4-dimensional object space with two bits of resolution, in each dimension.
  • the resolution-spatial locations are generated. Accordingly, the sixteen dimensional-spatial locations for the four dimensions are reflected initially to the right to generate two levels of resolution for the first dimension. At this stage, there are thirty-two dimensional-spatial locations and resolution-spatial locations.
  • thirty-two resolution-spatial locations are generated by reflecting in an upward direction the combination of thirty-two dimensional-spatial locations and resolution-spatial locations. Now there are a total of sixty-four spatial locations.
  • the two level resolution-spatial locations for the third dimension are generated by reflecting sixty-four resolution-spatial locations to the left of the previously generated sixty-four spatial locations.
  • the two level resolution-spatial locations may be generated for the fourth dimension by reflecting 128 resolution-spatial locations in a downward direction from the mixture of 128 mixed-resolution spatial locations from the first, second, and third dimensions. Accordingly, a total of 256 spatial locations are generated for the 4d, 2-bit object space. Object selectors are generated in a similar fashion as previously described for each mixed-resolution spatial location.
  • FIGS. 22A-22C are diagrams of a mixed-resolution, 4-dimensional object space derived from a binary, 4-dimensional object space.
  • FIGS. 22A-22C again shows the 4-dimensional object space with one bit of resolution.
  • FIG. 22C shows a mixed-resolution, 4-dimensional object space.
  • a mixed-resolution object space the number of bits of resolution for each dimension is permitted to differ.
  • Prior art methods for naming elements of an object space can be characterized as container-oriented in that the number of addressable element locations are a function of the container's extent.
  • the method disclosed herein is characterized as content-addressable, in that, the extent and configuration of an object space is a function of its contents.
  • the first and third dimensions each have two bits of resolution and the second and fourth dimensions have only one bit of resolution. Therefore, the object selectors for the object space of FIG. 22C have a total of six bits.
  • the object space of FIG. 22C comprises sixty-four elements. It should be noted that prior art representations of higher-dimensional spaces typically fix the resolution for each dimension relative to the greatest number of bits required for any dimension. Thereby, an inefficient spatial representation is created.
  • the method of the present invention generates logical object spaces by a process which relies on a novel object description rather than a process of spatial decomposition. In the case of FIG. 22C, the dimensional-spatial locations for one bit of resolution in each of the four dimensions are generated. Then, the resolution-spatial locations for the first and the third dimensions are generated.
  • Sixteen dimensional-spatial locations comprise a first square region.
  • a first square region of sixteen elements is reflected to the right; thereby, producing a second (reflected) square region.
  • the direction (right) of reflection is determined by the additional bit of resolution in the first dimension.
  • This step results in a rectangular region comprising thirty-two elements.
  • the second dimension has no additional bits of resolution and the next orthogonal direction (upward) is bypassed.
  • the third dimension however, has an additional bit of resolution. Therefore, the rectangular region comprising thirty-two elements is reflected in the next orthogonal direction (left). Thereby a second (reflected) rectangular region is produced.
  • the resulting first and second (reflected) regions account for the sixty-four elements shown in the object space of FIG. 22C.
  • An object selector is generated 1212, as illustrated in FIG. 12, for each resolution-spatial location in the mixed-resolution, N-dimensional object space.
  • An object selector is generated 1213, from the resolution-spatial locations, the dimensional-spatial locations and the object selectors, a virtual image is generated 1214 of the N-dimensional object space.
  • a user or machine may select 1215 a logical region of the virtual image for use or display.
  • the computing device may display the selected logical region of the virtual image of the mixed-resolution, N-dimensional object space on the display means.
  • FIG. 23 shows a functional diagram of the object description process.
  • Four procedures comprise the object description process: expression 2301; quantization 2304; transformation 2307; and execution 2310.
  • expression 2301 a user inputs a domain 2300 of an object which is expressed 2301 as an object description 2302.
  • the object description is encoded as a set of attributes. Each attribute selected corresponds to one dimension of an N-dimensional, object space. The order in which the attributes are specified determines a sequence in which an object space is generated.
  • the range 2303 of possible values of each attribute is encoded by a quantization 2304 procedure which assigns a logical digital code to range 2303 of values.
  • the resolution is the degree of range 2303 of values.
  • the degree of range compression (e.g., scaling of values) is part of the attribute specification.
  • Coded attribute values correspond to the transition sequence of a reflected binary code. Intuitively, the most straightforward way of naming or coding an ordered set of objects, where each codeword is a unique sequence of binary digits, is to count in binary, but consecutive codewords usually differ by more than one bit position.
  • the maximum number of bits required to represent a coded attribute value defines its dimensional resolution.
  • the range 2303 of values associated with each dimension of the object description 2303 is quantized 2304 to form a coded object description 2305, called a frame 2306.
  • the format of a frame 2306 is a bit pattern read from the right that represents a contiguous sequence of coded attributes or bitfields.
  • the rightmost bit of each attribute's bitfield is a logical one denoting a spatial dimension. Additional bits of resolution for a given attribute, if any, are assigned a logical zero; e.g., (0 1, 0, 1) is a frame 2300 for coded object description representing two four-valued attributes.
  • the bits of the object frame 2306 are then transformed 2307 to form an interleaved object 2308 called a descriptor 2309.
  • the object descriptor represents the name format for specific object expressions.
  • a collection of coded attribute values associated with the interleaved from 2308 of a named object expression is called an object selector.
  • the object descriptor 2309 controls the execution process 2310 for forming a visual space 2311.
  • the bitwise control sequence can be understood by considering the interleaved object frame 2306 in an expanded form.
  • the number of dimensions N describing a unit object space is defined in the first interval of the expanded frame. Each subsequent interval extends the dimensional resolution of the object space 2311.
  • a blank interval position in the expanded object descriptor 2309 may be thought of as the termination of the spatial control sequence for that particular dimension.
  • a frame controller is the syntactic expression of a visual space.
  • a region controller is part virtual machine which determines semantic expression of an object space as a name space.
  • an illustrative embodiment of an object description system comprises a plurality of physical modules which may be operatively coupled in various logical configurations to efficiently mechanize the method of the present invention.
  • a computing device 2400 including an input device 2401, a processor 2402, memory 2403, and a display device 2404.
  • the input device 2401 may be a key board, computer port, or an application within a computer.
  • the processor 2402 is coupled between the input device 2401, memory 2403 and display device 2404.
  • FIG. 24B shows object module 2405 having object frame module 2406, object region module 2407, and object selector module 2408 operatively coupled to the computing device 2400.
  • Each object module 2405 comprises at least one register device having at least one storage cell; combinational logic devices which relate to the registers; data signal paths which link devices within a module and which link devices in different modules; and control signal paths which link devices within a module and which link devices in different modules.
  • the region module 2407 is operatively coupled to the input logic of the computing device 2 and the object frame module 2406.
  • the object region logic 2407 is used for selecting relations of the virtual image.
  • a user may specify semantic expressions for a particular set of attributes defining dimensions and resolution levels in the object space.
  • a user using the input device 2401 inputs the semantic expressions for the particular set of attributes of a problem for the mixed-resolution, N-dimensional, object space.
  • the input logic of the processor 2402 is operatively coupled to the input device 2401 and interfaces the input device 2401 with the memory 2403.
  • the frame logic 2407 interleaves the frame to generate an object descriptor.
  • the frame logic 2407 also generates, from the frame and the object descriptor, dimensional-spatial locations for N dimensions. From the frame and the object descriptor, the frame logic 2407 generates resolution-spatial locations for resolution levels of each of the N dimensions of the mixed-resolution, N dimensional object space.
  • the frame logic 2407 uses frame data to generate, for a particular spatial location, an object selector.
  • the object selector as previously described conforms to a primary form of a reflected binary code.
  • the frame logic 2407 uses the dimensional-spatial locations and the object selectors, the frame logic 2407 generates a virtual image of the N-dimensional, object space.
  • the computing device using region logic 2408 manipulates the virtual image with bit selectors.
  • the apparatus of the present invention may be used for visualizing a mixed-resolution, N-dimensional, object space.
  • the user specifies an object described by for a particular set of attributes defining dimensions and resolution levels in the object space.
  • the user inputs the object description for the N-dimensional, object space using the input device 2401.
  • the frame module 2406 interleaves the frame to generate an object descriptor, and it generates dimensional-spatial locations for N dimensions from the frame and the object descriptor.
  • the frame module 2406 also generates, for each dimensional-spatial location, an object selector. From the dimensional-spatial locations and the object selectors, the frame module 2406 also generates a virtual image of the N-dimensional object space.
  • the region module 2407 is used for selecting one or more elements of the virtual image.
  • the display map 2406 stores the selected region of the virtual image and display device 2410 displays the virtual image of the N-dimensional object space.
  • the frame module 2406 generates, from the frame and the object descriptor, resolution-spatial locations for resolution levels of each of the N dimensions for a mixed-resolution, N dimensional object space.
  • An object description system can be regarded as an implementation of procedures that transforms mixed-resolution, N-dimensional object description into a mechanical form which can be logically manipulated.
  • An object description system also can be regarded as an implementation of procedures that transforms mixed-resolution, N-dimensional object descriptions into a perceptible form which can be presented as an image on a graphics display device.
  • the functional model of an object description system comprises a plurality of logical processors, which perform the correlative functions corresponding to the reference numerals of FIG. 12:
  • descriptor processor 2503 (1203/1204)
  • dimension-location processor 2504 (1204/1205)
  • a logical processor in the functional model corresponds to one or more physical modules, and two logical processors in the functional model may share a physical module.
  • representations of object spaces may exist in one or more different memories.
  • a plurality of such object description systems may be operatively coupled in various logical configurations dictated by the conceptual problem domain, enabling concurrent manipulation of a plurality of object space descriptions or concurrent manipulation of a plurality of views of a particular object space description.
  • FIG. 26A-26H shows the object space configurations formed by the 4-bit frame logic module.
  • Each object space 2602 shown in FIGS. 26A through 26H is associated with a diagram of its object frame selector 2600 and the logical names of their frame and interleaved frame 2603.
  • the logical names of the frame and interleave frame 2601 shown in FIGS. 26E through 26H are the same, resulting in the practical observation that the object frames for these spaces are in their interleaved form.
  • Visible light is a small segment of the continuum of electromagnetic radiation, which includes, for example, radio waves, radar, microwaves, infrared and ultraviolet light, x-rays, and gamma rays.
  • a color representation system determines the location of a particular color sensation in a visual space, called the logical color space.
  • the system is a color representation system; the input is white light; and the response is a color space generated in accordance with the method of the present invention.
  • a color representation system determines the location of a particular color sensation in a visual space called the color space.
  • Color space expressions indirectly produce physical device control signals for a color display.
  • the RGB color cube represents red, green, and blue primaries as orthogonal axes.
  • the displayable colors are within the cube from (0, 0, 0) to (1, 1, 1).
  • the neutral axis is a (diagonal) line from The black point (0, 0, 0) to the white point (1, 1, 1).
  • the color cube has been referred to in the literature as a "natural" coordinate system in the sense that the three color components are mapped into an orthogonal coordinate system in the same fashion as three-dimensional geometry.
  • Color specification means interactive visualization and control of the perceptual color gamuts (range of producible colors) of color display devices.
  • An ideal color model should accomplish intuitive addressability; uniformity; independent control of lightness and chromatic contrast; display device characterization in perceptual terms; and a basis is for naming color specifications.
  • Intuitive addressability is the specification of color representations in perceptual terms.
  • Perceptual specifications may include, by way of example, hue, saturation and intensity.
  • Hue is the basic component of color and is primarily responsible for a specific color sensation (e.g., red, green, blue, etc.).
  • Saturation is most closely related to the number of wavelengths contributing to a color sensation. Saturation depends on the relative dominance of a pure hue in a color specification. Intensity is an increased level of illumination permitting a broader range of hues to be visible.
  • Uniformity is the regular representation of gradations in perceived color, due to the perceptual relationship of color expressions. Independent control of lightness and chromatic contrast is the opportunity to expand chromatic contrast independently of intensity or vice versa.
  • Display device characterization in perceptual terms chooses appropriate display representations and controls their production.
  • a basis for naming color specifications is the opportunity to use a consistent method of color referencing to construct multidimensional models of process expressions in terms of spectral descriptors.
  • the illustrative example of the invention applied to the problem of color space description teaches a method for representing visual color sensations logically and reproducing logical color spaces visually.
  • Color specification and color space organization conventionally involve levels of computational indirection between the specification of color in terms of its perceptual attributes (e.g., hue, saturation and intensity) and subsequent production of electronic color signals.
  • the process enables the description of a logical color space expressed in terms of perceptual color attributes to be directly realized in terms of a given display device's physical color space.
  • the approach to the problem is a descriptive specification of color space component relationships.
  • the domain description of a color representation system is the human visual system's response to a limited portion of the electromagnetic spectrum called visible light.
  • Light generally refers to electromagnetic radiation from 380 nm to 770 nm.
  • the observed color of light results from a mixture of intensities at different wavelengths.
  • the rate of change in intensity for a given control source is a function of wavelengths.
  • the graph of intensity as a function of wavelength is the spectral curve for a given test color.
  • This graph represents a schematic for determining control light intensities for a given test color spectral curve.
  • Each control source spectral curve corresponds to a dimensional component of the color space domain. Colors mixed in a fashion in which bands of wavelengths are added to one another is called an additive color mixture.
  • the range of dimensional resolution is determined by one or more bits for each dimension. The number of bits specified for each dimension may differ. Two bits of resolution (e.g., four values) are specified for each primary in the RGB color space generated below.
  • spectral sampling means reducing a spectral curve to a set of sample values for subsequent color computations.
  • a logical color space (e.g., a space of color names) is performed as follows.
  • the frame is a coded representation of user-specified attribute descriptions for a problem domain.
  • each attribute corresponding to a primary hue is described by a bitfield in the frame.
  • the first bit of each bitfield is always a logical one.
  • Subsequent bits in a given bitfield are logical zeros. Each logical zero represents an additional bit of resolution.
  • a frame "010101" comprises three two-bit bitfields where: the rightmost pair of bits represents the red attribute; the center pair of bits represents the green attribute; and the leftmost pair of bits represents the blue attribute.
  • the primary function of a frame is as an interpreter which distinguishes between the possible meanings of an object descriptor or an object selector.
  • the object descriptor is the result of a transformation of a frame where the bits of each frame bitfield are interleaved.
  • the result is the object descriptor "000111.”
  • the primary function of an object descriptor is its role in generating N-dimensional object spaces. Using the frame to distinguish dimensional bits from resolution bits, the object descriptor determines the orthogonal generation of N-dimensional object spaces.
  • the first cycle is the order of interpretation of the object descriptor.
  • Object descriptor bits are logically grouped into dimensional intervals, e.g., "000 111". Each dimensional interval is processed as a cycle beginning at the spatial origin.
  • a second cycle associated with the orthogonal generation of N-dimensional object spaces is the order of reflection for generating the logical selector names.
  • the steps of the reflection cycle may correspond to the four orthogonal directions: right, up, left, and down.
  • a counterclockwise rather than a clockwise cycle was arbitrarily chosen, but the chosen direction must be strictly adhered to. If the number of dimensions is greater than four, then the reflection process continues in the next orthogonal direction for each non-null position in an expanded form of the object descriptor intervals.
  • the expanded form of an object descriptor inserts null place holders for attributes in the object descriptor whose resolution is less than others in a given interval.
  • a frame is a positional notation which denotes the number of the values or sense of each bit position in a given frame.
  • the rightmost bitfield of frame data "10” represents a value for a particular intensity of the red attribute in a color specification.
  • the object selector is a transformation of frame data where the frame data is interleaved.
  • the result of interleaving frame data "000010” is the object selector "001000.”
  • the name of each location in an N-dimensional space corresponds to an object selector.
  • FIGS. 27-31 show an illustrative example of a color representation system in accordance with the method of the present invention.
  • FIGS. 27A-27C show how the name space elements of a binary RGB color cube are projected onto a plane in accordance with the method of the present invention.
  • Each axis 2701 of the RGB color cube corresponds to a color primary.
  • Each node 2700, 2702 of the RGB color cube corresponds to a particular color sensation or element 2703 in a logical color space.
  • the name of each color sensation of an RGB color space corresponds to a particular element location 2702 in a logical color space.
  • FIG. 27C shows how the elements, name space labels, of a binary RGB color space are labeled.
  • the vertical regions labeled "R” 2704 contain elements whose rightmost bit position is set.
  • the horizontal region labeled “G” 2705 contains elements whose middle bit position is set.
  • the left half labeled "B” 2706 contain elements whose leftmost bit position is set.
  • FIGS. 28A-28C show the elements of a sixty-four element RGB color space.
  • FIG. 28B shows how the elements of a sixty-four element RGB color space are labeled.
  • FIG. 28C shows the object selectors of a sixty-four element RGB color space which correspond to the logical names of each color sensation.
  • FIGS. 29A-29C show the relationships between three-dimensional spaces with different resolutions.
  • FIG. 30 shows a graph of the resulting matching curves for 445 nm, 535 nm, and 630 nm control sources.
  • FIGS. 31A-31C show how percentages of spectral intensities over a range of values for each primary are determined in a sixty-four element RGB color space, using the graph of matching curves of FIG. 30.
  • Manipulation of a logical color space is accomplished by methods associated with a particular logical view, such as: elements; relations; paths; regions; and subspaces. Referencing a particular color sensation as an element of a logical color space may be accomplished in two ways: reference by value or reference by location.
  • Reference by value means a user or an application process provides a description of a particular color sensation in terms of its component hues and their respective intensities, typically as Frame data.
  • frame data correspond to the value or sense of each bit position in a given frame. For example, given the frame "010101" and frame data "000010" the rightmost bitfield of frame data "10" represents a value for a particular intensity of the red attribute in a color specification.
  • Reference by location means a user or an application process selects a particular color sensation in terms of its location; either indirectly by index (e.g., palette entry) or directly by its selector.
  • index e.g., palette entry
  • the object selector is a transformation of frame data where the bits of each frame data bitfield are interleaved. For example, given the frame "010101" and frame data "000010" where the frame data is interleaved the result is the object selector "001000.”
  • the name of each location in an N-dimensional space corresponds to an object selector.
  • Referencing a set of harmonious color sensations as relations of a logical color space may be accomplished by generating combinations of n-things taken k at a time, where n is the number of elements in a logical color space and k is the number of selector bits.
  • the elements of a set are said to be neighbors or logically adjacent because one can be obtained from the other by switching a "0" and a "1" in a particular selector bit position.
  • the number of elements in each logical relation corresponds to the number of selector bits.
  • Referencing various sets in a logical color space may be accomplished selectively masking one or more selector bits.
  • Generating a harmonious sequence of color sensations as paths in a logical color space ma be accomplished because the collection of element names describe a Gray sequence, where the Hamming distance between successive elements is one. The sequence of color sensations is said to cycle if its first and last element codewords differ in only one quantum interval. Otherwise, the sequence of color sensations is known as a path. Given an initial element codeword and a transition sequence the entire set of element codewords in a logical color space can be generated.
  • Referencing various regions of a logical color space may be accomplished selectively by masking lower-order selector bits.
  • Referencing various subspaces within a logical color space may be accomplished by element scaling; that is, the value of an element location is actually an object descriptor rather than a color sensation.
  • RGC demodulation may be generalized as a novel form of digital to analog conversion.
  • the inverse of RGC demodulation is the conversion of analog information to a digital form (e.g., quantization, spectral decomposition, etc.) by the process of RGC modulation.
  • the method of the present invention represents a novel coding system. Object descriptions have meaning, that is, they refer to or describe some system with certain physical or conceptual properties. For color graphics, the objects may be particular color sensations described in terms of attributes such as: red; green; blue; which define a color space.
  • the objects may be a particular coherent light source described in terms of its lightwave components, which define a signal space.
  • the significant aspect of system description is that the actual description is one selected from a set possible descriptions.
  • the invention is a general apparatus and method, designed to operate for each possible problem selection not just the one which will actually be chosen since this is unknown at the time of design.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Graphics (AREA)
  • Geometry (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Processing Or Creating Images (AREA)
  • Image Generation (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Geophysics And Detection Of Objects (AREA)
  • Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
  • Image Processing (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
US07/642,508 1991-01-16 1991-01-16 Mixed-resolution, N-dimensional object space method and apparatus Expired - Lifetime US5301284A (en)

Priority Applications (18)

Application Number Priority Date Filing Date Title
US07/642,508 US5301284A (en) 1991-01-16 1991-01-16 Mixed-resolution, N-dimensional object space method and apparatus
IL100462A IL100462A (en) 1991-01-16 1991-12-22 Mixed-resolution, n-dimensional object space method and apparatus
SG1996003653A SG43876A1 (en) 1991-01-16 1992-01-07 Mixed resolution n-dimensional object space
EP92904389A EP0567563B1 (de) 1991-01-16 1992-01-07 Vorrichtung und verfahren zur räumlichen darstellung eines n-dimensionalen objektes gemischter auflösung
JP50451592A JP3385019B2 (ja) 1991-01-16 1992-01-07 混合解像度n次元オブジェクト空間
CA002100359A CA2100359C (en) 1991-01-16 1992-01-07 Mixed resolution, n-dimensional object space
ES92904389T ES2142313T3 (es) 1991-01-16 1992-01-07 Metodo y aparato para espacios de objeto n-dimensionales de resolucion mixta.
AU12393/92A AU647247B2 (en) 1991-01-16 1992-01-07 Mixed resolution, N-dimensional object space
KR1019930701860A KR100236493B1 (ko) 1991-01-16 1992-01-07 혼합-해상도, n-차원 목적공간 가시적 논리표시 장치 및 방법
BR9205572-9A BR9205572A (pt) 1991-01-16 1992-01-07 Espaço de objetos n-dimensionais de resoluçao mista
DE69230334T DE69230334T2 (de) 1991-01-16 1992-01-07 Vorrichtung und verfahren zur räumlichen darstellung eines n-dimensionalen objektes gemischter auflösung
AT92904389T ATE187002T1 (de) 1991-01-16 1992-01-07 Vorrichtung und verfahren zur räumlichen darstellung eines n-dimensionalen objektes gemischter auflösung
PCT/US1992/000218 WO1992013313A1 (en) 1991-01-16 1992-01-07 Mixed resolution, n-dimensional object space
CN92100094A CN1041568C (zh) 1991-01-16 1992-01-16 混合分辨率n维客体空间的方法和装置
MX9200189A MX9200189A (es) 1991-01-16 1992-01-16 Metodo y aparato para espacios de objeto-dimensionales de resolucion mixta.
TW081101757A TW287341B (de) 1991-01-16 1992-03-07
US08/218,333 US5680634A (en) 1991-01-16 1994-03-28 Fixed interconnection network method and apparatus for a modular mixed-resolution, N-dimensional configuration control mechanism
US08/951,057 US5852740A (en) 1991-01-16 1997-10-15 Polymorphic network methods and apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/642,508 US5301284A (en) 1991-01-16 1991-01-16 Mixed-resolution, N-dimensional object space method and apparatus

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US08/218,333 Continuation-In-Part US5680634A (en) 1991-01-16 1994-03-28 Fixed interconnection network method and apparatus for a modular mixed-resolution, N-dimensional configuration control mechanism

Publications (1)

Publication Number Publication Date
US5301284A true US5301284A (en) 1994-04-05

Family

ID=24576867

Family Applications (3)

Application Number Title Priority Date Filing Date
US07/642,508 Expired - Lifetime US5301284A (en) 1991-01-16 1991-01-16 Mixed-resolution, N-dimensional object space method and apparatus
US08/218,333 Expired - Lifetime US5680634A (en) 1991-01-16 1994-03-28 Fixed interconnection network method and apparatus for a modular mixed-resolution, N-dimensional configuration control mechanism
US08/951,057 Expired - Fee Related US5852740A (en) 1991-01-16 1997-10-15 Polymorphic network methods and apparatus

Family Applications After (2)

Application Number Title Priority Date Filing Date
US08/218,333 Expired - Lifetime US5680634A (en) 1991-01-16 1994-03-28 Fixed interconnection network method and apparatus for a modular mixed-resolution, N-dimensional configuration control mechanism
US08/951,057 Expired - Fee Related US5852740A (en) 1991-01-16 1997-10-15 Polymorphic network methods and apparatus

Country Status (16)

Country Link
US (3) US5301284A (de)
EP (1) EP0567563B1 (de)
JP (1) JP3385019B2 (de)
KR (1) KR100236493B1 (de)
CN (1) CN1041568C (de)
AT (1) ATE187002T1 (de)
AU (1) AU647247B2 (de)
BR (1) BR9205572A (de)
CA (1) CA2100359C (de)
DE (1) DE69230334T2 (de)
ES (1) ES2142313T3 (de)
IL (1) IL100462A (de)
MX (1) MX9200189A (de)
SG (1) SG43876A1 (de)
TW (1) TW287341B (de)
WO (1) WO1992013313A1 (de)

Cited By (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654762A (en) * 1995-05-01 1997-08-05 Tektronix, Inc. Block matching for picture motion estimation using gray codes
US5729754A (en) * 1994-03-28 1998-03-17 Estes; Mark D. Associative network method and apparatus
US5745570A (en) * 1996-04-15 1998-04-28 International Business Machines Corporation Object-oriented programming environment that provides object encapsulation via encryption
US6102958A (en) * 1997-04-08 2000-08-15 Drexel University Multiresolutional decision support system
US6323879B1 (en) * 1998-05-14 2001-11-27 Autodesk, Inc. Method and system for determining the spacing of objects
US6477643B1 (en) 1996-12-27 2002-11-05 Pact Gmbh Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
US20020188678A1 (en) * 2001-06-05 2002-12-12 Edecker Ada Mae Networked computer system for communicating and operating in a virtual reality environment
US6526520B1 (en) 1997-02-08 2003-02-25 Pact Gmbh Method of self-synchronization of configurable elements of a programmable unit
US20030046607A1 (en) * 2001-09-03 2003-03-06 Frank May Method for debugging reconfigurable architectures
US20030056085A1 (en) * 1996-12-09 2003-03-20 Entire Interest Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US20030074631A1 (en) * 2001-10-12 2003-04-17 Masateru Minemoto Multi-dimensional programming device and multi-dimensional programming method
US20030097243A1 (en) * 2001-10-23 2003-05-22 Mays Thomas Gilmore Method and system for operating a hydrocarbon production facility
US20030135686A1 (en) * 1997-02-11 2003-07-17 Martin Vorbach Internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US20030220926A1 (en) * 2001-03-21 2003-11-27 Huelsman David L. Rule processing system
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US6697979B1 (en) 1997-12-22 2004-02-24 Pact Xpp Technologies Ag Method of repairing integrated circuits
US20040181500A1 (en) * 2002-03-20 2004-09-16 Huelsman David L. Method and system for capturing business rules for automated decision procession
US20040260667A1 (en) * 2001-03-21 2004-12-23 Huelsman David L. Method of providing decision automation
US6859869B1 (en) * 1995-11-17 2005-02-22 Pact Xpp Technologies Ag Data processing system
US20050053056A1 (en) * 2001-09-03 2005-03-10 Martin Vorbach Router
US20050066213A1 (en) * 2001-03-05 2005-03-24 Martin Vorbach Methods and devices for treating and processing data
US20050080798A1 (en) * 2003-09-29 2005-04-14 Huelsman David L. Batch validation method, apparatus, and computer-readable medium for rule processing
US20050080648A1 (en) * 2003-09-29 2005-04-14 Huelsman David L. Rule processing method, apparatus, and computer-readable medium to generate valid combinations for selection
US20050108183A1 (en) * 2003-09-29 2005-05-19 Huelsman David L. Rule processing method, apparatus, and computer-readable medium to provide improved selection advice
US6898563B1 (en) 1999-12-20 2005-05-24 Mcfarland M. David System for aiding in the design of combinatorial logic and sequential state machines
US20050128212A1 (en) * 2003-03-06 2005-06-16 Edecker Ada M. System and method for minimizing the amount of data necessary to create a virtual three-dimensional environment
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7003660B2 (en) 2000-06-13 2006-02-21 Pact Xpp Technologies Ag Pipeline configuration unit protocols and communication
US20060192586A1 (en) * 2002-09-06 2006-08-31 Martin Vorbach Reconfigurable sequencer structure
US7174443B1 (en) 1996-12-20 2007-02-06 Pact Xpp Technologies Ag Run-time reconfiguration method for programmable units
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US20070094204A1 (en) * 2001-03-21 2007-04-26 Huelsman David L Rule processing method and apparatus providing automatic user input selections
US20070094203A1 (en) * 2004-09-28 2007-04-26 Huelsman David L Rule processing method and apparatus providing exclude cover removal to simplify selection and/or conflict advice
US20070113046A1 (en) * 2001-03-05 2007-05-17 Martin Vorbach Data processing device and method
US20070208905A1 (en) * 2006-03-06 2007-09-06 Ramot At Tel-Aviv University Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US7389208B1 (en) * 2000-06-30 2008-06-17 Accord Solutions, Inc. System and method for dynamic knowledge construction
US20080316815A1 (en) * 2007-06-25 2008-12-25 Lin Jason T Methods of programming multilevel cell nonvolatile memory
US20090144485A1 (en) * 1996-12-27 2009-06-04 Martin Vorbach Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
US20090172351A1 (en) * 2003-08-28 2009-07-02 Martin Vorbach Data processing device and method
US7570261B1 (en) 2003-03-06 2009-08-04 Xdyne, Inc. Apparatus and method for creating a virtual three-dimensional environment, and method of generating revenue therefrom
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US7595659B2 (en) 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US20090265030A1 (en) * 2008-04-21 2009-10-22 Mori Seiki Co., Ltd Machining simulation method and machining simulation apparatus
US7650448B2 (en) 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US20100034388A1 (en) * 2001-03-29 2010-02-11 Toshihisa Nakano Data protection system that protects data by encrypting the data
US20100063616A1 (en) * 2008-09-05 2010-03-11 Mori Seiki Co., Ltd. Machining status monitoring method and machining status monitoring apparatus
US20100063617A1 (en) * 2008-09-05 2010-03-11 Mori Seiki Co., Ltd Machining state checking method and machining state checking apparatus
US20110072009A1 (en) * 2009-09-18 2011-03-24 Claurissa Tuttle Space efficient visualization of pedigree data
US20110093652A1 (en) * 2006-03-06 2011-04-21 Sandisk Il Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US8156284B2 (en) 2002-08-07 2012-04-10 Martin Vorbach Data processing method and device
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
CN103559413A (zh) * 2013-11-15 2014-02-05 北京搜房科技发展有限公司 一种数据处理方法和装置
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US10108693B2 (en) 2013-03-14 2018-10-23 Xdyne, Inc. System and method for interacting with virtual maps
US20210365825A1 (en) * 2020-05-19 2021-11-25 Mitchell A. Thornton Systems and methods for controlled quantum information processing with a trans-radix basis component
US12085642B2 (en) * 2020-06-24 2024-09-10 Leolabs, Inc. System and method for orbital collision screening

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU6813894A (en) * 1994-03-28 1995-10-17 Mark D Estes Polymorphic network methods and apparatus
FR2724033B1 (fr) * 1994-08-30 1997-01-03 Thomson Broadband Systems Procede de generation d'image de synthese
US5768564A (en) * 1994-10-07 1998-06-16 Tandem Computers Incorporated Method and apparatus for translating source code from one high-level computer language to another
US5931938A (en) * 1996-12-12 1999-08-03 Sun Microsystems, Inc. Multiprocessor computer having configurable hardware system domains
KR100259276B1 (ko) 1997-01-27 2000-06-15 윤종용 대역폭확장이 가능한 상호연결망
US6292810B1 (en) * 1997-03-03 2001-09-18 Richard Steele Richards Polymorphic enhanced modeling
US5970254A (en) * 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
US6425118B1 (en) 1997-07-18 2002-07-23 Compaq Computer Corporation System for automatically generating tests to ensure binary compatibility between software components produced by a source-to-source computer language translator
US6317871B1 (en) 1997-07-18 2001-11-13 Compaq Computer Corporation System for ensuring the accuracy of file structures in a source-to-source computer program translator
US6282627B1 (en) 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US6425101B1 (en) * 1998-10-30 2002-07-23 Infineon Technologies North America Corp. Programmable JTAG network architecture to support proprietary debug protocol
US6622233B1 (en) * 1999-03-31 2003-09-16 Star Bridge Systems, Inc. Hypercomputer
US6647408B1 (en) * 1999-07-16 2003-11-11 Novell, Inc. Task distribution
US6721780B1 (en) * 1999-11-09 2004-04-13 Fireclick, Inc. Predictive pre-download of network objects
TW456122B (en) * 1999-11-29 2001-09-21 Jang Jeng Shang Bandwidth division switching device and method
US7139743B2 (en) 2000-04-07 2006-11-21 Washington University Associative database scanning and information retrieval using FPGA devices
US6978301B2 (en) * 2000-12-06 2005-12-20 Intelliden System and method for configuring a network device
US20020069271A1 (en) * 2000-12-06 2002-06-06 Glen Tindal Event manager for network operating system
US8219662B2 (en) 2000-12-06 2012-07-10 International Business Machines Corporation Redirecting data generated by network devices
US7054946B2 (en) * 2000-12-06 2006-05-30 Intelliden Dynamic configuration of network devices to enable data transfers
US7249170B2 (en) 2000-12-06 2007-07-24 Intelliden System and method for configuration, management and monitoring of network resources
US7269784B1 (en) 2001-01-22 2007-09-11 Kasriel Stephane Server-originated differential caching
US7150037B2 (en) 2001-03-21 2006-12-12 Intelliden, Inc. Network configuration manager
US20030065632A1 (en) * 2001-05-30 2003-04-03 Haci-Murat Hubey Scalable, parallelizable, fuzzy logic, boolean algebra, and multiplicative neural network based classifier, datamining, association rule finder and visualization software tool
US7185063B1 (en) * 2001-06-22 2007-02-27 Digital River, Inc. Content delivery network using differential caching
US7092997B1 (en) 2001-08-06 2006-08-15 Digital River, Inc. Template identification with differential caching
US7188214B1 (en) 2001-08-07 2007-03-06 Digital River, Inc. Efficient compression using differential caching
US8296400B2 (en) 2001-08-29 2012-10-23 International Business Machines Corporation System and method for generating a configuration schema
US7200548B2 (en) * 2001-08-29 2007-04-03 Intelliden System and method for modeling a network device's configuration
US20030079053A1 (en) * 2001-10-23 2003-04-24 Kevin Burns System and method for evaluating effectiveness of network configuration management tools
US7065562B2 (en) * 2001-11-26 2006-06-20 Intelliden, Inc. System and method for generating a representation of a configuration schema
WO2003055119A2 (en) * 2001-12-06 2003-07-03 New York University Logic arrangement, data structure, system and method for multilinear representation of multimodal data ensembles for synthesis, recognition and compression
US7296051B1 (en) 2002-02-19 2007-11-13 Digital River, Inc. Predictive predownload of templates with delta encoding
US7487261B1 (en) 2002-02-22 2009-02-03 Digital River, Inc. Delta caching service
US6959329B2 (en) * 2002-05-15 2005-10-25 Intelliden System and method for transforming configuration commands
US7359384B2 (en) * 2002-06-10 2008-04-15 Lucent Technologies Inc. Scheduling of guaranteed-bandwidth low-jitter traffic in input-buffered switches
US20040003067A1 (en) * 2002-06-27 2004-01-01 Daniel Ferrin System and method for enabling a user interface with GUI meta data
US7464145B2 (en) 2002-07-11 2008-12-09 Intelliden, Inc. Repository-independent system and method for asset management and reconciliation
US7461158B2 (en) 2002-08-07 2008-12-02 Intelliden, Inc. System and method for controlling access rights to network resources
US7366893B2 (en) 2002-08-07 2008-04-29 Intelliden, Inc. Method and apparatus for protecting a network from attack
US7558847B2 (en) 2002-09-13 2009-07-07 Intelliden, Inc. System and method for mapping between and controlling different device abstractions
CA2836758C (en) 2003-05-23 2017-06-27 Roger D. Chamberlain Intelligent data processing system and method using fpga devices
US8059125B2 (en) * 2003-06-25 2011-11-15 Ab Initio Technology Llc Computer-aided parallelizing of computation graphs
US7379925B2 (en) * 2003-07-25 2008-05-27 New York University Logic arrangement, data structure, system and method for multilinear representation of multimodal data ensembles for synthesis, rotation and compression
EP1709572A2 (de) * 2004-01-13 2006-10-11 New York University Verfahren, system, speichermedium und datenstruktur zur bilderkennung unter verwendung einer multilinearen unabhängigen komponentenanalyse
JP4662117B2 (ja) * 2004-03-05 2011-03-30 株式会社日立製作所 ストレージシステム
US7698118B2 (en) * 2004-04-15 2010-04-13 Mentor Graphics Corporation Logic design modeling and interconnection
US7278122B2 (en) * 2004-06-24 2007-10-02 Ftl Systems, Inc. Hardware/software design tool and language specification mechanism enabling efficient technology retargeting and optimization
JP2008532177A (ja) 2005-03-03 2008-08-14 ワシントン ユニヴァーシティー 生物学的配列類似検索を実行するための方法および装置
US7788471B2 (en) * 2006-09-18 2010-08-31 Freescale Semiconductor, Inc. Data processor and methods thereof
US7660793B2 (en) 2006-11-13 2010-02-09 Exegy Incorporated Method and system for high performance integration, processing and searching of structured and unstructured data using coprocessors
US8122149B2 (en) 2007-12-28 2012-02-21 Microsoft Corporation Model-based datacenter management
US8265070B2 (en) * 2008-12-15 2012-09-11 Oracle America, Inc. System and method for implementing a multistage network using a two-dimensional array of tiles
US20120062933A1 (en) * 2010-09-10 2012-03-15 Jun Zeng Controlled job release in print manufacturing
US10037568B2 (en) 2010-12-09 2018-07-31 Ip Reservoir, Llc Method and apparatus for managing orders in financial markets
US8681416B2 (en) * 2011-11-04 2014-03-25 Nxp B.V. Passive multiplexing extension for electronic paper displays
US9990393B2 (en) 2012-03-27 2018-06-05 Ip Reservoir, Llc Intelligent feed switch
US11436672B2 (en) 2012-03-27 2022-09-06 Exegy Incorporated Intelligent switch for processing financial market data
US10121196B2 (en) 2012-03-27 2018-11-06 Ip Reservoir, Llc Offload processing of data packets containing financial market data
CN104751823B (zh) * 2015-04-16 2017-04-19 曲阜师范大学 一种适用于移动终端显示屏幕的特征化方法
CN105243469A (zh) * 2015-09-17 2016-01-13 上海寰信网络信息技术有限公司 一种多维空间映射到低维空间的方法及其展示方法和系统
US9978164B2 (en) 2016-10-06 2018-05-22 Halliburton Energy Services, Inc. Enhanced visualization method for down hole diagnostics and characterization
EP3560135A4 (de) 2016-12-22 2020-08-05 IP Reservoir, LLC Rohrleitungen zum hardware-beschleunigten maschinellen lernen
KR102204031B1 (ko) * 2019-04-11 2021-01-18 몬드리안에이아이 주식회사 지리데이터를 기반으로 한 공간의 3차원 시각화 시스템 및 이를 이용한 공간의 3차원 시각화 방법

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1079504A (en) * 1910-07-18 1913-11-25 Charles P R Macaulay Logic machine.
US2632058A (en) * 1946-03-22 1953-03-17 Bell Telephone Labor Inc Pulse code communication
US4313159A (en) * 1979-02-21 1982-01-26 Massachusetts Institute Of Technology Data storage and access apparatus
US4475156A (en) * 1982-09-21 1984-10-02 Xerox Corporation Virtual machine control
US4721952A (en) * 1984-02-03 1988-01-26 Dr. Johannes Heidenhain Gmbh Apparatus and process for graphically representing three-dimensional objects in two-dimensions
US4855903A (en) * 1984-12-20 1989-08-08 State University Of New York Topologically-distributed-memory multiprocessor computer
US4887878A (en) * 1984-06-14 1989-12-19 Polaroid Corporation Optical modulation device
US4905163A (en) * 1988-10-03 1990-02-27 Minnesota Mining & Manufacturing Company Intelligent optical navigator dynamic information presentation and navigation system
US4918600A (en) * 1988-08-01 1990-04-17 Board Of Regents, University Of Texas System Dynamic address mapping for conflict-free vector access
US4922415A (en) * 1984-03-02 1990-05-01 Hemdal Goran A H Data processing system for converting virtual to real addresses without requiring instruction from the central processing unit
US5189416A (en) * 1991-04-29 1993-02-23 Walker-Estes Corporation Chordal keyboard method and apparatus
US5195172A (en) * 1990-07-02 1993-03-16 Quantum Development Corporation System and method for representing and solving numeric and symbolic problems
US5202981A (en) * 1989-10-23 1993-04-13 International Business Machines Corporation Process and apparatus for manipulating a boundless data stream in an object oriented programming system

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3408532A (en) * 1965-12-06 1968-10-29 Northrop Corp Electron beam scanning device
US3609397A (en) * 1969-12-29 1971-09-28 Ibm Signal-classifying circuit
US4272829A (en) * 1977-12-29 1981-06-09 Ncr Corporation Reconfigurable register and logic circuitry device for selective connection to external buses
US4630045A (en) * 1983-10-24 1986-12-16 International Business Machines Corporation Controller for a cross-point switching matrix
US4605928A (en) * 1983-10-24 1986-08-12 International Business Machines Corporation Fault-tolerant array of cross-point switching matrices
US4679186A (en) * 1984-09-26 1987-07-07 American Telephone And Telegraph Company, At&T Bell Laboratories Alternate self-routing packet switching node having fault detection capabilities
US4744028A (en) * 1985-04-19 1988-05-10 American Telephone And Telegraph Company, At&T Bell Laboratories Methods and apparatus for efficient resource allocation
US4744026A (en) * 1986-04-11 1988-05-10 American Telephone And Telegraph Company, At&T Bell Laboratories Methods and apparatus for efficient resource allocation
US4745630A (en) * 1986-06-18 1988-05-17 Hughes Aircraft Company Multi-mode counter network
US4888692A (en) * 1986-08-11 1989-12-19 Texas Instruments Incorporated Real-time scheduling system
US4744027A (en) * 1986-08-22 1988-05-10 American Telephone And Telegraph Company, At&T Bell Laboratories Method and apparatus for optimizing system operational parameters
US5038386A (en) * 1986-08-29 1991-08-06 International Business Machines Corporation Polymorphic mesh network image processing system
US4930092A (en) * 1987-01-20 1990-05-29 Auto-Trol Technology Corporation Polygon display apparatus and method
US4943909A (en) * 1987-07-08 1990-07-24 At&T Bell Laboratories Computational origami
DE68929518T2 (de) * 1988-10-05 2005-06-09 Quickturn Design Systems, Inc., Mountain View Verfahren zur Verwendung einer elektronisch wiederkonfigurierbaren Gatterfeld-Logik und dadurch hergestelltes Gerät
US5020059A (en) * 1989-03-31 1991-05-28 At&T Bell Laboratories Reconfigurable signal processor
US5030921A (en) * 1990-02-09 1991-07-09 Motorola, Inc. Cascaded cold cathode field emission devices
JPH0828749B2 (ja) * 1990-06-14 1996-03-21 株式会社東芝 ネットワークコントローラ
US5075595A (en) * 1991-01-24 1991-12-24 Motorola, Inc. Field emission device with vertically integrated active control
US5289365A (en) * 1991-12-23 1994-02-22 Donnelly Corporation Modular network control system

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1079504A (en) * 1910-07-18 1913-11-25 Charles P R Macaulay Logic machine.
US2632058A (en) * 1946-03-22 1953-03-17 Bell Telephone Labor Inc Pulse code communication
US4313159A (en) * 1979-02-21 1982-01-26 Massachusetts Institute Of Technology Data storage and access apparatus
US4475156A (en) * 1982-09-21 1984-10-02 Xerox Corporation Virtual machine control
US4721952A (en) * 1984-02-03 1988-01-26 Dr. Johannes Heidenhain Gmbh Apparatus and process for graphically representing three-dimensional objects in two-dimensions
US4922415A (en) * 1984-03-02 1990-05-01 Hemdal Goran A H Data processing system for converting virtual to real addresses without requiring instruction from the central processing unit
US4887878A (en) * 1984-06-14 1989-12-19 Polaroid Corporation Optical modulation device
US4855903A (en) * 1984-12-20 1989-08-08 State University Of New York Topologically-distributed-memory multiprocessor computer
US4918600A (en) * 1988-08-01 1990-04-17 Board Of Regents, University Of Texas System Dynamic address mapping for conflict-free vector access
US4905163A (en) * 1988-10-03 1990-02-27 Minnesota Mining & Manufacturing Company Intelligent optical navigator dynamic information presentation and navigation system
US5202981A (en) * 1989-10-23 1993-04-13 International Business Machines Corporation Process and apparatus for manipulating a boundless data stream in an object oriented programming system
US5195172A (en) * 1990-07-02 1993-03-16 Quantum Development Corporation System and method for representing and solving numeric and symbolic problems
US5189416A (en) * 1991-04-29 1993-02-23 Walker-Estes Corporation Chordal keyboard method and apparatus

Non-Patent Citations (64)

* Cited by examiner, † Cited by third party
Title
A. Newell, On Programming a Highly Parallel Machine to be an Intelligent Technician, Proc. of Western Joint Comp. Conf., vol. 17, May 1960, pp. 267 280. *
A. Newell, On Programming a Highly Parallel Machine to be an Intelligent Technician, Proc. of Western Joint Comp. Conf., vol. 17, May 1960, pp. 267-280.
A. R. Smith, "Color Gamut Transformation Pairs," ACM Computer Graphics (SIGGRAPH 78), vol. 12, No. 3, pp. 12-19.
A. R. Smith, Color Gamut Transformation Pairs, ACM Computer Graphics (SIGGRAPH 78), vol. 12, No. 3, pp. 12 19. *
A. Santisteban, The Perceptual Color Space of Digital Image Display Terminals, IBM J. Res. Develop., vol. 27, No. 2, Mar. 1983, pp. 127 132. *
A. Santisteban, The Perceptual Color Space of Digital Image Display Terminals, IBM J. Res. Develop., vol. 27, No. 2, Mar. 1983, pp. 127-132.
C. Faloutons, Gray Codes for Partial Match and Range Queries, IEEE Trans. on Software Eng., vol. 14, No. 10, Oct. 1988, pp. 1381 1393. *
C. Faloutons, Gray Codes for Partial Match and Range Queries, IEEE Trans. on Software Eng., vol. 14, No. 10, Oct. 1988, pp. 1381-1393.
C. L. Seitz, "The Cosmic Cube," Communications of the ACM, vol. 28, No. 1, Jan. 1985, pp. 22-33.
C. L. Seitz, The Cosmic Cube, Communications of the ACM, vol. 28, No. 1, Jan. 1985, pp. 22 33. *
C. R. Clare, Designing Logic Systems Using State Machines, 1973, McGraw Hill, pp. 14 17. *
C. R. Clare, Designing Logic Systems Using State Machines, 1973, McGraw-Hill, pp. 14-17.
D. L. MacAdam, Uniform Color Scales, J. Optical Society of America, vol. 64, No. 12, Dec. 1974, pp. 1691 1702. *
D. L. MacAdam, Uniform Color Scales, J. Optical Society of America, vol. 64, No. 12, Dec. 1974, pp. 1691-1702.
D. S. Rogers, Procedural Elements for Computer Graphics, McGraw Hill, N.Y., 1985, pp. 8 19. *
D. S. Rogers, Procedural Elements for Computer Graphics, McGraw-Hill, N.Y., 1985, pp. 8-19.
E. A. Feustel, On the Avdantages of Tagged Architecture, IEEE Trans. on Comp., vol. C 22, No. 7, Jul. 1973, pp. 644 656. *
E. A. Feustel, On the Avdantages of Tagged Architecture, IEEE Trans. on Comp., vol. C-22, No. 7, Jul. 1973, pp. 644-656.
E. Gibson, Objects Born and Bred, BYTE, Oct. 1990, pp. 245 254. *
E. Gibson, Objects-Born and Bred, BYTE, Oct. 1990, pp. 245-254.
G. Knight, "Technology and Needs Analysis Report: Potential New Research Directions for MCC", Technology Strategy Section, International Liaison Office, Feb. 6, 1990, pp. 36-45.
G. Knight, Technology and Needs Analysis Report: Potential New Research Directions for MCC , Technology Strategy Section, International Liaison Office, Feb. 6, 1990, pp. 36 45. *
H. J. Durrett, ed., Color and the Computer , Color Displays and Color Science (G. Murch), Academic Press, Boston (1987), pp. 1 25. *
H. J. Durrett, ed., Color and the Computer, "Color Displays and Color Science" (G. Murch), Academic Press, Boston (1987), pp. 1-25.
H. Samet, The Design and Analysis of Spatial Data Structures, 1989, Addison Wesley, N.Y., pp. 104 111. *
H. Samet, The Design and Analysis of Spatial Data Structures, 1989, Addison Wesley, N.Y., pp. 104-111.
J. P. Roth, "The Synthesis of Switching Systems I.," Transactions of the American Mathematical Society, vol. 88, No. 2, Jul. 1958, pp. 301-327.
J. P. Roth, The Synthesis of Switching Systems I., Transactions of the American Mathematical Society, vol. 88, No. 2, Jul. 1958, pp. 301 327. *
Joblove and Greenberg, "Color Spaces for Computer Graphics," ACM Computer Graphics (SIGGRAPH 78), vol. 12, No. 3, pp. 20-25.
Joblove and Greenberg, Color Spaces for Computer Graphics, ACM Computer Graphics (SIGGRAPH 78), vol. 12, No. 3, pp. 20 25. *
K. Hwang and J. Ghosh, Hypernet: A Communication Efficient Architecture for Constructing Massively Parallel Computers, IEEE Trans. on Comp., vol. C 36, No. 12, Dec. 1987, pp. 1450 1466. *
K. Hwang and J. Ghosh, Hypernet: A Communication-Efficient Architecture for Constructing Massively Parallel Computers, IEEE Trans. on Comp., vol. C-36, No. 12, Dec. 1987, pp. 1450-1466.
L. D. Silverstein et al., Modeling of Display Color Parameters and Algorithmic Color Selection, Proc. of SPIE, vol. 624 (1986), pp. 26 35. *
L. D. Silverstein et al., Modeling of Display Color Parameters and Algorithmic Color Selection, Proc. of SPIE, vol. 624 (1986), pp. 26-35.
Liu and Fu, "Cellwork, Its Network Duals, and Some Applications-Three-Dimensional Karnaugh Map and its Virtual Planar Representation," Information Science, vol. 24, 1981, pp. 93-109.
Liu and Fu, Cellwork, Its Network Duals, and Some Applications Three Dimensional Karnaugh Map and its Virtual Planar Representation, Information Science, vol. 24, 1981, pp. 93 109. *
M. A. Svilotti, "A Dynamically Configurable Architecture for Prototyping Analog Circuits," Advanced Research Proceedings of the Fifth MIT Conference, 1988, MIT, pp. 238-258.
M. A. Svilotti, A Dynamically Configurable Architecture for Prototyping Analog Circuits, Advanced Research Proceedings of the Fifth MIT Conference, 1988, MIT, pp. 238 258. *
M. Gardner, Logic Machines and Diagrams, 2nd Ed., Univ. of Chicago Press: Chicago, 1982, 165 p., especially pp. 14 20, pp. 27 36, pp. 39 45, pp. 54 61, pp. 75 80, pp. 92 99, p. 113, and pp. 125 137. *
M. Gardner, Logic Machines and Diagrams, 2nd Ed., Univ. of Chicago Press: Chicago, 1982, 165 p., especially pp. 14-20, pp. 27-36, pp. 39-45, pp. 54-61, pp. 75-80, pp. 92-99, p. 113, and pp. 125-137.
M. Karnaugh, "The Map Method for Synthesis of Combinational Logic Circuits," AIEE Transactions, Part I, vol. 72, Nov. 1953, pp. 593-599.
M. Karnaugh, The Map Method for Synthesis of Combinational Logic Circuits, AIEE Transactions, Part I, vol. 72, Nov. 1953, pp. 593 599. *
M. T. Heath, "The Hypercube: A Tutorial Overview" Hypercube Microprocessors 1986, SIAM, Philadelphia (1986), pp. 7-10.
M. T. Heath, The Hypercube: A Tutorial Overview Hypercube Microprocessors 1986, SIAM, Philadelphia (1986), pp. 7 10. *
Marihugh and Anderson, "The H-Diagram: A Graphical Approach to Logic Design," IEEE Transaction on Computers, vol. C-20, No. 10 Oct. 1971, pp. 1192-1196.
Marihugh and Anderson, The H Diagram: A Graphical Approach to Logic Design, IEEE Transaction on Computers, vol. C 20, No. 10 Oct. 1971, pp. 1192 1196. *
P. K. Robertson, Perceptual Color Spaces, IEEE CG&A, Sep. 1988, pp. 50 64. *
P. K. Robertson, Perceptual Color Spaces, IEEE CG&A, Sep. 1988, pp. 50-64.
Patrick, Anderson and Bechtel, "Mapping Multidimensional Space to One-Dimension for Computer Output Display," IEEE Transactions on Computers, vol. C-17, No. 10, Oct. 1968, pp. 949-953.
Patrick, Anderson and Bechtel, Mapping Multidimensional Space to One Dimension for Computer Output Display, IEEE Transactions on Computers, vol. C 17, No. 10, Oct. 1968, pp. 949 953. *
R. Bayer et al., ed., Operating Systems, An Advanced Course, Springer Verlag: New York (1979), pp. 2 16. *
R. Bayer et al., ed., Operating Systems, An Advanced Course, Springer-Verlag: New York (1979), pp. 2-16.
R. Hall, Illumination and Color in Computer Generated Imagery, Springer Verlag: New York (1988) pp. 47 52. *
R. Hall, Illumination and Color in Computer Generated Imagery, Springer-Verlag: New York (1988) pp. 47-52.
R. L. Dayton, Guide to Integrating Digital Services, Intertext Publications, McGraw Hill: New York (1989), pp. 61 74. *
R. L. Dayton, Guide to Integrating Digital Services, Intertext Publications, McGraw-Hill: New York (1989), pp. 61-74.
R. Perez, Electronic Display Devices, TAB Professional and Reference Books, Blue Ridge Summit, Pa., 1988, pp. 69 129. *
R. Perez, Electronic Display Devices, TAB Professional and Reference Books, Blue Ridge Summit, Pa., 1988, pp. 69-129.
S. W. Srihari, "Representation of Three-Dimensional Images," Computing Surveys, vol. 13, No. 4, Dec. 1981, pp. 399-424.
S. W. Srihari, Representation of Three Dimensional Images, Computing Surveys, vol. 13, No. 4, Dec. 1981, pp. 399 424. *
T. Berk et al., A New Color Naming System for Graphics Languages, IEEE CG&A, May 1982, pp. 37 44. *
T. Berk et al., A New Color-Naming System for Graphics Languages, IEEE CG&A, May 1982, pp. 37-44.
W. C. Athas and C. L. Seitz, Multicomputers: Message Passing Concurrent Computers, IEEE Computer, Aug. 1988, pp. 9 24. *
W. C. Athas and C. L. Seitz, Multicomputers: Message-Passing Concurrent Computers, IEEE Computer, Aug. 1988, pp. 9-24.

Cited By (162)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729754A (en) * 1994-03-28 1998-03-17 Estes; Mark D. Associative network method and apparatus
US5654762A (en) * 1995-05-01 1997-08-05 Tektronix, Inc. Block matching for picture motion estimation using gray codes
US6859869B1 (en) * 1995-11-17 2005-02-22 Pact Xpp Technologies Ag Data processing system
US5745570A (en) * 1996-04-15 1998-04-28 International Business Machines Corporation Object-oriented programming environment that provides object encapsulation via encryption
US7822968B2 (en) 1996-12-09 2010-10-26 Martin Vorbach Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
US7237087B2 (en) 1996-12-09 2007-06-26 Pact Xpp Technologies Ag Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells
US7565525B2 (en) 1996-12-09 2009-07-21 Pact Xpp Technologies Ag Runtime configurable arithmetic and logic cell
US20080010437A1 (en) * 1996-12-09 2008-01-10 Martin Vorbach Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)
US8156312B2 (en) 1996-12-09 2012-04-10 Martin Vorbach Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units
US20030056085A1 (en) * 1996-12-09 2003-03-20 Entire Interest Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)
US7650448B2 (en) 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7899962B2 (en) 1996-12-20 2011-03-01 Martin Vorbach I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US7174443B1 (en) 1996-12-20 2007-02-06 Pact Xpp Technologies Ag Run-time reconfiguration method for programmable units
US8195856B2 (en) 1996-12-20 2012-06-05 Martin Vorbach I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7822881B2 (en) 1996-12-27 2010-10-26 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
US20090144485A1 (en) * 1996-12-27 2009-06-04 Martin Vorbach Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
US6477643B1 (en) 1996-12-27 2002-11-05 Pact Gmbh Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
USRE45223E1 (en) 1997-02-08 2014-10-28 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
US6968452B2 (en) 1997-02-08 2005-11-22 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable unit
USRE45109E1 (en) 1997-02-08 2014-09-02 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
US20040052130A1 (en) * 1997-02-08 2004-03-18 Martin Vorbach Method of self-synchronization of configurable elements of a programmable unit
US6526520B1 (en) 1997-02-08 2003-02-25 Pact Gmbh Method of self-synchronization of configurable elements of a programmable unit
USRE44383E1 (en) 1997-02-08 2013-07-16 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US20040083399A1 (en) * 1997-02-08 2004-04-29 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US7036036B2 (en) 1997-02-08 2006-04-25 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US20030135686A1 (en) * 1997-02-11 2003-07-17 Martin Vorbach Internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US7010667B2 (en) 1997-02-11 2006-03-07 Pact Xpp Technologies Ag Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US6102958A (en) * 1997-04-08 2000-08-15 Drexel University Multiresolutional decision support system
US6697979B1 (en) 1997-12-22 2004-02-24 Pact Xpp Technologies Ag Method of repairing integrated circuits
US20040181726A1 (en) * 1997-12-22 2004-09-16 Martin Vorbach Method and system for alternating between programs for execution by cells of an integrated circuit
US8819505B2 (en) 1997-12-22 2014-08-26 Pact Xpp Technologies Ag Data processor having disabled cores
US7233341B1 (en) 1998-05-14 2007-06-19 Autodesk, Inc. Spacing objects within a constraint
US6323879B1 (en) * 1998-05-14 2001-11-27 Autodesk, Inc. Method and system for determining the spacing of objects
US8468329B2 (en) 1999-02-25 2013-06-18 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US8726250B2 (en) 1999-06-10 2014-05-13 Pact Xpp Technologies Ag Configurable logic integrated circuit having a multidimensional structure of configurable elements
US8312200B2 (en) 1999-06-10 2012-11-13 Martin Vorbach Processor chip including a plurality of cache elements connected to a plurality of processor cores
US6898563B1 (en) 1999-12-20 2005-05-24 Mcfarland M. David System for aiding in the design of combinatorial logic and sequential state machines
US8301872B2 (en) 2000-06-13 2012-10-30 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US7003660B2 (en) 2000-06-13 2006-02-21 Pact Xpp Technologies Ag Pipeline configuration unit protocols and communication
US20090018984A1 (en) * 2000-06-30 2009-01-15 Solinsky James C System and method for dynamic knowledge construction
US7389208B1 (en) * 2000-06-30 2008-06-17 Accord Solutions, Inc. System and method for dynamic knowledge construction
US8471593B2 (en) 2000-10-06 2013-06-25 Martin Vorbach Logic cell array and bus system
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US9047440B2 (en) 2000-10-06 2015-06-02 Pact Xpp Technologies Ag Logical cell array and bus system
US7595659B2 (en) 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US20050066213A1 (en) * 2001-03-05 2005-03-24 Martin Vorbach Methods and devices for treating and processing data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US8099618B2 (en) 2001-03-05 2012-01-17 Martin Vorbach Methods and devices for treating and processing data
US8145881B2 (en) 2001-03-05 2012-03-27 Martin Vorbach Data processing device and method
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US20070113046A1 (en) * 2001-03-05 2007-05-17 Martin Vorbach Data processing device and method
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US9075605B2 (en) 2001-03-05 2015-07-07 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US8312301B2 (en) 2001-03-05 2012-11-13 Martin Vorbach Methods and devices for treating and processing data
US7430548B2 (en) 2001-03-21 2008-09-30 Verde Sabor Assets, L.L.C. Rule processing system
US20030220926A1 (en) * 2001-03-21 2003-11-27 Huelsman David L. Rule processing system
US7809669B2 (en) 2001-03-21 2010-10-05 Huelsman David L Rule processing system for determining a result response
US7761397B2 (en) 2001-03-21 2010-07-20 Huelsman David L Rule processing method and apparatus providing automatic user input selections
US20040260667A1 (en) * 2001-03-21 2004-12-23 Huelsman David L. Method of providing decision automation
US20070094204A1 (en) * 2001-03-21 2007-04-26 Huelsman David L Rule processing method and apparatus providing automatic user input selections
US20080270337A1 (en) * 2001-03-21 2008-10-30 Verde Sabor Assets, L.L.C. Rule processing system
US20100318476A1 (en) * 2001-03-21 2010-12-16 Huelsman David L Rule processing method and apparatus providing automatic user input selection
US20070150429A1 (en) * 2001-03-21 2007-06-28 Huelsman David L Rule processing system
US7188091B2 (en) 2001-03-21 2007-03-06 Resolutionebs, Inc. Rule processing system
US6965887B2 (en) 2001-03-21 2005-11-15 Resolutionebs, Inc. Rule processing methods for automating a decision and assessing satisfiability of rule-based decision diagrams
US8416953B2 (en) * 2001-03-29 2013-04-09 Panasonic Corporation Data protection system that protects data by encrypting the data
US9130741B2 (en) 2001-03-29 2015-09-08 Panasonic Corporation Data protection system that protects data by encrypting the data
US20100034388A1 (en) * 2001-03-29 2010-02-11 Toshihisa Nakano Data protection system that protects data by encrypting the data
US8667081B2 (en) 2001-06-05 2014-03-04 Xdyne, Inc. Networked computer system for communicating and operating in a virtual reality environment
US7269632B2 (en) 2001-06-05 2007-09-11 Xdyne, Inc. Networked computer system for communicating and operating in a virtual reality environment
US8954527B2 (en) 2001-06-05 2015-02-10 Xdyne, Inc. Networked computer system for communicating and operating in a virtual reality environment
US20020188678A1 (en) * 2001-06-05 2002-12-12 Edecker Ada Mae Networked computer system for communicating and operating in a virtual reality environment
US8429245B2 (en) 2001-06-05 2013-04-23 Xdyne, Inc. Networked computer system for communicating and operating in a virtual reality environment
US20070288598A1 (en) * 2001-06-05 2007-12-13 Edeker Ada M Networked computer system for communicating and operating in a virtual reality environment
US8539085B2 (en) 2001-06-05 2013-09-17 Xydne, Inc. Networked computer system for communicating and operating in a virtual reality environment
US8417822B2 (en) 2001-06-05 2013-04-09 Xdyne, Inc. Networked computer system for communicating and operating in a virtual reality environment
US8150941B2 (en) 2001-06-05 2012-04-03 Xdyne, Inc. Networked computer system for communicating and operating in a virtual reality environment
US8655980B2 (en) 2001-06-05 2014-02-18 Xdyne, Inc. Networked computer system for communicating and operating in a virtual reality environment
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US8869121B2 (en) 2001-08-16 2014-10-21 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US7480825B2 (en) 2001-09-03 2009-01-20 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US8209653B2 (en) 2001-09-03 2012-06-26 Martin Vorbach Router
US20050022062A1 (en) * 2001-09-03 2005-01-27 Martin Vorbach Method for debugging reconfigurable architectures
US20050053056A1 (en) * 2001-09-03 2005-03-10 Martin Vorbach Router
US8069373B2 (en) 2001-09-03 2011-11-29 Martin Vorbach Method for debugging reconfigurable architectures
US7840842B2 (en) 2001-09-03 2010-11-23 Martin Vorbach Method for debugging reconfigurable architectures
US8429385B2 (en) 2001-09-03 2013-04-23 Martin Vorbach Device including a field having function cells and information providing cells controlled by the function cells
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US8407525B2 (en) 2001-09-03 2013-03-26 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US20030046607A1 (en) * 2001-09-03 2003-03-06 Frank May Method for debugging reconfigurable architectures
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US20030074631A1 (en) * 2001-10-12 2003-04-17 Masateru Minemoto Multi-dimensional programming device and multi-dimensional programming method
US6973642B2 (en) * 2001-10-12 2005-12-06 Masateru Minemoto Multi-dimensional programming device and multi-dimensional programming method
US20030097243A1 (en) * 2001-10-23 2003-05-22 Mays Thomas Gilmore Method and system for operating a hydrocarbon production facility
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US20090313201A1 (en) * 2002-03-20 2009-12-17 Huelsman David L Method and system for capturing business rules for automated decision procession
US20040181500A1 (en) * 2002-03-20 2004-09-16 Huelsman David L. Method and system for capturing business rules for automated decision procession
US8732107B2 (en) 2002-03-20 2014-05-20 Verde Sabor Assets, L.L.C. Method and system for capturing business rules for automated decision procession
US7587379B2 (en) 2002-03-20 2009-09-08 Huelsman David L Method and system for capturing business rules for automated decision procession
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US8281265B2 (en) 2002-08-07 2012-10-02 Martin Vorbach Method and device for processing data
US8156284B2 (en) 2002-08-07 2012-04-10 Martin Vorbach Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US7602214B2 (en) 2002-09-06 2009-10-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7782087B2 (en) 2002-09-06 2010-08-24 Martin Vorbach Reconfigurable sequencer structure
US8803552B2 (en) 2002-09-06 2014-08-12 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US8310274B2 (en) 2002-09-06 2012-11-13 Martin Vorbach Reconfigurable sequencer structure
US7928763B2 (en) 2002-09-06 2011-04-19 Martin Vorbach Multi-core processing system
US20060192586A1 (en) * 2002-09-06 2006-08-31 Martin Vorbach Reconfigurable sequencer structure
US20050128212A1 (en) * 2003-03-06 2005-06-16 Edecker Ada M. System and method for minimizing the amount of data necessary to create a virtual three-dimensional environment
US7570261B1 (en) 2003-03-06 2009-08-04 Xdyne, Inc. Apparatus and method for creating a virtual three-dimensional environment, and method of generating revenue therefrom
US20100020075A1 (en) * 2003-03-06 2010-01-28 Xydne, Inc. Apparatus and method for creating a virtual three-dimensional environment, and method of generating revenue therefrom
US8812820B2 (en) 2003-08-28 2014-08-19 Pact Xpp Technologies Ag Data processing device and method
US20090172351A1 (en) * 2003-08-28 2009-07-02 Martin Vorbach Data processing device and method
US20050108183A1 (en) * 2003-09-29 2005-05-19 Huelsman David L. Rule processing method, apparatus, and computer-readable medium to provide improved selection advice
US8055604B2 (en) 2003-09-29 2011-11-08 Verde Sabor Assets, L.L.C. Rule processing method, apparatus and computer-readable medium to provide improved selection advice
US20090228420A1 (en) * 2003-09-29 2009-09-10 Verde Sabor Assets, L.L.C. Rule processing method, apparatus and computer-readable medium to provide improved selection advice
US20050080648A1 (en) * 2003-09-29 2005-04-14 Huelsman David L. Rule processing method, apparatus, and computer-readable medium to generate valid combinations for selection
US7587380B2 (en) 2003-09-29 2009-09-08 Huelsman David L Rule processing method, apparatus, and computer-readable medium to generate valid combinations for selection
US7565337B2 (en) 2003-09-29 2009-07-21 Huelsman David L Batch validation method, apparatus, and computer-readable medium for rule processing
US20050080798A1 (en) * 2003-09-29 2005-04-14 Huelsman David L. Batch validation method, apparatus, and computer-readable medium for rule processing
US7552102B2 (en) 2003-09-29 2009-06-23 Huelsman David L Rule processing method, apparatus, and computer-readable medium to provide improved selection advice
US7734559B2 (en) 2004-09-28 2010-06-08 Huelsman David L Rule processing method and apparatus providing exclude cover removal to simplify selection and/or conflict advice
US20070094203A1 (en) * 2004-09-28 2007-04-26 Huelsman David L Rule processing method and apparatus providing exclude cover removal to simplify selection and/or conflict advice
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
US20070208905A1 (en) * 2006-03-06 2007-09-06 Ramot At Tel-Aviv University Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US20080291724A1 (en) * 2006-03-06 2008-11-27 Ramot At Tel Aviv University Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
WO2007102141A3 (en) * 2006-03-06 2009-04-09 Univ Ramot Multi-bit-per-cell flash memory device with non-bijective mapping
US20110093652A1 (en) * 2006-03-06 2011-04-21 Sandisk Il Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US8804423B2 (en) 2006-03-06 2014-08-12 Ramot At Tel-Aviv University Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US7643342B2 (en) * 2006-03-06 2010-01-05 Ramot At Tel-Aviv University Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US7388781B2 (en) * 2006-03-06 2008-06-17 Sandisk Il Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US8848442B2 (en) 2006-03-06 2014-09-30 Sandisk Il Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US7719889B2 (en) * 2007-06-25 2010-05-18 Sandisk Corporation Methods of programming multilevel cell nonvolatile memory
US20080316815A1 (en) * 2007-06-25 2008-12-25 Lin Jason T Methods of programming multilevel cell nonvolatile memory
US20090265030A1 (en) * 2008-04-21 2009-10-22 Mori Seiki Co., Ltd Machining simulation method and machining simulation apparatus
US8175861B2 (en) * 2008-04-21 2012-05-08 Mori Seiki Co., Ltd. Machining simulation method and machining simulation apparatus
US20100063617A1 (en) * 2008-09-05 2010-03-11 Mori Seiki Co., Ltd Machining state checking method and machining state checking apparatus
US8180476B2 (en) * 2008-09-05 2012-05-15 Mori Seiki Co., Ltd. Machining state checking method and machining state checking apparatus
US8180477B2 (en) * 2008-09-05 2012-05-15 Mori Seiki Co., Ltd. Machining status monitoring method and machining status monitoring apparatus
US20100063616A1 (en) * 2008-09-05 2010-03-11 Mori Seiki Co., Ltd. Machining status monitoring method and machining status monitoring apparatus
US8229967B2 (en) 2009-09-18 2012-07-24 The University Of Utah Research Foundation Space efficient visualization of pedigree data
US20110072009A1 (en) * 2009-09-18 2011-03-24 Claurissa Tuttle Space efficient visualization of pedigree data
US10108693B2 (en) 2013-03-14 2018-10-23 Xdyne, Inc. System and method for interacting with virtual maps
CN103559413A (zh) * 2013-11-15 2014-02-05 北京搜房科技发展有限公司 一种数据处理方法和装置
CN103559413B (zh) * 2013-11-15 2016-11-02 北京搜房科技发展有限公司 一种数据处理方法和装置
US20210365825A1 (en) * 2020-05-19 2021-11-25 Mitchell A. Thornton Systems and methods for controlled quantum information processing with a trans-radix basis component
US11868848B2 (en) * 2020-05-19 2024-01-09 Mitchell A. Thornton Systems and methods for controlled quantum information processing with a trans-radix basis component
US12085642B2 (en) * 2020-06-24 2024-09-10 Leolabs, Inc. System and method for orbital collision screening

Also Published As

Publication number Publication date
MX9200189A (es) 1992-07-01
JPH06504393A (ja) 1994-05-19
CN1041568C (zh) 1999-01-06
US5680634A (en) 1997-10-21
ATE187002T1 (de) 1999-12-15
BR9205572A (pt) 1994-05-17
CA2100359C (en) 2004-08-03
IL100462A0 (en) 1992-09-06
TW287341B (de) 1996-10-01
EP0567563B1 (de) 1999-11-24
AU1239392A (en) 1992-08-27
KR930703650A (ko) 1993-11-30
ES2142313T3 (es) 2000-04-16
KR100236493B1 (ko) 2000-01-15
JP3385019B2 (ja) 2003-03-10
CA2100359A1 (en) 1992-07-17
CN1063374A (zh) 1992-08-05
AU647247B2 (en) 1994-03-17
WO1992013313A1 (en) 1992-08-06
EP0567563A4 (de) 1994-03-09
US5852740A (en) 1998-12-22
SG43876A1 (en) 1997-11-14
DE69230334T2 (de) 2000-11-30
EP0567563A1 (de) 1993-11-03
IL100462A (en) 1997-04-15
DE69230334D1 (de) 1999-12-30

Similar Documents

Publication Publication Date Title
US5301284A (en) Mixed-resolution, N-dimensional object space method and apparatus
Rogowitz et al. An architecture for rule-based visualization
Alexandrov Image representation and processing: a recursive approach
Renka Algorithm 772: STRIPACK: Delaunay triangulation and Voronoi diagram on the surface of a sphere
Takeyama et al. Map dynamics: integrating cellular automata and GIS through Geo-Algebra
Clementini et al. Composite regions in topological queries
KR100364942B1 (ko) 다차원데이타변환장치및방법
JPH08263566A (ja) 低次元出力装置を使用する人々に高次元テーブル情報を伝達する方法及び装置
Acan et al. Succinct navigational oracles for families of intersection graphs on a circle
Brandenburg Fan-crossing free graphs and their relationship to other beyond-planar graphs
US5586236A (en) Universal color look up table and method of generation
McBryan et al. Matrix and vector operations on hypercube parallel processors
Angelini et al. Beyond clustered planar graphs
Bachoc et al. On the density of sets avoiding parallelohedron distance 1
Vaidya et al. Design and architectural implications of a spatial information system
Fukui et al. Flexible-structured computation based on optical array logic
EP0754323B1 (de) Polymorphe netzwerkverfahren und geräte
Kastenholz Two-valued number pyramids
JP7266121B2 (ja) 計算装置、チップ、ボードカード、電子デバイスおよび計算方法
WO2022001499A1 (zh) 一种计算装置、芯片、板卡、电子设备和计算方法
Tang et al. Set-based visualization and enhancement of embedding results for heterogeneous multi-label networks
Filkins Graphical concepts in image processing-a bridge between two worlds
Xie et al. Operator-centric design patterns for information visualization software
Putanowicz et al. Simple visualizations of unstructured grids with VTK
Peitgen et al. Pascal’s Triangle: Cellular Automata and Attractors

Legal Events

Date Code Title Description
AS Assignment

Owner name: WALKER-ESTES CORPORATION, 3535 N.W. 58TH STREET, S

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:ESTES, MARK D.;WALKER, JOHN P.;REEL/FRAME:005582/0840

Effective date: 19910115

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

FPAY Fee payment

Year of fee payment: 12