US5093783A - Microcomputer register bank accessing - Google Patents

Microcomputer register bank accessing Download PDF

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Publication number
US5093783A
US5093783A US06/761,892 US76189285A US5093783A US 5093783 A US5093783 A US 5093783A US 76189285 A US76189285 A US 76189285A US 5093783 A US5093783 A US 5093783A
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Prior art keywords
register
bit
bank address
address
bank
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US06/761,892
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Yoshitaka Kitada
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NEC Electronics Corp
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NEC Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets

Definitions

  • the present invention relates to a microcomputer including a plurality of register banks, of which any one bank is designated by means of a bank address register for processing data stored therein.
  • General purpose registers are widely employed for arithmetic calculation and comparing processing in the microcomputer, and thus the microcomputer must be equipped with a plurality of general purpose registers for storing therein the results of a variety of processings or data to be processed.
  • the microcomputer actually employed comprises a plurality of register banks, each consisting of a series of general purpose registers. Any one of the register banks is selected by means of a bank address register for each processing to be executed. In such a microcomputer, it is easy to execute a processing of data in the same register bank. For example, in case the contents in the registers A and B of the register bank 0 should be added with each other and the result should be stored in the register A or the register bank 0, the address of the register bank 0 is set in the bank address register and then an instruction for adding the content of the register A with that of the register B is executed.
  • the processing has to be executed by a plurality of instructions, because two different register banks cannot be accessed at the same time during the execution of one instruction. That is, in a first instruction, the bank register 1 is accessed by setting the address of the register bank 1 in the bank address register to transfer the content of the register B of the register bank 1 to a memory. With another instruction, the bank register 0 is accessed by setting the address of the register bank 0 in the bank address register to add the content of the register A of the register bank 0 with the content stored in the memory.
  • a microcomputer which includes a plurality of register banks each consisting of a plurality of registers for containing data therein, a bank address register for holding the address of one of said register banks to be accessed and access control means responsive to a bank address signal for putting one of said register banks in accessible condition, said microcomputer comprising:
  • a logic gate circuit receiving at one input at least one bit of the address held in the bank address register and at another input a predetermined portion of the code of an instruction to be executed by the microcomputer and for modifying the inputted bit of the bank address;
  • a selection means for selecting any one of the modified bit and the non-modified bit of the bank address and outputting the selected bit as at least a portion of the bank address signal to said access control means.
  • the logic gate circuit comprises, for example, an OR gate.
  • the logic gate circuit comprises a first OR gate receiving at one input the least significant bit of the address (which is preferably coded in 2 bit length) held in the bank address register and at another input the least significant bit of the code of an instruction to be executed by the microcomputer and a second OR gate receiving at one input the most significant bit of the address held in the bank address register and at another input the least significant bit of the code of the instruction to be executed by the microcomputer.
  • the selection means comprises a first selection circuit receiving the output of the first OR gate and the least significant bit of the address held in the bank address register and for selecting any one thereof, and a second selection circuit receiving the output of the second OR gate and the most significant bit of the address held in the bank address register and for selecting any one thereof.
  • the first and second selection circuits are responsive to the variation of a timing signal to select one of the inputted signals.
  • the logic gate circuit is constituted by an Exclusive OR gate receiving at one input the least significant bit of the address held in the bank address register and at another input the least significant bit of the code of an instruction to be executed by the microcomputer.
  • FIG. 1 is a block diagram of the first example of the microcomputer embodying the present invention
  • FIG. 2 is a block diagram of the second example of the microcomputer embodying the present invention.
  • FIG. 3 is a block diagram of the third example of the microcomputer embodying the present invention.
  • the microcomputer shown in FIG. 1 comprises registers arrayed in a matrix form of four rows and four columns.
  • Each row of the register matrix constitutes a register bank 0 to 3. That is, the register bank 0 includes registers A 0 , B 0 , C 0 and D 0 .
  • the register bank 1 includes registers A 1 , B 1 , C 1 and D 1 .
  • the register bank 2 includes register A 2 , B 2 , C 2 and D 2 , and the register bank 3 includes registers A 3 , B 3 , C 3 and D 3 .
  • the microcomputer is equipped with an access control means or decoder 5.
  • the decoder 5 receives bank designating signals S 0 and S 1 and puts any one of the register banks 0 to 3 in accessible condition according to the combination of the bank designating signals S 0 and S 1 as shown in Table 1.
  • decoder 5 The construction of the decoder 5 is well known in the art and thus it will not be further explained.
  • the microcomputer further comprises a bank address register 6 and an instruction register 7.
  • the bank address register 6 has a two bit length for storing the address of the register bank to be accessed.
  • the bank address register 6 is set at "00" for designating the register bank 0, "01” for the register bank 1, "10” for the register bank 2, and "11” for the register bank 3.
  • the instruction register 7 is a memory circuit for storing therein the code of a certain instruction to be executed by the microcomputer.
  • the instruction register has an eight bit length.
  • the instruction code of the first transfer instruction for transferring the data contained in the register B to the register A in the same register bank is expressed as "10011000”.
  • the instruction code of the second transfer instruction for transferring the data from register B to register A in the same register bank or between different register banks is "10011001". Namely, the instruction code of the second transfer instruction is obtained by adding "1" to the least significant bit of the instruction code of the first transfer instruction.
  • the microcomputer comprises first and second OR gates 8 and 9.
  • the first OR gate 8 receives signals S 2 and S 4 which are respectively the contents b 0 stored in the least significant bit of the bank address register 6 and the instruction register 7.
  • the first OR gate 8 outputs a logical sum signal S 5 of the signals S 2 and S 4 .
  • the second OR gate 9 receives a signal S 3 which is the content b 1 stored in the most significant bit of the bank address register 6 and the signal S 4 which is the content b 0 stored in the least significant bit of the instruction register 7.
  • the second OR gate 9 makes a logical sum of these signals S 3 and S 4 and outputs it as a signal S 6 .
  • the microcomputer comprises a pair of selection circuits 10 and 11.
  • the first selection circuit 10 receives at its inputs the signal S 2 which is the content held in the least significant bit of the bank address register 6 and the logical sum signal S 5 .
  • the first selection circuit 10 receives at its third input a timing signal T, and outputs either one of the signals S 2 and S 5 as the signal S 0 in response to the variation of the timing signal T.
  • the first selection circuit 10 selects the logical sum signal S 5 as the output signal S 0 , while, when the timing signal T is at lower level "0" which means the timing to write the data in the register A, the first selection circuit 10 selects the signal S 2 as the output signal S 0 .
  • the second selection circuit 11 also receives the signal S 3 which is the content b 1 held in the most significant bit of the bank address register 6 and the logical sum signal S 6 .
  • the second selection circuit 11 receives also at its third input the timing signal T. When the timing signal T is "1", the second selection circuit 11 selects and outputs the logical sum signal S 6 , while, when the timing signal T is "0", it selects and outputs the signal S 3 as its output signal S 1 .
  • the access control means 5 selects one of the register banks 0 to 3.
  • the selected register bank is made accessible through an interface means (not shown) to, for example, an arithmetic logic unit.
  • a first transfer instruction may, for example, effect transfer of the data in the register B 0 of the register bank 0 to the register A 0 of the register bank 0.
  • the bank address register 6 is set to "00", while the instruction register 7 is set to "10011000".
  • the signal S 4 which is the least significant bit of the instruction register 7 is then "0".
  • the first and second OR gates 8 and 9 output respectively as the logical sum signals S 5 and S 6 the signals S 2 and S 3 which are the contents of the bits b 0 and b 1 of the bank address register 6. That is, the first and second OR gates 8 and 9 do not modify the address designated by the bank address register 6.
  • the first and second selection circuits 10 and 11 When the timing signal T is "1" which corresponds to the timing of read, the first and second selection circuits 10 and 11 output respectively the logical sum signals S 5 and S 6 , which are now equal to the signals S 2 and S 3 .
  • the signals S 2 and S 3 are inputted as the bank designating signals S 0 and S 1 to the decoder 5 and then the decoder 5 puts a register bank having an address "00" in accessible condition. Accordingly, the register bank 0 is selected and the data contained in the register B 0 is read out.
  • the first and second selection circuits 10 and 11 select respectively the signals S 2 and S 3 which are the contents of the bits b 0 and b 1 of the bank address register 6. Accordingly, the access control means or decoder 5 are inputted with the signals S 2 and S 3 as the bank designating signals S 0 and S 1 and selects the register bank 0. Thus, the data read out from the register B 0 of the register bank 0 is written in the register A 0 of the register bank 0.
  • the data is transferred from the register B 0 of the register bank 0 to the register A 0 of the register bank 0.
  • a second transfer instruction may effect transfer of the data stored in the register B 3 of the register bank 3 to the register A 0 of the register bank 0.
  • the bank address register 6 is set to "00" and the instruction register 7 is set to "10011001". Then, the signal S 4 which is the least significant bit of the instruction register 7 is "1".
  • the first and second OR gates 8 and 9 are inputted with "1” at one input thereof to thereby output "1" as the logical sum signals S 5 and S 6 regardless of the other inputs which are the contents held in the bits b 0 and b 1 of the bank address register 6.
  • the first and second selection circuits 10 and 11 When the timing signal T is "1", the first and second selection circuits 10 and 11 output respectively the logical sum signals S 5 and S 6 as the bank designating signals S 0 and S 1 , which are now "1". Thus, with these designating signals S 0 and S 1 , the access control means 5 selects the register bank 3 of which the address is "11". Accordingly, the data stored in the register B 3 of the register bank 3 is read out.
  • the first and second selection circuits 10 and 11 select respectively the signals S 2 and S 3 which are the contents held in the bits 0 and 1 of the bank address register 6, which are "0" in this case.
  • the access control means 5 selects the register bank having the address held in the bank address register 6, which is in this case the register bank 0. Accordingly, the data which has been read from the register B 3 of the register bank 3 is written in the register A 0 of the register bank 0.
  • the data transfer from the register B 3 of the register bank 3 to the register A 0 of the register bank 0 can be executed by only one instruction.
  • the register bank to which the data is to be transferred can be designated by setting its address in the bank address register 6. That is, the data can be transferred to the register belonging to any one of the register banks 0 to 3 by setting the address thereof in the bank address register 6.
  • the code of the first add instruction ordering that the data stored in the registers A and B of the same register bank are added with each other and the result is to be stored in the register A is expressed for example as "01011000”.
  • the code of the second add instruction for executing an addition of the data stored in the same register bank or different register banks is expressed as "01011001".
  • the first add instruction is executed by, first, reading the data stored in the register B 0 of the register bank 0, and reading the data stored in the register A 0 of the register bank 0, adding these data with each other and storing the result in the register A 0 of the register bank 0.
  • the second add instruction is executed by reading the data stored in the register B 3 of the register bank 3 and then the data stored in the register A 0 of the register bank 0, adding these data with each other and storing the result in the register A 0 of the register bank 0.
  • the addition of the data stored in the registers belonging to the register banks 0 and 3 can be executed by one instruction.
  • the direction of the data transfer can be changed. That is, when the polarity of the timing signal T is inverted so that the timing signal T is at a lower level "0" when the data in the register B is to be read and the timing signal T is at higher level "1" when the data is to be written in the register A, the transfer of data is conducted in an opposite direction to that in the above explained cases.
  • the bank address register 6 is set to "00"
  • the data is transferred from the register B 0 of the register bank 0 to the register A 0 of the register bank 0 in the execution of the first transfer instruction.
  • the second transfer instruction the data is transferred from the register B 0 of the register bank 0 to the register A 3 of the register bank 3.
  • FIG. 2 shows another embodiment of the present invention.
  • the microcomputer shown in FIG. 2 is designed for the data processing in a same register bank or between the register banks 0 and 1 or between the register banks 2 and 3.
  • the computer shown in FIG. 2 has a similar construction as that shown in FIG. 1 except that the signal S 3 , that is, the content held in the most significant the bit of the bank address register 6, is directly inputted to the access control means 5.
  • the computer shown in FIG. 2 does not include the second OR gate 9 nor the second selection circuit 11 shown in FIG. 1.
  • the selection circuit 10 When the timing signal T is "0", the selection circuit 10 outputs the signal S 2 which is the content held in the least significant bit of the bank address register 6. When the timing signal T is "1", the selection circuit 10 outputs the signal S 5 which has been obtained by modifying the signal S 2 by the OR gate 8.
  • the instruction code is "10011000".
  • the signal S 4 which is the least significant bit of the instruction register 7, is "0".
  • the OR gate 8 outputs the signal S 2 without modifying the same.
  • the bank designating signal S 0 outputted from the selection circuit 10 is equal to the signal S 2 regardless of the variation of the timing signal T.
  • the access control means 5 always selects the same register bank as that designated by the bank address register 6. Accordingly, with the first data transfer instruction, the data are transferred between the registers belonging to a same register bank.
  • the instruction code is, for example, "10011001".
  • the signal S 4 of "1" is inputted to an input of the OR gate 8 which, in return, outputs the signal S 5 of "1" to the selection circuit 10 by modifying the signal S 2 .
  • the OR gate 8 modifies the signal S 2 to "1". Accordingly, at the upper level "1" of the timing signal T, the selection circuit 10 selects the signal S 5 and thus the access control means 5 designates a register bank having an address of "01" or "11".
  • the selection circuit 10 selects the signal S 2 as the bank designating signal S 0 which is now "0" and then the access control means 5 selects the same register bank as designated by the bank address register 6. That is, when the bank address register is set to "00" or "10", the data transfer is executed between the register banks 0 and 1 or between the register banks 2 and 3. On the other hand, when the bank register 6 is set to "01" or "11", the OR gate 8 outputs the signal S 2 as it is. That is, the data transfer is executed in a same register bank, even with the second data transfer instruction.
  • FIG. 3 illustrates the third embodiment of the present invention.
  • the microcomputer shown in FIG. 3 has the same construction as that shown in FIG. 2 except that an Exclusive OR gate 12 is employed in lieu of the OR gate 8.
  • the first input S 4 of the Exclusive OR gate 12 is "0" and thus the Exclusive OR gate 12 does not modify the another input signal S 2 . Accordingly, the data transfer is executed in a same register bank.
  • the signal S 4 is "1".
  • the Exclusive OR gate 12 modifies the another input signal S 2 and outputs it as the signal S 5 .
  • the bank address register 6 is set to "00”
  • the Exclusive OR gate 12 outputs the signal S 5 of "1".
  • the selection circuit 10 selects the signal S 5 as the bank designating signal S 0 and thus, with the inputs of S 5 and S 3 which are respectively "1" and "0”, the access control means 5 designates the register bank 1.
  • the selection circuit 10 selects the signal S 2 which is now "0", and the access control means 5 selects the register bank 0.
  • the data is transferred from a register of the register bank 1 to a register of the register bank 0.
  • the bank address register 6 is set to "01", and the data is transferred from a register of the register bank 0 to a register of the register bank 1. That is, in this example, the register banks 0 and 1 constitute a pair of register banks between which data can be transferred.
  • the same result can be obtained when the bank address register 6 is set to "10" and "11". That is, the register banks 2 and 3 constitute a pair of register banks between which data can be transferred.
  • the transfer or processing of the data between different register banks can be executed by only one instruction. Accordingly, the program steps can be largely reduced and the data processing can be executed at a high speed.

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JP16306184A JPS6140650A (ja) 1984-08-02 1984-08-02 マイクロコンピユ−タ

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US20030115440A1 (en) * 1991-07-08 2003-06-19 Sanjiv Garg RISC microprocessor architecture implementing multiple typed register sets
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US20070106878A1 (en) * 1991-07-08 2007-05-10 Nguyen Le T High-performance, superscalar-based computer system with out-of-order instruction execution
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Cited By (32)

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US5751988A (en) * 1990-06-25 1998-05-12 Nec Corporation Microcomputer with memory bank configuration and register bank configuration
US7739482B2 (en) 1991-07-08 2010-06-15 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US7941636B2 (en) 1991-07-08 2011-05-10 Intellectual Venture Funding Llc RISC microprocessor architecture implementing multiple typed register sets
US7685402B2 (en) 1991-07-08 2010-03-23 Sanjiv Garg RISC microprocessor architecture implementing multiple typed register sets
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DE3583080D1 (de) 1991-07-11
JPH0248931B2 (xx) 1990-10-26
EP0170284B1 (en) 1991-06-05
EP0170284A3 (en) 1988-04-20
EP0170284A2 (en) 1986-02-05
JPS6140650A (ja) 1986-02-26

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