US5079733A - Pseudo-random sequence generator arrangement - Google Patents

Pseudo-random sequence generator arrangement Download PDF

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Publication number
US5079733A
US5079733A US07/683,082 US68308291A US5079733A US 5079733 A US5079733 A US 5079733A US 68308291 A US68308291 A US 68308291A US 5079733 A US5079733 A US 5079733A
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United States
Prior art keywords
arrangement
bits
registers
register
independent
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Expired - Fee Related
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US07/683,082
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English (en)
Inventor
Patrick Antoine
Jean-Jacques Quisquater
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US Philips Corp
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US Philips Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/16—Analogue secrecy systems; Analogue subscription systems
    • H04N7/167—Systems rendering the television signal unintelligible and subsequently intelligible
    • H04N7/1675—Providing digital key or authorisation information for generation or regeneration of the scrambling sequence
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
    • H04L9/0668—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator producing a non-linear pseudorandom sequence
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58—Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/581—Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58—Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/582—Parallel finite field implementation, i.e. at least partially parallel implementation of finite field arithmetic, generating several new bits or trits per step, e.g. using a GF multiplier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations

Definitions

  • the present invention relates to a pseudo-random sequence generator arrangement, including at least two basic shift registers which are arranged as multipliers, the shifts being controlled by pulses from a clock, the initial contents of the registers being preset by an internal key, and which are fed back to each other via a modifying member incorporated in the feedback loop
  • the supplied sequences must have an adequately random character, that is to say they must obey the same laws as a real random sequence (wherein, for example, the statistic proportion of 1 bit to 0 bits is 50%).
  • the duration of the cycle that is to say the cycle before a new identical sequence is found (assuming that the contents are not reinitialized) must be adequately long.
  • the duration can be at its maximum and be constant and the sequences are statistically random.
  • the duration of a cycle is variable and there is a risk of deterioration, resulting in the appearance of cycles which are too short and/or statistically not random.
  • the invention has for its object to produce a pseudo-random sequence generator which can provide the best compromise between the contradicting advantages of the linear and non-linear generators. It utilizes linear generators which are modified by non-linear operators which are controlled in such manner that they cause only little deterioration, and also no statistically non-random properties.
  • the modifying member is a gate which can interrupt the transfer of bits in at least a portion of the loop and is controlled by a signal supplied by at least one fed-back shift register and independently from the first two shift registers.
  • this gate is an AND-gate controlled by a signal coming from an OR-gate to whose inputs those bits are applied which each originate from such an independent shift register.
  • the complexity is increased without any significant degradation when the independent registers modify each other, and when furthermore this modification is effected by the insertion of at least one non-linear element, more specifically a bistable counter.
  • a second essential characteristic of the arrangement is that at least one of the two basic registers is linearly modified by inserting bits originating from a source external to the register to be modified. The detection is thus rendered more difficult, while the advantages of linear generators are preserved.
  • Each modifying bit can advantageously be obtained from an AND-gate to whose inputs the bits originating from two different independent registers are applied.
  • these two independent registers are the same as those controlling the modifying member of the loop of the basic registers.
  • the pseudo-random sequence is the result of a logic combination of bits from a plurality of pairs of registers
  • outputting the pseudo-random sequence is effected in the parallel form by taking several bits simultaneously from different stages of one of the basic shift registers.
  • a non-linear element is advantageously inserted in the path of at least one bit coming from the register(s).
  • the sole FIGURE is a circuit diagram of the overall arrangement.
  • the arrangement is used in an enciphered television system, for generating an 8-bit pseudo-random word which defines, for example, a cut-off point in a picture line. Eight bits are then necessary for each line, that is to say every 64 microseconds.
  • the present system supplies eight bits in parallel and, at least during the periods in which the supply of the codes is necessary, operates with a clock which supplies one single pulse per line.
  • the pseudo-random frequency generators are based on the use of shift registers, which include a feedback link which conveys a bit linked with the output sequence to modifiers inserted between every two stages of the register. Arrangements of this type can constitute what are commonly denoted multiplier registers, which utilize mathematical analogy in accordance with which these registers effect the multiplication of a sequence of bits supplied serially to the input, by a polynomial.
  • All the registers of the present arrangement are loaded at the start with words produced by means of an algorithm which starts from an internal key associated with a code transmitted by the transmitter. This does not form part of the invention.
  • the arrangement is based on a multiplier register 1, denoted basic register, from which the pseudo-random sequence is drawn.
  • the corresponding polynomial is of a comparatively high degree, for example comprised between 40 and 70; the basic cycle is therefore relatively long.
  • This register is a register of a type using linear modifiers which are inserted between the stages of the register (it should be noted that a variant exists in which the modifiers are positioned in a feedback loop).
  • linear modifiers must here be understood to mean that the modifying bit is applied to an element which effects a modulo-2 addition (exclusive-OR) inserted in the loop.
  • a second register 3 is provided. This register is denoted the second basic register as it is coupled to the first register. This register is also arranged as a multiplier having linear modifiers inserted between certain stages. It can have a much lower degree, for example comprised between 5 and 20.
  • the feedback link of each of them is open, and the other register is inserted there.
  • the output 2 of the register 3 is connected to the input 26 of the register 1, and the output 4 of the latter is connected to the input 27 of the register 3.
  • the output 2 is connected to the input 26 via a dual-input AND-gate 5, which can interrupt the transfer of bits in that portion of the loop shown at the right hand in the drawing.
  • the second input of the AND-gate is controlled by a signal supplied by two shift registers 33, 34 independently of the two first ones.
  • registers 33 and 34 are fed back directly one to the other, the output 20 of the register 33 being looped back to its input 7, which also holds for the output 9 of the register 34 which is fed back to its input 14.
  • the registers 33 and 34 are, for example, of a lower order than the order of the basic polynomial, and near to each other, of the order of 25 to 35.
  • a bistable counter 10 which is a non-linear element is connected to the output 9 of the register 34.
  • a bistable counter denotes a counter whose output changes state (triggering effect) when a predetermined number of 1 bits has been counted at its input. All the bistable counters of the arrangement are initialized at the start.
  • the output of the bistable counter 10 is combined with the output 20 of the register 33 in an "exclusive-OR" gate whose output value is applied to the input 7 of the register 33.
  • a symmetrical arrangement is obtained by means of the bistable counter 11 arranged between the output 20 of the register 33 and the input 14 of the register 34.
  • the two registers 33 and 34 are modified relative to each other and the counters disturb the sequence from time to time. If the counter is a count-by-n counter, an inversion of the future bits of the sequence occurs on an average every 2n clock pulses.
  • the counters 10 and 11 have unequal counting values, which are not high, for example comprised between 4 and 12.
  • an inverter 35 is inserted in the input of one of the counters, in this case the counter 11.
  • This counter has for its object to provide that one of the counters counts zeros and the other one counts "ones", so as to avoid any self-blocking: if there are many zeros, the counter 11 changes state and changes the order of the sequence.
  • the second input of the AND-gate 5, which is inserted between the basic registers 3 and 1, is connected to the output of an OR-gate 8.
  • An input of this gate 8 is connected to the input 7 of the register 33 and the other input is connected to the output 9 of the register 34. It should be understood that they might alternatively, in a variant, be connected to any random stage of these registers, without a fundamental change in the operating principle.
  • Bits supplied by an element 28 which furnishes a figure resulting from a count of television fields are introduced in the member of the register 3, and act on the linear modifiers (not shown); the resultant modification has for its object to avoid that the output is the same if periodically the same starting key is used again.
  • the register 1 is also modified, but in a more complex manner.
  • the register comprises five linear modifiers (which are not shown so as not to complicate the FIGURE, their position in the arrangement being well known) to each of which a modifying bit originating from an AND-gate 21 to 25 is conveyed.
  • the points of insertion allow between them a certain number of register stages.
  • the points in which the modifier bits are inserted are arranged such as to allow between them blocks of registers whose orders are different and as far as possible, incommensurable. If, for example, the register is of an order 67, a block of the order 19 can be provided between the output 4 and the point in which the bit coming from the gate 21 is inserted, followed by a block of the order 13 between the points in which the bit coming from the port 21 and the port 22 are inserted, thereafter a block of the order 11 between the points in which the bits originating from the gates 22 and 23 are inserted, a block of the order 7 between the points in which the bits coming from the gates 23 and 24 are inserted, a block of the order 17 between the points in which the bits from the gates 24 and 25 are inserted, the output of the gate 25 itself being directly applied to the input of the register.
  • Each of the AND-gates 21 to 25 has two inputs. For each gate, one of the inputs is connected to an intermediate output of the register 33 and the other one to an intermediate output of the register 34.
  • intermediate output is meant a connection branched between two stages at the inside (not shown) of a register.
  • Many register inputs or outputs are not denoted individually by means of a reference numeral, to avoid computation of the Figure, arrows being sufficient to indicate that outputs or inputs are concerned.
  • Gates of the AND-type are here preferably chosen, for the following reason: with equally probable sequences of ones and zeroes at the input, each AND-gate 21 to 25 supplies 1 bit only for one quarter of the bits (statistically). Since there are five modifiers, the chances of modification are consequently 5/4, that is to say almost one chance per clock pulse.
  • the inputs of the same gate are connected to intermediate outputs of very different orders in the register 33 and in the register 34.
  • a gate can be connected to the output of the order 5 of the register 33 and to the output of the order 26 of the register 34.
  • the intermediate outputs are, preferably, not equidistant.
  • the two registers 33, 34 have therefore several ways of influencing the two registers 3, 1. In constrast thereto, there is no return line from the registers 3, 1 to the registers 33, 34. They are consequently independent of the basic registers.
  • the register 1 includes five intermediate outputs 15 to 19, which supply a pseudo-random sequence of five parallel bits.
  • each output connection of the register a bistable counter 12 or 13 is inserted. All those associated with the same register preferably have different and incommensurable counting values, for example 2, 5, 7, 9, 13 or 3, 5, 7, 11, 13 etc.
  • Each counter output controls four gates which thus modify four of the five connecting lines 15-19.
  • the non-modified connection line is different: for example for the register 34, the first output most to the left in the Figure does not modify the connection 15, the second output does not modify the connecting line 15, the second output does not modify the connecting line 16, and so forth, the fifth output at the utmost right does not modify a connecting line 19.
  • the modification is linear.
  • a clock having a much higher frequency is used.
  • This clock (not shown) can, for example, be obtained by multiplying the line frequency by means of a phase-locked loop oscillator.
  • the outputs are concealed during the field retraces, in order to prevent detection of the sequence during these periods.
  • a down-counter is initialized with a pseudo-random number. The latter is obtained by taking some internal bits from the pseudo-random generator. Thereafter, the down-counter counts down at the clock rate until zero, after which the clock of a much higher frequency is stopped and the beginning of the picture is awaited to start again with the line frequency clock.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Complex Calculations (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
US07/683,082 1988-12-30 1991-04-09 Pseudo-random sequence generator arrangement Expired - Fee Related US5079733A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8817499 1988-12-30
FR8817499A FR2641921B1 (fr) 1988-12-30 1988-12-30 Dispositif generateur de sequence pseudo-aleatoire

Related Parent Applications (1)

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US07452982 Continuation 1989-12-19

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US5079733A true US5079733A (en) 1992-01-07

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US (1) US5079733A (de)
EP (1) EP0377241B1 (de)
JP (1) JPH02226911A (de)
DE (1) DE68921730T2 (de)
FR (1) FR2641921B1 (de)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5187676A (en) * 1991-06-28 1993-02-16 Digital Equipment Corporation High-speed pseudo-random number generator and method for generating same
US5222142A (en) * 1992-06-22 1993-06-22 Hughes Aircraft Company Sequence generator
EP0614147A2 (de) 1992-12-17 1994-09-07 Bull HN Information Systems Inc. Vorrichtung zum Schutz von Software
US5351300A (en) * 1992-07-29 1994-09-27 U.S. Philips Corporation Method of modifying pseudo-random sequences and device for scrambling or descrambling information components
US5434806A (en) * 1992-05-12 1995-07-18 Telefonaktiebolaget Lm Ericsson Apparatus and method for random number generation
US5452328A (en) * 1991-09-27 1995-09-19 Lockheed Missiles & Space Company, Inc. Technique for generating sets of binary spreading-code sequences for a high data-rate spread-spectrum network
US5664017A (en) * 1995-04-13 1997-09-02 Fortress U & T Ltd. Internationally regulated system for one to one cryptographic communications with national sovereignty without key escrow
US5852665A (en) * 1995-04-13 1998-12-22 Fortress U & T Ltd. Internationally regulated system for one to one cryptographic communications with national sovereignty without key escrow
EP0924894A2 (de) * 1997-12-22 1999-06-23 Siemens Aktiengesellschaft Verfahren zur Erzeugung pseudo-zufälliger Datenworte zur Verschlüsselung
US6339781B1 (en) * 1998-05-28 2002-01-15 Oki Electric Industry Co., Ltd. M-sequence generator and PN code generator with mask table for obtaining arbitrary phase shift
US6430586B1 (en) * 1999-06-08 2002-08-06 International Business Machines Corporation Controllable bit stream generator
US6457147B1 (en) 1999-06-08 2002-09-24 International Business Machines Corporation Method and system for run-time logic verification of operations in digital systems in response to a plurality of parameters
US6590929B1 (en) 1999-06-08 2003-07-08 International Business Machines Corporation Method and system for run-time logic verification of operations in digital systems
US6691142B2 (en) * 2001-01-09 2004-02-10 Hewlett-Packard Development Company, L.P. Pseudo random address generator for 0.75M cache
US20040052222A1 (en) * 2000-11-15 2004-03-18 Rudolf Ladyzhenskii Method of updating a shift register
US20070053411A1 (en) * 2000-06-14 2007-03-08 Commissariat A L'energie Atomique Generator of repetitive sets of spreading sequences
US20110261654A1 (en) * 2007-08-30 2011-10-27 Junichi Miyamoto Optimum pseudo random sequence determining method, position detection system, position detection method, transmission device and reception device

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Publication number Priority date Publication date Assignee Title
EP1063584A4 (de) * 1998-12-25 2004-03-10 Samsung Electronics Co Ltd Kodegenerator

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US4023026A (en) * 1975-12-15 1977-05-10 International Telephone And Telegraph Corporation Pseudo-random coder with improved near range rejection
US4785410A (en) * 1985-06-05 1988-11-15 Clarion Co., Ltd. Maximum length shift register sequences generator
US4845654A (en) * 1987-07-31 1989-07-04 Clarion Co., Ltd. Pseudo random noise code generator
US4864525A (en) * 1986-07-11 1989-09-05 Clarion Co., Ltd. Maximum length shift register sequence generator

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FR1532396A (fr) * 1967-05-12 1968-07-12 Lignes Telegraph Telephon Appareillages électroniques destinés à la génération de séquences pseudo-aléatoires de signaux à quatre niveaux
SE435979B (sv) * 1983-03-14 1984-10-29 Ericsson Telefon Ab L M Anordning for kryptering/dekryptering av digitala meddelanden
DE3580679D1 (de) * 1984-02-06 1991-01-03 British Broadcasting Corp Binaere pseudo-zufalls-reihengeneratoren.

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US4023026A (en) * 1975-12-15 1977-05-10 International Telephone And Telegraph Corporation Pseudo-random coder with improved near range rejection
US4785410A (en) * 1985-06-05 1988-11-15 Clarion Co., Ltd. Maximum length shift register sequences generator
US4864525A (en) * 1986-07-11 1989-09-05 Clarion Co., Ltd. Maximum length shift register sequence generator
US4845654A (en) * 1987-07-31 1989-07-04 Clarion Co., Ltd. Pseudo random noise code generator

Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5187676A (en) * 1991-06-28 1993-02-16 Digital Equipment Corporation High-speed pseudo-random number generator and method for generating same
US20020172260A1 (en) * 1991-09-27 2002-11-21 Rice Bart F. Spread spectrum electromagnetic signals
US20080069186A1 (en) * 1991-09-27 2008-03-20 Rice Bart F Spread-spectrum transceiver
US20100215078A1 (en) * 1991-09-27 2010-08-26 Rice Bart F Spread spectrum transceiver
US7760792B2 (en) 1991-09-27 2010-07-20 Rice Bart F Spread spectrum electromagnetic signals
US5452328A (en) * 1991-09-27 1995-09-19 Lockheed Missiles & Space Company, Inc. Technique for generating sets of binary spreading-code sequences for a high data-rate spread-spectrum network
US7457345B2 (en) 1991-09-27 2008-11-25 Kipling Sahibs Llc Spread-spectrum transceiver
US7457348B2 (en) 1991-09-27 2008-11-25 Kipling Sahibs Llc Spread-spectrum transceiver
US5815526A (en) * 1991-09-27 1998-09-29 Lockheed Martin Corporation Signal comprising binary spreading-code sequences
US20070104250A1 (en) * 1991-09-27 2007-05-10 Rice Bart F Spread-spectrum transceiver
US20050025219A1 (en) * 1991-09-27 2005-02-03 Rice Bart E. Spread-spectrum transceiver
US5991333A (en) * 1991-09-27 1999-11-23 Lockheed Martin Corporation Spread-spectrum transceiver
US7924906B2 (en) 1991-09-27 2011-04-12 Kipling Sahibs Llc Spread-spectrum receiver
US5434806A (en) * 1992-05-12 1995-07-18 Telefonaktiebolaget Lm Ericsson Apparatus and method for random number generation
US5222142A (en) * 1992-06-22 1993-06-22 Hughes Aircraft Company Sequence generator
US5351300A (en) * 1992-07-29 1994-09-27 U.S. Philips Corporation Method of modifying pseudo-random sequences and device for scrambling or descrambling information components
EP0614147A3 (en) * 1992-12-17 1995-09-27 Bull Hn Information Syst Software data protection mechanism.
EP0614147A2 (de) 1992-12-17 1994-09-07 Bull HN Information Systems Inc. Vorrichtung zum Schutz von Software
US5852665A (en) * 1995-04-13 1998-12-22 Fortress U & T Ltd. Internationally regulated system for one to one cryptographic communications with national sovereignty without key escrow
US5664017A (en) * 1995-04-13 1997-09-02 Fortress U & T Ltd. Internationally regulated system for one to one cryptographic communications with national sovereignty without key escrow
EP0924894A3 (de) * 1997-12-22 2001-03-07 Siemens Aktiengesellschaft Verfahren zur Erzeugung pseudo-zufälliger Datenworte zur Verschlüsselung
EP0924894A2 (de) * 1997-12-22 1999-06-23 Siemens Aktiengesellschaft Verfahren zur Erzeugung pseudo-zufälliger Datenworte zur Verschlüsselung
US6339781B1 (en) * 1998-05-28 2002-01-15 Oki Electric Industry Co., Ltd. M-sequence generator and PN code generator with mask table for obtaining arbitrary phase shift
US6430586B1 (en) * 1999-06-08 2002-08-06 International Business Machines Corporation Controllable bit stream generator
US6590929B1 (en) 1999-06-08 2003-07-08 International Business Machines Corporation Method and system for run-time logic verification of operations in digital systems
US6457147B1 (en) 1999-06-08 2002-09-24 International Business Machines Corporation Method and system for run-time logic verification of operations in digital systems in response to a plurality of parameters
US20070053411A1 (en) * 2000-06-14 2007-03-08 Commissariat A L'energie Atomique Generator of repetitive sets of spreading sequences
US7738528B2 (en) * 2000-06-14 2010-06-15 Commissariat A L'energie Atomique Generator of repetitive sets of spreading sequences
US20040052222A1 (en) * 2000-11-15 2004-03-18 Rudolf Ladyzhenskii Method of updating a shift register
US7433906B2 (en) * 2000-11-15 2008-10-07 Indoaust Investments Ltd. Method of updating a shift register
US6691142B2 (en) * 2001-01-09 2004-02-10 Hewlett-Packard Development Company, L.P. Pseudo random address generator for 0.75M cache
US8427905B2 (en) * 2007-08-30 2013-04-23 Nec Corporation Optimum pseudo random sequence determining method, position detection system, position detection method, transmission device and reception device
US20110261654A1 (en) * 2007-08-30 2011-10-27 Junichi Miyamoto Optimum pseudo random sequence determining method, position detection system, position detection method, transmission device and reception device

Also Published As

Publication number Publication date
FR2641921B1 (fr) 1991-03-15
EP0377241A1 (de) 1990-07-11
JPH02226911A (ja) 1990-09-10
DE68921730D1 (de) 1995-04-20
FR2641921A1 (fr) 1990-07-20
DE68921730T2 (de) 1995-09-14
EP0377241B1 (de) 1995-03-15

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