US4734691A - Video bit transition advancement circuit - Google Patents

Video bit transition advancement circuit Download PDF

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US4734691A
US4734691A US06/826,692 US82669286A US4734691A US 4734691 A US4734691 A US 4734691A US 82669286 A US82669286 A US 82669286A US 4734691 A US4734691 A US 4734691A
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pel
waveform
clock
pulse
output
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Geoffrey A. Bailey
Milan H. Miessler
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International Business Machines Corp
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International Business Machines Corp
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Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION,A CORP. OF NEW YORK reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION,A CORP. OF NEW YORK ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: BAILEY, GEOFFREY A., MIESSLER, MILAN H.
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/002—Intensity circuits

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  • This invention relates to a video display system of the kind in which at least one visible characteristic of consecutive image points on the screen of a raster-scan CRT is defined by the values of consecutive pels of a digital video drive waveform, each such pel comprising one or a plurality of video bits in parallel, and in which a pulse stretching circuit is provided for extending the duration of selected pels in the video waveform in order at least partially to compensate for image distortion introduced by the finite video amplifier rise and fall times of the CRT.
  • a pulse stretching circuit is provided for extending the duration of selected pels in the video waveform in order at least partially to compensate for image distortion introduced by the finite video amplifier rise and fall times of the CRT.
  • the video channel of a high content raster-scan CRT display must operate at a very fast data rate if flicker is to be avoided.
  • a data display having 1.2 million image points refreshed at 60 Hz with a non-interlaced raster requires a peak data rate of about 100 Mpels/Sec. This corresponds to a pel period of 10 nSecs.
  • Full modulation of the electron beam requires a cathode drive voltage of about 35 volts for a monochrome tube and up to 60 Volts for color. It is very difficult to design a video amplifier to product these voltage transitions in a time which is short compared to the pel period. This is particularly true if the amplifier must handle analogue signals rather than a simple binary waveform.
  • the pulse stretching circuit comprises decoding means for examining each pel at least in relation to its two immediate neighbors on either side in order to detect predetermined relationships between the values of the pels, and retiming means for selectively advancing or delaying the transitions between consecutive pels of different value in accordance with the relationships so detected.
  • the system described in the aforesaid European patent application provides substantially improved visual results for highly dense or mixed video pictures, and considerably enhances the front-of-screen performance of the display system compared to the existing technique, the penalty for this improved performance is one of cost in the additional circuitry involved.
  • the preferred circuitry includes a 5 stage shift register; a multi-bit comparator; a 3-stage shift register with associated output logic; and 3 clocking latches also with associated output logic.
  • the system is not restricted to this simple case and by providing more complex circuits at further cost it is possible to compensate for image distortions in both color and monochrome to an increased degree of sophistication.
  • FIG. 1 shows the relationship between the grid (or cathode) voltage V d and beam current I b in a cathode ray tube display. Beam current is linearly related to the resultant luminance of the screen phosphors.
  • the relationship between the applied grid voltage V d and beam current I b is given by the expression:
  • FIG. 1 two relationships are shown, continuous curve 1 for the case where the gamma value is 1 and broken curve 2 where the gamma value is 3.
  • continuous curve 1 for the case where the gamma value is 1
  • broken curve 2 where the gamma value is 3.
  • FIG. 2 Two curves illustrating the relationship of grid voltage to beam current of the video amplifier are shown in FIG. 2 in response to the rising and falling edges of a single bit of a video signal bi-level waveform 3 such as might be applied as input to a CRT grid electrode.
  • An input step function V in applied to a CRT grid electrode is shown as waveform 3.
  • the resulting grid voltage V d is shown as continuous waveform 4. It might be expected that the resultant beam current would follow the grid voltage faithfully.
  • the continuous curve 4 represents the theoretical response of the amplifier. However, in view of the non-linear relationship between grid voltage and beam current in practice, with a CRT gamma of 3, the beam current I b and hence the light emission is more likely to be as represented by the broken curve 5.
  • the waveforms 3, 4 and 5 are all shown on the same time scale in FIG. 2. It is seen therefore that the rise time of an input pulse is made effectively longer while the fall time is made shorter. Furthermore, the amplitude of the effective video amplifier pulse never reaches its intended full magnitude represented by the magnitude of the bi-level input signal waveform 3 and the displayed pel on the screen never reaches full brightness.
  • FIG. 3 two portions of a bi-level input waveform leading to opposite conditions on the screen are shown.
  • the first, waveform portion 6, shows the signal applied to a video amplifier in order to display a single white or ⁇ on-pel ⁇ on each side of which is a black or ⁇ off-pel ⁇ .
  • the second, waveform portion 7, shows the signal required in order to display the condition where a black or ⁇ off-pel ⁇ is sandwiched between two white or ⁇ on-pels ⁇ .
  • superimposed on these two input waveform portions in FIG. 3 are the effective resulting video amplifier output waveforms shown as continuous curves 8 and 9 respectively, which actually drive the video guns of the CRT.
  • the resultant video output pulse 8 is distorted as described hereinbefore with reference to FIG. 2. that is, it is shorter in duration than the input waveform that drives it and does not reach its intended full magnitude. Accordingly, the resulting white pel is narrower and of lower intensity than desired.
  • the response to the rising and falling edges of the input pulse by the video amplifier is just the same, but because of the inverted input pulse condition, produces a different effect.
  • the video output pulse falls fairly rapidly in response to the trailing edge of the input pulse but is relatively slow to respond to the subsequent rising edge. The effect of this is to cause the video output to be at its down level for a longer period than that called for by the input pulse. Consequently, the width of the resulting black pel is wider than required. This increase of width of the black pel is not so noticeable to a viewer of the CRT screen as the reduction in width and intensity of a white pel.
  • the solution to the problem therefore is to arrange for the relative advancement of the rising edges only, of the input pel waveform by predetermined amounts in order to compensate for the experienced signal delays occasioned by the particular apparatus in question.
  • a rising edge will occur whenever a lighter pel follows a darker pel and in the specific case whenever a white pel follows a black pel.
  • FIG. 3 the rising leading edge of the positive going portion of the input waveform 6 is shown advanced in time as broken outline 6', and the rising trailing edge of the negative going portion of the input waveform 7 is shown advanced as broken outline 7'.
  • the resulting corrected video amplifier output waveforms 8 and 9 are shown in broken outline as curves 8' and 9' respectively.
  • the effect of this time shift of the rising edges of the input waveform is in each case to provide an amplifier output waveform which more closely follows the original uncorrected input waveform.
  • FIG. 1 shows the relationship between grid voltage V d and beam current I b in a cathode ray tube display
  • FIG. 2 shows the relationship between a grid voltage waveform and a beam current waveform for a single bit in a cathode ray tube display
  • FIG. 3 shows two portions of a bi-level input grid voltage waveform superimposed on the resultant beam current waveform
  • FIG. 4 shows a block diagram of a pulse stretching circuit in accordance with the present invention
  • FIG. 5 shows waveforms used to illustrate the mode of operation of the circuit FIG. 4.
  • FIG. 6 shows an expansion of the circuit of FIG. 4 to enable it to function with multiple intensity CRT displays with additional details of the circuit blocks of FIG. 4.
  • FIGS. 1-3 have been discussed above, in connection with the background art.
  • the embodiment shown in FIG. 4 is for implementation in a monochrome bi-level, e.g. white-on-black, display system.
  • the invention is equally applicable to monochrome or color displays capable of displaying multiple brightness levels in grey or color.
  • each individual n-bit line of data for display on the CRT is conventionally loaded in parallel from the system display buffer (not shown) into an n-bit shift register 10 having stages S1 to Sn. It has been assumed for the purpose of illustration, that as a result of the loading operation, the eight left-most stages of the register S1, S2, . . . of the shift register 10 containing the first eight pels for display on the CRT scan line have the binary values 0, 1, 0, 0, 1, 1, 0, 1. It is seen that this portion of the pel data, shown as waveform (a) in FIG. 5, includes a white pel (binary 1) between two black pels (binary 0) and a black pel between two white pels.
  • the contents of the shift register are incrementally clocked one stage at a time from right to left, as shown in the figure, by means of predetermined transitions of a pel clock waveform applied to terminal 11.
  • the clocking is in response to the rising edges of the pel clock waveform.
  • the pel clock waveform is shown as waveform (b) in FIG. 5.
  • the binary values representing the pels to be displayed on the screen are sampled from the left-most stage S1 of register 10, each pel clock cycle.
  • the resulting pel binary waveform, such as waveform (a) is then used to drive the video amplifier in order to effect the display on the screen.
  • the video waveform is modified by advancing relative in time, those rising edges of the binary waveform which occur when the lighter pel follows darker pel or, as in this specific implementation, when a white pel follows a black pel.
  • this is achieved simply by using a delayed version of the pel clock to gate the pel waveform to the video amplifier except when a black-to-white (or dark to lighter) transition occurs, in which case the clocking of the pel value immediately following the transition is by means of the undelayed pel clock.
  • the transitions which occur between adjacent pels of different intensity are detected by comparing their binary values. This is achieved by means of an additional stage S0 connected to the output from stage S1 of shift register 10.
  • stage S0 is clocked by the same pel clock as the register so that each pel value clocked through stage S1 is contained in the extra stage S0 one clock period later.
  • stage S1 is regarded as containing PEL(N) then at that time extra stage S0 contains PEL(N-1).
  • Output lines 12 and 13 from stages S1 and S0 respectively are connected as inputs to a comparator 14 which continuously compares the binary values of the two adjacent pels contained therein.
  • the output on line 15 from comparator 14 is at an up-level for the condition PEL(N)>PEL(N-1). That is, a rising output on line 15 indicates the current pel, PEL(N) in stage S1, is brighter than the preceding pel, PEL(N-1), in stage S0, (in this example a white pel following a black pel). Accordingly, the rising edge of the pel waveform representing this increase in brightness is required to be advanced relative in time as explained hereinbefore.
  • a copy of the clock waveform with the clocking transitions occurring mid-way through the pel clock cycle is achieved by passing the pel clock waveform from terminal 11 through a suitable phase shift circuit 17. Since in this embodiment, the pel clock waveform is symmetrical, a 1/2-pel cycle phase shift is most readily achieved by simple inversion.
  • the copy of the pel clock waveform phase shifted by 1/2-pel clock cycle is shown as waveform (d) in FIG. 5 is identified as (PEL CL).
  • This phase-shifted copy of the original pel clock is applied over line 18 as one input to multiplexor 16.
  • the 1/2-pel phase-shifted copy of the original pel clock is applied over line 18 as one input to multiplexor 16.
  • the 1/2-pel phase-shifted the clock waveform is itself separately passed through delay circuit 19 in order to impart an additional small phase shift equal to a predetermined delay (dt).
  • the additionally delayed phase shifted clock waveform is shown as waveform (e) in FIG. 5 and is identified as (DELAYED PEL CL).
  • This delayed copy of the clock waveform is applied over line 20 as a second input to multiplexor 16.
  • the arrangement is such that when the output from the compare circuit is high, a clock transition from the undelayed copy of the shifted pel clock (PEL CL) is gated to the output of the multiplexor and when the output is low, a clock transition from the additionally delayed copy of the shifted pel clock (DELAYED PEL CL) is gated to the output of the multiplexor.
  • the resultant pel clock waveform with re-timed or corrected transitions appearing on line 21 from the output of the multiplexor is shown as waveform (f) in FIG. 5. From this it is seen that three of the clock transitions in the waveform coincide with corresponding transitions in the 1/2-pel phase shifted clock of waveform (d) whereas the remaining clock transitions in the waveform coincide with corresponding transitions in the delayed version of this clock of waveform (e).
  • the pel values supplied successively to data input of the latch are gated to its output line 23 under timing control of the re-timed clock transitions of the clock waveform from the multiplexor 16.
  • the resultant selectively stretched pel data waveform with the three black-to-white transitions advanced relative to the remaining waveform transitions by the small time predetermined interval (dt) is shown as waveform (g) in FIG. 5.
  • the compare circuit 14 is expanded so that instead of being a simple bi-level comparator it is operable to compare two 3-bit values each pel period and to provide an output signal having an up-level each time the intensity value of the current pel exceeds that of the preceding pel.
  • This binary output signal from the comparator is used to select, by means of the multiplexor gating circuit 16, clocking transitions from either the nominal 1/2-pel cycle phase shifted clock or clocking transitions from the additionally delayed clock. This in turn is used to gate the bit values representing the current pel intensity from the three corresponding stages of the three shift registers through three associated latches 22.1, 22.2, and 22.3 so as to drive the video amplifier.
  • a comparator suitable for comparing two multi-bit binary values is shown in FIG. 6 within the dotted outline of block 14.
  • the example selected for the purpose of illustration compares two three bit numbers A0, B0, C0 and A1, B1, C1 where A0 and A1 are the most significant bits.
  • the value A0, B0, C0 represents the intensity of the preceding pel of the pel data stream and is current held in the three extra stages S0.1, S0.2, S0.3
  • the value A1, B1, C1 represent the intensity of the current pel of the data stream and is currently held in the three stages S1.1, S1.2, S1.3 of the three parallel shift registers 10.1, 10.2, 10.3.
  • Each corresponding bit value from the two numbers is applied simultaneously as inputs to comparator over lines 12.1, 12.2, 12.3 and 13.1, 13.2, 13.3 to each of three AND-gates (24, 25, 26) and to each of two OR-gates (27, 28).
  • the inputs to the gates receiving the bit values representing the preceding pel in stages S0.1, S0.2, S0.3 are all inverting inputs as designated by the small circles in the circuit diagram.
  • an up-level signal from AND-gate 24 indicates the bit condition A1>A0
  • an up-level signal from AND-gate 25 indicates the bit condition B1>B0
  • an up-level signal from AND-gate 26 indicates the bit condition C1>C0.
  • the signal level output from an OR-gate is the inverse of that of its associated AND-gate.
  • the only occasion where there is no output from an OR-gate (27 or 28) is when the current pel is brighter than the preceding pel that is PEL(N)>PEL(N-1). Should the comparison of the higher significant bits indicate that PEL(N) is brighter than PEL(N-1) then an output from the associated OR-gate (27 or 28) is used to inhibit further comparisons of lesser significant bits.
  • the output from the OR-gate 27 representing the result of comparison of the two most significant bits is applied as one input to a further AND-gate 29 which receives its second input from the AND-gate 25 comparing the second most significant bits B0 and B1.
  • the output from OR-gate 27 is further applied as input to a 3 input AND-gate 30 which receives as its other two inputs the outputs from OR-gate 28 representing the result of comparison of the two second most significant bits B0 and B1, the outputs from the AND-gate 26 representing the result of comparison of the two least significant bits C0 and C1.
  • the output from the three AND-gates 24, 29 and 30 are applied as inputs to a 3 input OR-gate 31.
  • An up-level signal through OR-gate 31 from AND-gate 24, or from AND-gate 25 through OR-gate 29, or from AND-gate 28 through OR-gate 30 indicates the sought for condition of PEL(N)>PEL(N-1).
  • bit A1 >bit B1 an up-level signal is gated through AND-gate 24 and OR-gate 31 to output line 15 to multiplexor 16. Simultaneously, a down-level output from OR-gate 27 inhibits the results of comparisons of lesser significant bits being gated through AND-gates 29 and 30. If bit A1 ⁇ bit A0, then the OR-gate 27 output is at an up-level enabling one input of OR-gate 29. In the event that bit B1 >bit B0 then an up-level output from AND-gate 25 is gated through enabled AND-gate 29 and OR-gate 31 to output line 15.
  • OR-gate 27 output and OR-gate 28 output are both at an up-level enabling two inputs of OR-gate 30. If bit C1>bit C0 then an up-level output from AND-gate 26 is gated through enabled AND-gate 30 and OR-gate 31 to output line 15. It is seen that by addition of further logic stages as shown in phantom outline in FIG. 6 this comparator can easily be extended to be operable to compare pel values in excess of 3 bits. Finally, in order to equalize signal transmission time through the circuit by the various different routes, an additional logic stage 32 is provided between the output of AND-gate 24 and the input of OR-gate 31.
  • the pel waveform in this embodiment is symmetrical in shape and a half-pel period phase shift is achieved simply by inversion.
  • a non-symmetrical waveform would require a different means of phase shifting. Accordingly, as shown in FIG. 6, the circuit within the dotted outline of block 17 to achieve the 1/2-pel period phase shift is represented by a simple inverter 33.
  • the small delay (dt) imparted to this 1/2-pel period phase shifted clock is provided by the pulse transmission delays provided by a number of series connected simple logic circuits. It has been found convenient to provide the means for selecting not just one value of delay (dt) but several different values dt1, dt2 . . . dtn, each individually selectable to suit the operating characteristics of the display system in which the circuit is to be employed. As shown within the dotted outline of block 19 the value of the delay is selected by tapping the signal at various points from the AND-gates 34.1, 34.2, 34.2, . . . 34.(x-1) connected in series. All gates are one-input gates. The tap connection from the input of each AND-gate 34.1, 34.2 . . .
  • selection of gate 35.1 by energization of its SELECT (dt1) input delays the phase shifted pel clock waveform (PEL CL) by the shortest time, namely the sum of the transmission delays of the two logic units, namely 35.1 and 36.
  • Selection of gate 35.2 by energization of its SELECT (dt2) input delays the phase shifted pel clock waveform by an amount equal to the sum of the transmission delays of three logic circuits, namely 34.1, 35.2 and 36.
  • Selection of gate 35.3 delays the phase shifted pel clock waveform by the sum of the transmission delays of three logic units and so on.
  • the maximum delay equal to the sum of the transmission delays of all the series connected input AND-gates 34.1, 34.2 . . . 34. (x-1), select AND-gate 35.x, and the OR-gate 36 is provided by energization of the SELECT (dtx) input to AND-gate 35.x.
  • the multiplexor shown in dotted outline 16 in FIG. 6 consists simply of two AND-gates 37 and 38.
  • the nominal or 1/2-pel period phase shifted clock waveform from inverter 33 is applied as one input to AND-gate 37 and the delayed clock waveform from delay circuit 19 is applied as one input to AND-gate 38.
  • the comparator output signal on line 15 is applied as the other input to AND-gate 37 and AND-gate 38.
  • the second input of AND-gate 38 is an inverting input as indicated by the symbol in the representation of the circuit in FIG. 6.
  • the output signal from one or other of the two AND-gates 37 and 38 is passed by OR-gate 39 to the output line 21.
  • the output clock waveform with re-timed clock transitions from OR-gate 39 is applied to the clock inputs of three latches 22.1, 22.2, 22.3 in parallel, each corresponding to the single latch 22 required for the bi-level embodiment described with reference to FIG. 4.
  • the output lines 12.1, 12.2, 12.3 from the three corresponding shift register stages S1.1, S1.2, S1.3 are applied to the data input of the latches respectively.
  • portions of the connecting lines from the shift register outputs to the latch inputs have been omitted. Accordingly, with this arrangement the 3-bit binary values appearing in parallel each pel clock cycle in the last stages S1.1, S1.2, S1.3 of the shift registers are gated through the three latches onto output lines 23.1, 23.3, 23.3.
  • the signal levels on this three line output bus represent the data for display by the display system with selected transition re-timed to compensate for video amplifier rise time distortion as described in detail hereinabove.
  • a pel is represented by more than 3 bits, a corresponding number of output latched will be required as illustrated by the additional latch shown in dotted outline in the figure.

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  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Transforming Electric Information Into Light Information (AREA)
US06/826,692 1985-03-04 1986-02-06 Video bit transition advancement circuit Expired - Fee Related US4734691A (en)

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EP85301482A EP0193663B1 (en) 1985-03-04 1985-03-04 Video display system
EP85301482.7 1985-03-04

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US (1) US4734691A (enrdf_load_stackoverflow)
EP (1) EP0193663B1 (enrdf_load_stackoverflow)
JP (1) JPS61204687A (enrdf_load_stackoverflow)
DE (1) DE3580475D1 (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4853683A (en) * 1988-01-25 1989-08-01 Unisys Corporation Enhanced capacity display monitor
CN1311418C (zh) * 2002-07-31 2007-04-18 精工爱普生株式会社 电子电路、电光装置和电子仪器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0069994A2 (de) * 1981-07-14 1983-01-19 GRUNDIG E.M.V. Elektro-Mechanische Versuchsanstalt Max Grundig holländ. Stiftung & Co. KG. Verfahren und Schaltungsanordnung zur Verbesserung der Wiedergabe alpha-numerischer Zeichen und Grafik auf Rasterbildschirmen
EP0104289A1 (en) * 1982-09-29 1984-04-04 International Business Machines Corporation Video display system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0069994A2 (de) * 1981-07-14 1983-01-19 GRUNDIG E.M.V. Elektro-Mechanische Versuchsanstalt Max Grundig holländ. Stiftung & Co. KG. Verfahren und Schaltungsanordnung zur Verbesserung der Wiedergabe alpha-numerischer Zeichen und Grafik auf Rasterbildschirmen
EP0104289A1 (en) * 1982-09-29 1984-04-04 International Business Machines Corporation Video display system
US4604614A (en) * 1982-09-29 1986-08-05 International Business Machines Corp. Video display system employing pulse stretching to compensate for image distortion

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, vol. 17, No. 11, Apr. 1975, pp. 3325 3327, M. H. Nasser et al.; Correction of Phase Distortion in a Television Receiver when used for Character Display Purposes . *
IBM Technical Disclosure Bulletin, vol. 17, No. 11, Apr. 1975, pp. 3325-3327, M. H. Nasser et al.; "Correction of Phase Distortion in a Television Receiver when used for Character Display Purposes".

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4853683A (en) * 1988-01-25 1989-08-01 Unisys Corporation Enhanced capacity display monitor
CN1311418C (zh) * 2002-07-31 2007-04-18 精工爱普生株式会社 电子电路、电光装置和电子仪器

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DE3580475D1 (de) 1990-12-13
JPH0261034B2 (enrdf_load_stackoverflow) 1990-12-18
EP0193663B1 (en) 1990-11-07
JPS61204687A (ja) 1986-09-10
EP0193663A1 (en) 1986-09-10

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