US4682402A - Semiconductor device comprising polycrystalline silicon resistor element - Google Patents

Semiconductor device comprising polycrystalline silicon resistor element Download PDF

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Publication number
US4682402A
US4682402A US06/610,827 US61082784A US4682402A US 4682402 A US4682402 A US 4682402A US 61082784 A US61082784 A US 61082784A US 4682402 A US4682402 A US 4682402A
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polycrystalline silicon
pattern
resistor element
section
forming
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US06/610,827
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Yasutaka Yamaguchi
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NEC Electronics Corp
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NEC Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/47—Resistors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/136—Resistors

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a resistor element made of polycrystalline silicon on a field insulating film formed on a major surface of a semiconductor substrate and a method of manufacturing the resistor element.
  • a plan configuration that is, a width and a length of a resistor element are designed so as to obtain a high resistance.
  • a width W of a resistor element can be made small up to a lower limit of a resolution of a photo-resist process, there are shortcomings that if design close to the lower limit is effected, fluctuations of the manufacturing conditions would become large and hence resistor elements having a stable resistance cannot be obtained.
  • a resistor element is formed by making a length L of the resistor element large, a degree of integration cannot be raised.
  • a specific resistance of a resistor element is raised.
  • a semiconductor layer normally used in a semiconductor device for forming a resistor element is used at the other portions of the device as wirings, gate electrodes, etc., and in view of the objects of use of these portions it is desirable to reduce the specific resistance as low as possible.
  • an addition of a manufacturing step of process is associated with shortcomings that it brings about rise of the cost, also defects are liable to occur and hence the yield is lowered.
  • a resistor element having high resistance can be formed by thinning a thickness of a semiconductor layer which makes the resistor element.
  • etching would be effected up to the silicon layer of the resistor element, resulting in formation of apertures in the layer. This becomes an issue especially when a reactive ion etching process in which anisotropic etching is possible, is employed for micro-fine patterning. Therefore, thinning of the thickness of the silicon layer of the resistor element is subjected to certain limitation.
  • the rate of polycrystalline silicon is 100 to 150 ⁇ /min.
  • the deviation of the respective etching rate becomes 20 to 40% in a reactor chamber.
  • a thickness that is as thick as 4000 to 6000 ⁇ must be removed by etching.
  • a uniformity within the resistor section would become very poor. Deviations in the film thickness of the resistor sections among the respective pellets or wafers would also become very large.
  • a long etching time is necessitated.
  • Another object of the present invention is to provide a method for manufacturing a semiconductor device in which the above-referred semiconductor device can be obtained without increasing steps of the manufacturing process.
  • a semiconductor device comprising a semiconductor substrate.
  • a first insulating film such as a field silicon oxide film is formed on a major surface of the semiconductor substrate, a resistor element being formed on the first insulating film.
  • the resistor element includes a first conductive layer made of a first silicon layer such as a polycrystalline silicon layer and having a resistor section for determining the resistance value of the resistor element. At least one contact section is adjacent to the resistor section and a second conductive layer made of a second silicon layer such as a polycrystalline silicon layer and is positioned on the contact section of the first conductive layer.
  • a second insulating film such as silicon oxide film or P.S.G.
  • the film covers the first and second conductive layers and has an aperture reaching the surface of the second conductive layer.
  • An electrode wiring layer connected to the surface of the said second conductive layer through the aperture and extends to the second insulating film.
  • the thickness of the first conductive layer, especially that of the resistor section is favorably 2000 ⁇ or less.
  • the upper surface of the resistor section may be lower than the upper surface of the contact section by favorably 2000 ⁇ or less.
  • the shape of the second conductive layer may be island-like, and the total thickness of the second conductive layer and the contact section of the first conductive layer is favorably 5000 ⁇ or more.
  • the first and second conductive layers of the resistor element can be made with electrodes or wiring layers of the other element in the same semiconductor substrate.
  • a semiconductor device comprises a semiconductor substrate.
  • a first insulating film is selectively formed on a major surface of the substrate.
  • An active region of the substrate is adjacent to the field insulating film.
  • a resistor element is provided on the field insulating film.
  • a stacked-gate field effect transistor namely an erasable programmable read-only memory element (hereinafter abbreviated as EPROM element), is provided on the active region.
  • the resistor element includes a first conductive layer made of a first polycrystalline silicon layer and has a resistor section for determining the resistance of the resistor element and a contact section adjacent to the resistor section.
  • a second conductive layer is made of a second polycrystalline silicon, positioned on said contact section of the first conductive layer and having an island-shaped plan configuration.
  • the EPROM element includes a floating gate electrode made of the first polycrystalline silicon layer and a control gate electrode made of the second polycrystalline silicon layer.
  • a method of manufacturing a semiconductor device comprising the steps of forming a first insulating film on a semiconductor substrate, forming a first polycrystalline silicon pattern on the first insulating film, forming a island-like pattern of a second polycrystalline silicon on a predetermined portion of the first polycrystalline silicon pattern, covering a second insulating film over the first and second polycrystalline silicon, opening an aperture reached to the island-like pattern of the second polycrystalline silicon in the second insulating film by a reactive ion etching method, and forming a wiring layer in contact with the upper surface of the island-like pattern through said aperture.
  • a portion of the first polycrystalline silicon pattern adjacent to the predetermined portion may be reduced by 2000 ⁇ or less, after forming the first polycrystalline silicon pattern on the first insulating film.
  • the first and second polycrystalline silicon may be used as a resistor element.
  • the resistance of the resistor element is determined by a portion of the first polycrystalline silicon pattern on which the island-like second polycrystalline silicon is not provided.
  • the thickness of the portion used as the resistor section is favorably 2000 ⁇ or less to obtain high resistance without sacrificing the degree of integration.
  • the sum of the thickness of the predetermined portion of the first polycrystalline and that of the second polycrystalline is favorably 5000 ⁇ more to obtain a reliable contact structure.
  • a second conductive layer is provided on the contact sections of the thin first conductive layer.
  • the apertures for contacts in the second insulating film are provided so as to reach the surface of the second conductive layer. Accordingly, upon opening the contact apertures in the second insulating film, an accident would not occur such that undesired apertures may be opened in the first conductive layer which was made thin for the purpose of realizing a high resistance.
  • the electrode wiring layer for making ohmic contact with the second conductive layer can be formed of a metallic layer made of aluminium or the like.
  • a floating gate in EPROM element provided in another portion of the semiconductor device can be formed in the same step of process as the first conductive layer. In other words, no problem would arise even if the conductive layer is formed to have a thin film thickness for the purpose of increasing the sheet resistance R s of the resistor and is used as a floating gate in an EPROM element.
  • a control gate electrode of the above-mentioned EPROM element, or a gate electrode of a conventional insulated gate field effect transistor (hereinafter abbreviated as IGFET) or wiring layers to be directly connected to impurity regions provided in a semiconductor substrate and serving as a source and a drain in the IGFET can be formed simultaneously with formation of the above-described second conducting layer.
  • IGFET insulated gate field effect transistor
  • This second conductive layer can be thick because it is irrelevant to the enhancement of a resistance of the resistor.
  • the wiring layer can be advantageously formed thick in order to realize a low resistance, the thickness of the second conductive layer, control gate electrodes and wiring layers can be made thick, taking into consideration the easiness of the pattering.
  • the metallic wiring layer to be connected to the control gate electrodes and the wiring layer to be connected to the impurity regions in the semiconductor substrate can be formed.
  • the first conductive layer can be converted into a resistor having a further high resistance by partly etching away the first conductive layer within the range of 2000 ⁇ or smaller in depth as measured from its surface as mentioned above. In the case of etching away within the range of 2000 ⁇ or smaller in depth,the deviation of a film thickness and the uniformity among the produced resistors would not become an issue.
  • FIGS. 1A through 1E are cross-sectional views showing successive steps in a method of manufacturing a semiconductor device in the prior art
  • FIG. 2 is a plan view showing the portion of a resistor element shown in FIG. 1E,
  • FIGS. 3A through 3E are cross-sectional views showing successive steps in a method of manufacturing a semiconductor device according to a first preferred embodiment of the present invention
  • FIG. 4 is a plan view showing the portion of resistor element in FIG. 3E,
  • FIG. 5A is a plan view showing a second preferred embodiment of the present invention.
  • FIG. 5B is a cross-sectional view taken along line B-B' in FIG. 5A as viewed in the direction of arrows.
  • FIGS. 1A through 1E and FIG. 2 in which it is assumed that a resistor element having high resistance is manufactured jointly with an IGFET, especially with an EPROM element, by increasing a length L of the resistor element.
  • a resistor element having high resistance is manufactured jointly with an IGFET, especially with an EPROM element, by increasing a length L of the resistor element.
  • a thick field oxide film 2 for isolating elements has been grown on a P-type semiconductor substrate 1 as buried in the substrate, a first gate insulating film 3 is formed.
  • a P-type impurity for threshold control such as, for instance, boron
  • a first polycrystalline silicon layer 4 is grown, then a photo-resist 5 is deposited and pattering is carried out (FIG. 1A).
  • the first polysilicon layer 4 is etched by employing the photo-resist 5 as a mask, and thereby a resistor element 41 and a first gate electrode 42 which serves as a floating gate, are formed. Thereafter, an N-type impurity is ion-implanted to form source and drain regions 6, and a second gate insulating film 7 is formed by thermal oxidation. At this moment, a silicon oxide film 27 of about 500 ⁇ thickness is also formed on the surface of the resistor element 41, and on the source and drain regions 6 is also formed a silicon oxide film 17 that is thicker than the first gate insulating film 3. Subsequently, the silicon oxide film 17 at a buried contact portion 8 is removed by making use of the photo-resist 15 as a mask (FIG. 1B).
  • an insulating film 10 made of silicon dioxide or the like is grown above the electrodes 91 and 92, for instance, through a CVD process, and then predetermined apertures 11 are formed by a reactive ion etching process (FIG. 1D). It is to be noted that in FIGS. 1D and 1E the silicon oxide films 27 and 17 are depicted as included in the insulating film 10.
  • electrode wirings 12 are formed by depositing aluminium and pattering the aluminum layer, and thereby a semiconductor device including a resistor and an EPROM element is completed (FIGS. 1E and 2).
  • the sheet resistance R s of the resistor element 41 and the floating gate 42 in FIGS. 1E and 2 is about 150 ⁇ 50 ⁇ / ⁇ and the film thickness in the illustrated embodiment is about 6000 ⁇ .
  • the phenomenon that a withstand voltage of the second gate insulating film 7 formed on the first gate electrode 42 (floating gate) is lowered, would arise, and therefore, it is not favorable to lower the impurity concentration merely for the purpose of increasing the sheet resistance R s .
  • a first gate insulating film 3 is formed.
  • a first polycrystalline silicon layer 14 of 1300 ⁇ thickness is grown, then a photo-resist 5 is deposited thereon and patterning is effected therefor.
  • the layer 14 has the same impurity density of N type that of the layer 4 in FIG. 1. (FIG. 3A).
  • a portion 51 serving as a resistor element and a first gate electrode 52 serving as a floating gate are formed by etching the first polycrystalline silicon layer 14, and thereafter an N-type impurity is introduced by ion-implantation to form source and drain regions 6.
  • a second gate insulating film 17 is formed on the upper surface and side surfaces of the first gate electrode 52 by thermal oxidation, and at the same time a thermally oxidized film 27 of 600 ⁇ thickness is formed also on the upper surface and side surfaces of the resistor portion 51. Then the thickness of the first gate electrode 52 and that of the resistor portion 51 become 1000 ⁇ .
  • photo-resists 45 and 45' which have been subjected to patterning, are formed (FIG. 3B).
  • etching is carried out by employing these photo-resists 45 and 45' as a mask to remove the thermally oxidized silicon film on a buried contact 8 and also to remove the opposite end parts of the thermally oxidized silicon film 27 on the resistor portion 51, which parts are not coated with the photo-resist 45'.
  • the length of this photo-resist 45' and hence the length of the remaining silicon oxide film 27 would define the length of the resistor section which determines the resistance value of the resistor element.
  • a second polycrystalline silicon layer 9 of N-type having a thickness of 4000 to 8000 ⁇ is formed, then a photo-resist 55 is deposited thereon and patterning is carried out (FIG. 3C).
  • the second polycrystalline silicon layer 9 is subjected to etching by making used of the photo-resist 55 as a mask to form a second gate electrode 91 serving as a control gate, a lead-out wiring layer 92 and island-like layers 93 and 93'.
  • the silicon oxide film 27 remaining on the resistor portion 51 is used as a stopper for preventing the first polycrystalline silicon layer of the resistor portion 51 formed very thin from being etched.
  • the second polycrystalline silicon layer is etched by the anisotripic reactive ion etching
  • one or two kind of gases selected from a group consisting of CCl 4 , CClF 3 , CCl 2 F 2 and CCl 3 F gases is employed with O 2 gas or N 2 gas under the condition of 10 to 50 Pa (pascal) pressure.
  • the etching rate of polycrystalline silicon is 500 to 1500 ⁇ /min.
  • the etching rate of thermal silicon oxide is only 20 ⁇ /min.
  • the silicon oxide film 27 can be effectively used as an etching stopper film.
  • metallic wiring layers 12, 12' and 12" connected to the respective portions and extending on the silicon dioxide film are formed by depositing aluminium and patterning the aluminium layer.
  • a semiconductor device including a resistor and an EPROM element is completed (FIGS. 3E and 4).
  • the resistor element comprises the first polycrystalline silicon layer 51 including resistor section 51' and contact sections 51" and resistor lead-out electrodes, that is, island-like layers 93 and 93' made of the second layer.
  • the central section 51' of the first polycrystalline layer 51 that is, the resistor section having a length L' determines the resistance value
  • the opposite end sections, that is contact sections 51" of the first polycrystalline silicon layer 51 and the island-like electrodes 93 and 93' thereon jointly form contact structure.
  • the impurity concentration and the width W of the resistor in FIG. 3 are identical to those shown in FIG. 1. Accordingly, in order to realize the same resistance value as that of the resistor in the prior art as illustrated in FIG.
  • the length L' of the resistor section according to the present invention can be reduced to about 1/6 times the length L of the resistor section of the resistor element shown in FIG. 1, and hence according to the present invention, a degree of integration can be enhanced.
  • the first and second polycrystalline silicon layers are present under the apertures 21 and the thickness of the both layers amounts to about 5000 to 9000 ⁇ in total, even if the surface of these polycrystalline layers should be etched upon etching the above-mentioned apertures, connection having an improved reliability can be realized.
  • resistor lead-out electrodes 93 and 93' can be formed simultaneously with formation of the second gate electrode 91 and the lead-out wiring layer 92 by etching the second polycrystalline silicon layer 9, there is no need to add a special stepand the of the process.
  • FIGS. 5 component parts having the same functions as those in the first preferred embodiment shown in FIGS. 3 and 4 are given like reference numerals. It is to be noted that in FIG. 5A an insulating film 10 is omitted from illustration for the purpose of clarification of the structure.
  • the photo-resist 45' is not provided in the step shown in FIG. 3B, and thereby the silicon dioxide film 27 is entirely removed. Thereafter, the opposite end portions of the resistor serving as contact sections are masked by photo-resists, also other portions are masked, and etching is carried out with only the center section which determines the resistance value exposed to make this portion thinner. More particularly, the first polycrystalline silicon layer before this etching has a thickness of 3000 ⁇ . In this polycrystalline silicon layer, only the central section which is later converted into a resistor section is exposed, then preferably reactive and anisotropic etching is carried out to remove out a thickness part of 1500 ⁇ . Accordingly, the thickness of the remaining layer becomes 1500 ⁇ .

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JP58085280A JPS59210658A (ja) 1983-05-16 1983-05-16 半導体装置の製造方法
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Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2215123A (en) * 1988-02-16 1989-09-13 Stc Plc Transistor array with polysilicon resistors
GB2223624A (en) * 1988-08-19 1990-04-11 Murata Manufacturing Co Method of manufacturing a chip coil
US4968645A (en) * 1985-12-20 1990-11-06 Sgs-Thomson Microelectronics S.R.L. Method for manufacturing MOS/CMOS monolithic integrated circuits including silicide and polysilicon patterning
WO1992003843A1 (en) * 1990-08-13 1992-03-05 Mitel Corporation Method of manufacturing polycrystalline capacitors and resistors during integrated circuit process and integrated circuit obtained therewith
US5457062A (en) * 1989-06-30 1995-10-10 Texas Instruments Incorporated Method for forming gigaohm load for BiCMOS process
WO1997008747A1 (de) * 1995-08-28 1997-03-06 Siemens Aktiengesellschaft Verfahren zur herstellung einer eeprom-halbleiterstruktur
EP0764986A1 (en) * 1995-09-19 1997-03-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
US5620922A (en) * 1994-03-18 1997-04-15 Seiko Instruments Inc. Method for fabricating CMOS device having low and high resistance portions and wire formed from a single gate polysilicon
WO1998018152A3 (en) * 1996-10-18 1998-10-08 Micro Devices Corp California Programmable integrated passive devices and methods therefor
US5940712A (en) * 1995-10-06 1999-08-17 Micron Technology, Inc. Method of forming a resistor and integrated circuitry having a resistor construction
US5998275A (en) * 1997-10-17 1999-12-07 California Micro Devices, Inc. Method for programmable integrated passive devices
US6130138A (en) * 1996-10-14 2000-10-10 Samsung Electronics Co., Ltd. Methods of forming integrated circuit capacitors having doped dielectric regions therein
US6130137A (en) * 1997-10-20 2000-10-10 Micron Technology, Inc. Method of forming a resistor and integrated circuitry having a resistor construction
US6228735B1 (en) * 1998-12-15 2001-05-08 United Microelectronics Corp. Method of fabricating thin-film transistor
US6274452B1 (en) * 1996-11-06 2001-08-14 Denso Corporation Semiconductor device having multilayer interconnection structure and method for manufacturing the same
USRE38550E1 (en) 1996-10-18 2004-07-06 California Micro Devices, Inc. Method for programmable integrated passive devices
US20040175924A1 (en) * 2003-03-07 2004-09-09 Samsung Electronics Co., Ltd. Semiconductor device having resistor and method of fabricating the same
US20050042882A1 (en) * 1998-07-29 2005-02-24 Ichiro Ito Method of etching metallic thin film on thin film resistor
US20060220003A1 (en) * 2005-04-05 2006-10-05 Mitsuhiro Noguchi Semiconductor device
US20060267143A1 (en) * 2005-05-31 2006-11-30 Kikuko Sugimae Semiconductor integrated circuit device and manufacturing method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62219653A (ja) * 1986-03-20 1987-09-26 Hitachi Ltd 半導体装置の製造方法
JP5098214B2 (ja) * 2006-04-28 2012-12-12 日産自動車株式会社 半導体装置およびその製造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3364085A (en) * 1963-05-18 1968-01-16 Telefunken Patent Method for making semiconductor device
US4270262A (en) * 1977-03-04 1981-06-02 Hitachi, Ltd. Semiconductor device and process for making the same
US4278989A (en) * 1978-01-20 1981-07-14 Fujitsu Limited Semiconductor device having cross wires
US4317274A (en) * 1979-01-26 1982-03-02 Hitachi, Ltd. Method of producing a semiconductor device
US4380773A (en) * 1980-06-30 1983-04-19 Rca Corporation Self aligned aluminum polycrystalline silicon contact
US4441249A (en) * 1982-05-26 1984-04-10 Bell Telephone Laboratories, Incorporated Semiconductor integrated circuit capacitor
US4477962A (en) * 1978-05-26 1984-10-23 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50134389A (enrdf_load_stackoverflow) * 1974-04-10 1975-10-24
JPS54137982A (en) * 1978-04-19 1979-10-26 Hitachi Ltd Semiconductor device and its manufacture
JPS577150A (en) * 1980-06-16 1982-01-14 Fujitsu Ltd Manufacture of semiconductor device
JPS59207652A (ja) * 1983-05-11 1984-11-24 Hitachi Ltd 半導体集積回路装置およびその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3364085A (en) * 1963-05-18 1968-01-16 Telefunken Patent Method for making semiconductor device
US4270262A (en) * 1977-03-04 1981-06-02 Hitachi, Ltd. Semiconductor device and process for making the same
US4278989A (en) * 1978-01-20 1981-07-14 Fujitsu Limited Semiconductor device having cross wires
US4477962A (en) * 1978-05-26 1984-10-23 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4317274A (en) * 1979-01-26 1982-03-02 Hitachi, Ltd. Method of producing a semiconductor device
US4380773A (en) * 1980-06-30 1983-04-19 Rca Corporation Self aligned aluminum polycrystalline silicon contact
US4441249A (en) * 1982-05-26 1984-04-10 Bell Telephone Laboratories, Incorporated Semiconductor integrated circuit capacitor

Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4968645A (en) * 1985-12-20 1990-11-06 Sgs-Thomson Microelectronics S.R.L. Method for manufacturing MOS/CMOS monolithic integrated circuits including silicide and polysilicon patterning
GB2215123B (en) * 1988-02-16 1990-10-24 Stc Plc Improvement in integrated circuits
GB2215123A (en) * 1988-02-16 1989-09-13 Stc Plc Transistor array with polysilicon resistors
GB2223624A (en) * 1988-08-19 1990-04-11 Murata Manufacturing Co Method of manufacturing a chip coil
US5071509A (en) * 1988-08-19 1991-12-10 Murata Mfg. Co., Ltd Chip coil manufacturing method
GB2223624B (en) * 1988-08-19 1993-03-24 Murata Manufacturing Co Chip coil and manufacturing method thereof
US5457062A (en) * 1989-06-30 1995-10-10 Texas Instruments Incorporated Method for forming gigaohm load for BiCMOS process
WO1992003843A1 (en) * 1990-08-13 1992-03-05 Mitel Corporation Method of manufacturing polycrystalline capacitors and resistors during integrated circuit process and integrated circuit obtained therewith
US6255700B1 (en) 1994-03-18 2001-07-03 Seiko Instruments Inc. CMOS semiconductor device
US5620922A (en) * 1994-03-18 1997-04-15 Seiko Instruments Inc. Method for fabricating CMOS device having low and high resistance portions and wire formed from a single gate polysilicon
US5970338A (en) * 1995-08-28 1999-10-19 Siemens Aktiengesellschaft Method of producing an EEPROM semiconductor structure
WO1997008747A1 (de) * 1995-08-28 1997-03-06 Siemens Aktiengesellschaft Verfahren zur herstellung einer eeprom-halbleiterstruktur
US6124160A (en) * 1995-09-19 2000-09-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
KR100421520B1 (ko) * 1995-09-19 2004-06-24 마츠시타 덴끼 산교 가부시키가이샤 반도체장치및그제조방법
US5879983A (en) * 1995-09-19 1999-03-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
EP0764986A1 (en) * 1995-09-19 1997-03-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
US6492672B1 (en) 1995-09-19 2002-12-10 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US5940712A (en) * 1995-10-06 1999-08-17 Micron Technology, Inc. Method of forming a resistor and integrated circuitry having a resistor construction
US6130138A (en) * 1996-10-14 2000-10-10 Samsung Electronics Co., Ltd. Methods of forming integrated circuit capacitors having doped dielectric regions therein
WO1998018152A3 (en) * 1996-10-18 1998-10-08 Micro Devices Corp California Programmable integrated passive devices and methods therefor
USRE38550E1 (en) 1996-10-18 2004-07-06 California Micro Devices, Inc. Method for programmable integrated passive devices
US6281564B1 (en) 1996-10-18 2001-08-28 California Micro Devices, Inc. Programmable integrated passive devices
US6274452B1 (en) * 1996-11-06 2001-08-14 Denso Corporation Semiconductor device having multilayer interconnection structure and method for manufacturing the same
US5998275A (en) * 1997-10-17 1999-12-07 California Micro Devices, Inc. Method for programmable integrated passive devices
US6130137A (en) * 1997-10-20 2000-10-10 Micron Technology, Inc. Method of forming a resistor and integrated circuitry having a resistor construction
US20050042882A1 (en) * 1998-07-29 2005-02-24 Ichiro Ito Method of etching metallic thin film on thin film resistor
US7223668B2 (en) * 1998-07-29 2007-05-29 Denso Corporation Method of etching metallic thin film on thin film resistor
US6228735B1 (en) * 1998-12-15 2001-05-08 United Microelectronics Corp. Method of fabricating thin-film transistor
US20040175924A1 (en) * 2003-03-07 2004-09-09 Samsung Electronics Co., Ltd. Semiconductor device having resistor and method of fabricating the same
US20060220003A1 (en) * 2005-04-05 2006-10-05 Mitsuhiro Noguchi Semiconductor device
US8044450B2 (en) * 2005-04-05 2011-10-25 Kabushiki Kaisha Toshiba Semiconductor device with a non-volatile memory and resistor
US20060267143A1 (en) * 2005-05-31 2006-11-30 Kikuko Sugimae Semiconductor integrated circuit device and manufacturing method thereof
US7906816B2 (en) * 2005-05-31 2011-03-15 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device including memory cells having floating gates and resistor elements

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JPH0454979B2 (enrdf_load_stackoverflow) 1992-09-01

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