GB2215123A

GB2215123A - Transistor array with polysilicon resistors

Info

Publication number: GB2215123A
Application number: GB8803505A
Authority: GB
Inventors: Robert William Hunt; John Michael Young; Roger Leslie Baker
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1988-02-16
Filing date: 1988-02-16
Publication date: 1989-09-13
Anticipated expiration: 2008-02-16
Also published as: GB8803505D0; GB2215123B

Abstract

In a transistor array, such as a bipolar analogue array, comprising an array of cells 11, circuit function is determined by a customised resistor pattern. The resistors 16 comprise polysilicon deposited on the array. The transistors have polysilicon emitters and the polysilicon resistors may be formed from materials deposited simultaneously with these emitters. <IMAGE>

Description

IMPROVEMENT IN INTEGRATED CIRCUITS.

This invention relates to integrated circuits and in particular to transistor arrays in which circuit function is determined by the use of one or more customising masks.

Conventionally transistor arrays, e.g. bipolar analogue arrats, comprise an array of cells each formed from a number of transistors. Each cell is coupled to ablock of fixed value implanted or diffused resistors adjacent that cell. The particular function of the array is defined according to customer requirements by the provision of one or more customising metal layers which interconnect the transistors via particular series/parallel combinations of the fixed resistors.

This technique suffers from the disadvantage that serious constraints are placed on circuit design.

The length of any interconnect between a transistor and its associated resistor network in such a structure is, of necessity, longer than the ideal length. Furthermore, in such a construction, the design is often forced to route the interconnects to parts of the semiconductor die that may conflict with the required position of other interconnections. This limits the versatility and performance of the arrays.

The object of the present invention is to minimise or to overcome this disadvantage.

According to the invention there is provided a transistor array adapted to provide particular circuit functions by corresponding interconnection of the transistors, the array comprising a plurality of similar cells of transistors, and a plurality of resistors whereby selected transistors are coupled to define a predetermined circuit function, and wherein each said resistor comprises a body of polycrystalline silicon deposited on the array.

As the resistors are formed in the latter stages of processing they can be configured by a custom mask. This allows resistors of any required value to be placed at will or any part of the die. The metal routing task is thus reduced to that of interconnecting the transistors as required, the resistors being placed in the optimum positions to comply with positioning of the transistors interconnections.

An embodiment of the invention will now be described with reference to the accompanying drawings in which the single figure depicts in schematic form part of a transistor array. The invention is described below with reference to a bipolar analogue array, comprises an plurality of similar cells 11 of transistors disposed on a common semiconductor substrate 12. In the structure of the drawing, each cell consists of a pair of transistors each having a base 13 a 13 b, disposed in a common collector 14. Each transistor has a polycrystalline silicon (polysilicon) emitter body 15. Selected transistors of the array are coupled via polysilicon resistor tracks 16 routed via corridors 17 between the cells of array. Advantageously these tracks are deposited simultaneously with the transistor emitters using a customising mask. This provides the array with its desired circuit function. The polysilicon may be doped or undoped.

After provision of the polysilicon resistor pattern a further customising mask is employed to provide a desired metal interconnect (not shown). The chip is then mounted in a suitable package. The polysilicon resistors 16 may comprise a single polysilicon deposition or two polysilicon levels separated e.g. by oxide may be employed.

As the resistors are not formed until the latter part of the process there is no necessity to provide redundant resistors. This eases the constraints on chip space and simplifies the interconnection layout.

Claims

CLAIMS.

1. A transistor array adapted to provide particular circuit functions by corresponding interconnection of the transistors, the array comprising a plurality of similar cells of transistors, and a plurality of resistors whereby selected transistors are coupled to define a predetermined circuit function, and wherein each said resistor comprises a body of polychrystalline silicon deposited on the array.

2. A bipolar transistor analogue array adapted to provide particular circuit functions by corresponding interconnection of the transistors, the array comprising a plurality of similar cells each containing a pair of transistors disposed on a common collector and each having a polycrystalline (polysilicon) emitter, and a plurality of resistors whereby selected transistors are coupled to define a predetermined circuit function, and wherein each said resistor comprises a body of polysilicon deposited on the array.

3. A transistor array as claimed in claim 2, wherein the polysilicon resistors are formed from materials deposited simultaneously with the transmitter emitters.

4. A transistor array as claimed in claim 1 or 2, wherein the polysilicon resistors comprise first and second levels of polysilicon.

5. A transistor array substantially as described herein with reference to and as shown in the accompanying drawing.