US4417305A - Method for evaluating boolean expressions - Google Patents

Method for evaluating boolean expressions Download PDF

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Publication number
US4417305A
US4417305A US06/300,133 US30013381A US4417305A US 4417305 A US4417305 A US 4417305A US 30013381 A US30013381 A US 30013381A US 4417305 A US4417305 A US 4417305A
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boolean
result
expression
register
value
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Viktors Berstis
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International Business Machines Corp
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International Business Machines Corp
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Priority to JP57112614A priority patent/JPS5848153A/ja
Priority to EP82106250A priority patent/EP0073901A3/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT

Definitions

  • This invention relates to a method for evaluating boolean expressions in a computer system.
  • first and second vectors are formed from the boolean expression.
  • the first vector selects the variables of the expression as it is translated during the evaluation steps with the variables in a string as the translate table.
  • the result of the translation is set in a work area and is logically combined with the second vector which specifies the AND and OR logical operations, using an exclusive OR function.
  • the result of this logical operation is then translated with and upon itself whereby the Boolean expression is evaluated and the state of the last position in the result of this translation is the value of the Boolean expression.
  • FIG. 1 is a flow diagram illustrating the steps for forming the control vectors
  • FIG. 2 is a flow diagram illustrating the steps of using these vectors in the evaluation of the Boolean expressions.
  • the invention is illustrated by way of example as a method implementable in any computer system having a translate instruction or capable of simulating or emulating such an instruction.
  • the IBM computer system 360 which is shown and described in U.S. Pat. No. 3,400,371 issued Sept. 3, 1968 entitled “Data Processing System” can be used to implement the present invention for evaluating Boolean expressions.
  • Boolean expressions consists of performing the logical operations indicated by the expression using the values of the variables in the expression to derive a true or false result for the expression.
  • the normal form of a Boolean expression is discussed in "Introduction to Switching Theory and Logical Design” by Frederick J. Hill and Gerald R. Peterson 1968 John Wiley and Sons particularly in Chapter 6. All Boolean expressions can be expressed in either normal form, sum of products or in the form of product of sums. The two forms are duals of each other. In the normal sum of products form, the word "sum” represents the logical OR (1) operation and "product” represents the AND (&) operation.
  • the sum of products form of a Boolean expression can be the following expression E where E is represented as a sum of any number of product terms Pi:
  • Each literal Li consists of either the Boolean variable Ii or the inverse of the Boolean variable Ii.
  • the normal methods for evaluating Boolean expressions using a general purpose computer system include parsing and compiling the expression into instructions which are then executed or by parsing the Boolean expression and interpretively executing the parse tree. These methods are relatively slower than the present invention which, instead of parsing the expression and compiling instructions, forms two control vectors X and Y and then uses these vectors for evaluating the expression.
  • the first step in forming the control vectors X and Y, FIG. 1, is:
  • Step 0
  • Steps 2-4 are repeated until the entire expression E has been processed.
  • the evaluation of the Boolean expression, FIG. 2, is accomplished by translating the X vector using the Boolean variables I1, I2, etc., as the translate table. Translation in this instance is a process as described in the referenced U.S. Pat. No. 3,400,371.
  • the Translate Instruction is described in this patent at Column 90, lines 25-52 using a format set forth on Column 88, lines 16-56 having a microcode logic embodied as in FIGS. 5NA1 to 5NA3.
  • the Translate Instruction is also described in IBM 360 and 370 Principles of Operation manuals GA22-6821-8 and GA22-7000-4 respectively.
  • the Translate Instruction used as a step to implement the present invention can best be understood by the following example.
  • the translate table is:
  • the next step of the evaluation process is to perform an exclusive OR (XOR) operation using the translated vector X and vector Y as operands.
  • XOR exclusive OR
  • the next step in the evaluation process is to translate the result of the exclusive OR operation using the result itself as the translate table.
  • the translation of each position in the result will be described to provide a clear understanding of the process.
  • the value 01 in position 01 translates to 01.
  • the value 00 in position 03 translates to 00 because the value 00 points to position 00 and the value in this position is 00.
  • the value 03 points to position 03 which has a value of 00.
  • the value 02 points to position 02 which has the value of I1.
  • I1, as previously noted, can have the value of 00 or 01.
  • the value in position 04 will be 00 (false) if either I1 or I3 is 00 (false) or will be 01 (true) only if I1 and I3 are both 01 (true). It is seen that upon completing the translation of position 04, the logical operation of ANDing I1 with I3 has been performed.
  • Position 04 contains the value of the sub-expression (I1 & I3).
  • the value 01 in position 05 points to position 01 which has a value of 01.
  • the value 04 in position 07 points to position 04 which has the value of I3.
  • the value of the sub-expression at position 04 is copied into position 07.
  • Postion 08 after translation has a value which represents the result of the logical operation of (I1&I3)
  • the value 04 in position 09 copies the value of the sub-expression at position 04 into position 09.
  • Position 0C has the value of the Boolean expression (I1&I3)
  • the method of this invention simply uses a translate instruction, and an exclusive OR instruction followed by another translate instruction to evaluate the Boolean expression after forming the two control vectors X and Y from the Boolean expression
  • I is one of the exclusive-ored input variables.
  • X and Y are either constant (00 or 01), the value of some exclusive-ored input variable I or the value of some previously computed sub-expression.
  • I can be inverted either with the exclusive-or constant B or by interchanging X and Y.
  • the true/false value of I differs by only one bit (the units position). This means that N should always be even.
  • the following table shows the various possible logic results at position N+2 by selecting appropriate values for X and Y.
  • P and Q are results of another sub-expression earlier in the string, located at position P and Q, respectively.
  • any boolean expression can be computed.
  • equations would be written or converted to a "product of sums” or “sum of products” (as was the example), to simplify the construction of vector strings X and Y.
  • the head of string should contain 00 01 so that these two values are not altered during the translate.
  • the method of this invention could evaluate more than one boolean expression at a time; by using multivalued variables instead of binary valued variables; and optimizing the translate process to a minimum number of characters. For example, the first four characters of the example string need not be translated. If the boolean expressions are so complex that one 256 byte translate cannot accommodate them, then the result values of a previous translate can be input to a second translate which continues the evaluation of the expression(s). Thus the size of the boolean expression which can be evaluated is limited only by availability of computer storage space.

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  • Engineering & Computer Science (AREA)
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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
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US06/300,133 1981-09-08 1981-09-08 Method for evaluating boolean expressions Expired - Fee Related US4417305A (en)

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US06/300,133 US4417305A (en) 1981-09-08 1981-09-08 Method for evaluating boolean expressions
JP57112614A JPS5848153A (ja) 1981-09-08 1982-07-01 ブ−ル式の評価装置
EP82106250A EP0073901A3 (en) 1981-09-08 1982-07-13 Method for evaluating boolean expressions in a data processing system

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722071A (en) * 1985-04-19 1988-01-26 Pertron Controls, Corporation Compiler for evaluating Boolean expressions
US4831521A (en) * 1983-11-10 1989-05-16 General Signal Corporation Vital processor implemented with non-vital hardware
US5794227A (en) * 1989-12-23 1998-08-11 International Computers Limited Optimization of the order in which the comparisons of the components of a boolean query expression are applied to a database record stored as a byte stream
US20020041680A1 (en) * 2000-02-08 2002-04-11 George Cybenko System and methods for encrypted execution of computer programs
US6959314B1 (en) 2002-05-13 2005-10-25 Eurica Califorrniaa Method of translating Boolean algebra into basic algebra
US7406592B1 (en) * 2004-09-23 2008-07-29 American Megatrends, Inc. Method, system, and apparatus for efficient evaluation of boolean expressions
US7720807B1 (en) * 2007-01-17 2010-05-18 Square Zero, Inc. Representing finite node-labeled trees using a one bit encoding
US8655824B1 (en) 2011-03-07 2014-02-18 The Boeing Company Global policy framework analyzer
US10333696B2 (en) 2015-01-12 2019-06-25 X-Prime, Inc. Systems and methods for implementing an efficient, scalable homomorphic transformation of encrypted data with minimal data expansion and improved processing efficiency
US10706047B2 (en) * 2012-10-22 2020-07-07 Sap Se Boolean content search

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7735080B2 (en) * 2001-08-30 2010-06-08 International Business Machines Corporation Integrated system and method for the management of a complete end-to-end software delivery process

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001789A (en) * 1975-05-23 1977-01-04 Itt Industries, Inc. Microprocessor boolean processor
US4120043A (en) * 1976-04-30 1978-10-10 Burroughs Corporation Method and apparatus for multi-function, stored logic Boolean function generation
US4165534A (en) * 1977-04-25 1979-08-21 Allen-Bradley Company Digital control system with Boolean processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001789A (en) * 1975-05-23 1977-01-04 Itt Industries, Inc. Microprocessor boolean processor
US4120043A (en) * 1976-04-30 1978-10-10 Burroughs Corporation Method and apparatus for multi-function, stored logic Boolean function generation
US4165534A (en) * 1977-04-25 1979-08-21 Allen-Bradley Company Digital control system with Boolean processor

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin-Boolean Analysis Approach to Functional Macro Generation, Jun. 1977, vol. 20 No. 1 pp. 61-62. *
IBM Technical Disclosure Bulletin-Iterative Common Truth Set Detection Mechanism for Boolean Functin Satisfiability Recognition, Jun. 1974 vol. 17 No. 1 pp. 66-69. *
IBM Technical Disclosure Bulletin-Matrix Method of Modifying Logical Expressions, May 1976, vol. 18 No. 12 pp. 3958-3963. *

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4831521A (en) * 1983-11-10 1989-05-16 General Signal Corporation Vital processor implemented with non-vital hardware
US4722071A (en) * 1985-04-19 1988-01-26 Pertron Controls, Corporation Compiler for evaluating Boolean expressions
US5794227A (en) * 1989-12-23 1998-08-11 International Computers Limited Optimization of the order in which the comparisons of the components of a boolean query expression are applied to a database record stored as a byte stream
US7296163B2 (en) 2000-02-08 2007-11-13 The Trustees Of Dartmouth College System and methods for encrypted execution of computer programs
WO2001061905A3 (en) * 2000-02-08 2002-06-27 Dartmouth College System and methods for encrypted execution of computer programs
US20020041680A1 (en) * 2000-02-08 2002-04-11 George Cybenko System and methods for encrypted execution of computer programs
US6959314B1 (en) 2002-05-13 2005-10-25 Eurica Califorrniaa Method of translating Boolean algebra into basic algebra
US7406592B1 (en) * 2004-09-23 2008-07-29 American Megatrends, Inc. Method, system, and apparatus for efficient evaluation of boolean expressions
US7720807B1 (en) * 2007-01-17 2010-05-18 Square Zero, Inc. Representing finite node-labeled trees using a one bit encoding
US8655824B1 (en) 2011-03-07 2014-02-18 The Boeing Company Global policy framework analyzer
US10984331B2 (en) 2011-03-07 2021-04-20 The Boeing Company Global policy framework analyzer
US10706047B2 (en) * 2012-10-22 2020-07-07 Sap Se Boolean content search
US10333696B2 (en) 2015-01-12 2019-06-25 X-Prime, Inc. Systems and methods for implementing an efficient, scalable homomorphic transformation of encrypted data with minimal data expansion and improved processing efficiency

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JPS6314378B2 (cg-RX-API-DMAC7.html) 1988-03-30
JPS5848153A (ja) 1983-03-22
EP0073901A3 (en) 1985-05-02
EP0073901A2 (en) 1983-03-16

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