US4404661A - Semiconductor memory circuit - Google Patents

Semiconductor memory circuit Download PDF

Info

Publication number
US4404661A
US4404661A US06/202,822 US20282280A US4404661A US 4404661 A US4404661 A US 4404661A US 20282280 A US20282280 A US 20282280A US 4404661 A US4404661 A US 4404661A
Authority
US
United States
Prior art keywords
transistor
coupled
signal electrode
bit line
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US06/202,822
Other languages
English (en)
Inventor
Yasuji Nagayama
Makoto Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: NAGAYAMA, YASUJI, TANIGUCHI, MAKOTO
Application granted granted Critical
Publication of US4404661A publication Critical patent/US4404661A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Definitions

  • the present invention relates to semiconductor memory circuits. More particularly, the invention relates to a dynamic random access memory utilizing a MOS FET, hereinafter referred to as "a MOST.”
  • a MOST dynamic random access memory utilizing a MOS FET
  • MOSRAM dynamic random access memory utilizing a MOS FET
  • the chip area per bit is made small in order to prevent the total chip area from being larger than practical limits due to the desired large capacity of the memory. Accordingly, because of the small area per bit, a MOSRAM of this general type can store only a small amount of charge per bit. However, the small amount of charge stored per bit in each memory cell results in a small safe operational margin for reading data from the memory and increases the amount of "soft" error due to ⁇ rays. In order to overcome these difficulties, it is necessary that even a MOSRAM having a large capacity be so designed that the amount of charge stored per bit is not overly small.
  • the amount of charge Q stored in a memory cell in a MOSRAM of the single-transistor, single-capacitor type can, in general, be represented by the following equation:
  • Cs is the capacitance of the memory cell and Vs is the writing voltage of the memory cell.
  • the value Q can be increased by increasing the capacitance Cs or the voltage Vs.
  • the capacitance because it is necessary to minimize the cell area per bit in order to provide a large capacity memory.
  • the voltage Vs may be increased because to do so does not affect the chip area and, accordingly, such a memory may be realized merely by suitably designing the drive circuitry therefor.
  • FIG. 1 is a circuit diagram showing the arrangement of a conventional circuit for rewriting data into a memory cell.
  • a voltage difference read out of the memory cell is amplified by a sense amplifier and the voltage thus amplified is written back into the memory cell directly.
  • the associated charging circuit is not shown in FIG. 1.
  • reference character BL designates a bit line
  • MC a memory cell
  • DC a dummy cell
  • SA a sense amplifier circuit including a flip-flop
  • Q1, Q2, Q3 and Q4 MOSTs of the sense amplifier circuit C1 and C2 signal terminals for activating the sense amplifier circuit
  • Q5 and Q6 MOSTs for precharging the bit line
  • C3 and C3 signal terminals for precharging the bit line
  • C4 a signal line for connecting the bit line to the memory cell
  • Q7 a MOST in the memory cell Cs a storage capacitor in the memory cell
  • N1, N2, N3, N4 and N5 connection points designates a bit line
  • MC a memory cell
  • DC a dummy cell
  • SA a sense amplifier circuit including a flip-flop
  • Q1, Q2, Q3 and Q4 MOSTs of the sense amplifier circuit C1 and C2 signal terminals for activating the sense amplifier circuit
  • Q5 and Q6 MOSTs for precharging the bit line
  • the circuit in FIG. 1 operates as follows. After signals read out of the memory cell MC and the dummy cell DC are transmitted to the bit line BL, the signal terminal C1 is grounded to Vss to activate the sense amplifier circuit SA so that the small signal difference between the connection points N1 and N2 on the bit line is amplified.
  • the bit line BL is maintained precharged to V DD until a signal from the memory cell MC is transmitted thereto.
  • the MOSTs Q3 and Q4 are provided to prevent a decrease in the potential of the side whose potential is raised after amplification.
  • connection point N2 is at the high potential; however, it is lower by V th , corresponding to the threshold voltage of the MOST Q7, than V DD . Therefore, if the potential on the signal line C4 is V DD , the potential at the connection point N5 is V DD -V th and the maximum potential V DD -V th is rewritten into or stored by the capacitor Cs of the memory cell MC.
  • FIG. 2 A circuit for writing the potential V DD into the memory cell MC during the operation of the circuit has been proposed in the art, an example of which is shown in FIG. 2.
  • the circuit shown in FIG. 2 can be formed by connecting recharge circuits RC to both connection points of the bit line in the circuit shown in FIG. 1.
  • reference characters Q8 and Q9 designate MOSTs in the recharge circuit, C5 a signal terminal of the recharge circuit, CP1 a boostrap capacitor in the recharge circuit, and N6 a connection point in the recharge circuit.
  • the circuit of FIG. 2 operates the same as the circuit of FIG. 1 until the potential V DD -V th is rewritten.
  • the potential of the signal line C4 is raised to a level higher than V DD +V th and the level of a clock pulse applied to the signal terminal C5 is raised to "H" from "L” so that the potential of the connection point N6 is raised to a level higher than V DD +V th and the connection point N2 is recharged to V DD .
  • the signal line C4 is at a potential higher than V DD +V th
  • the potential V DD is written through the connection point N5 into the capacitor Cs of the memory cell MC.
  • the recharge circuit RC is recharged only when the connection point N2 is raised to the high potential.
  • the connection point N6 is also set to the zero potential and therefore the recharge circuit RC is not recharged. Accordingly, no power is unnecessarily consumed in the recharge circuit RC.
  • an object of the invention is to provide a circuit for increasing the storage charge of a dynamic MOSRAM.
  • a MOSRAM type semiconductor memory circuit including a plurality of bit lines, a potential decision circuit provided for each bit line for setting a potential on each bit line, and a boost circuit for increasing a potential on each bit line in accordance with the operation of the potential decision circuit.
  • One boost circuit may be provided for each bit line or a single boost circuit provided common to all or a plurality of the bit lines.
  • the potential decision circuit includes first, second, and third MOST transistors.
  • the first MOST transistor has a first signal electrode coupled to the bit line and a gate electrode coupled to a bias potential source while the gate electrode of the second MOST transistor is coupled to the second signal electrode of the first MOST transistor.
  • the term "signal electrode" refers to either of the drain or source of the MOST transistor.
  • the first signal electrode of the third MOST transistor is coupled to the first signal electrode of the first MOST transistor while its gate electrode is coupled to the second signal electrode of the second MOST transistor and through a capacitor to a second connection point.
  • the boost circuit includes a fourth MOST transistor having a first signal electrode coupled to the second signal electrode of the third MOST transistor in the potential decision circuit and a second signal electrode and gate electrode coupled to the bias voltage source.
  • a second capacitor is coupled between the first signal electrodes of the fourth MOST transistor and ground while a third capacitor is coupled between the first signal electrode of the fourth MOST transistor and a third connection point.
  • the potential decision circuit includes first and second MOST transistors both of which have a first signal electrode coupled to the corresponding bit line.
  • the gate electrode of the first MOST transistor is coupled to a bias voltage source while the gate electrode of the second MOST transistor is coupled to the second signal electrode of the first MOST transistor with the same point coupled through a first capacitor to a first connection point.
  • the boost circuit in this case includes a third MOST transistor having a first signal electrode coupled to the second signal electrode of the second MOST transistor and a second signal electrode and gate electrode coupled to the bias voltage source.
  • a second capacitor is coupled between the first signal electrode of the third MOST transistor and a second connection point.
  • FIG. 1 and FIG. 2 are circuit diagrams showing conventional MOSRAMs
  • FIGS. 3A and 3B are, respectively, a circuit diagram of a first embodiment of a semiconductor memory circuit according to the invention and a waveform diagram showing various signals in the circuit of FIG. 3A;
  • FIGS. 4A and 4B are a circuit diagram showing a second embodiment of a semiconductor memory circuit according to the invention and a waveform diagram showing various signals in the circuit of FIG. 4A.
  • FIGS. 3A and 3B and FIGS. 4A and 4B Examples of a semiconductor memory circuit constructed according to the present invention will be described with reference to FIGS. 3A and 3B and FIGS. 4A and 4B.
  • FIG. 3A shows a first preferred embodiment of a semiconductor memory circuit according to the invention. It should be noted that FIG. 3A shows only the essential components of the memory circuit of the invention and the sense amplifier circuit SA, the memory cell MC and the dummy cell DS are not shown in FIG. 3A.
  • FIG. 3B shows the waveforms of various signals in the circuit.
  • reference character LD designates a potential decision provided for each bit line BL; BO a boost circuit provided common to the bit lines BL; Q10, Q11 and Q12 MOSTs in the potential decision circuit; CP1 a boostrap capacitor in the potential decision circuit; C6 and C7 signal terminals of the circuit LD; N7 and N8 connection points in the circuit LD; Q13 a MOST in the boost circuit BO; CP2 a capacitor in the boost circuit BO; C8 a signal terminal of the boost circuit BO; and N9 a connection point in the boost circuit BO.
  • connection point N7 is also raised to the high potential.
  • the MOST Q10 operates as a self boostrap so that the connection point N7 is maintained at a sufficiently high voltage and, therefore, the voltage at the connection point N8 is made lower than that at the signal terminal C6 thus rendering the MOST Q10 non-conductive.
  • the connection point N9 of the boost circuit BO is precharged through the MOST Q13 to the potential V DD -V th .
  • the potential V B of the bit line is: ##EQU1##
  • the gate voltage (word line) of the pass transistor Q7 in the memory cell MC be raised to a level higher than V DD +2 V th .
  • FIG. 4A shows a second preferred embodiment of a semiconductor memory circuit according to the invention and FIG. 4B shows the waveforms of various signals in the circuit. Similar to FIG. 3A, FIG. 4A shows only the essential components of the circuit. Here, a potential decision circuit LD is provided for each bit line and a boost circuit BO is provided common to the bit lines BL.
  • connection point N10 is raised through the MOST Q14 to the high potential. Thereafter, when the signal terminal C9 is raised to "H” from “L,” the connection point N10 is raised to a sufficiently high potential as a result of which the MOST Q15 is rendered conductive.
  • the connection point N11 is precharged to V DD -V th . Therefore, when the signal terminal is raised to "H” from “L”, similarly, the connection point N2 of the bit line is raised to the high potential.
  • a potential decision circuit is provided for each bit line and a single boost circuit is provided common to the bit lines.
  • a separate boost circuit may be provided for each bit line.
  • N-channel type MOSTs and P-channel type MOSTs can be used as a MOST in the above-described embodiments.
  • the gates of the MOSTs Q 13 and Q 16 are coupled to the V DD in the above described embodiment, modifications are possible without departing from the essential scope of the invention by controlling the gate potential with a clock signal so that the MOSTs Q 13 and Q 16 are rendered non-conductive when the potential decision circuit LD and the boost circuit BO are activated.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
US06/202,822 1979-10-31 1980-10-31 Semiconductor memory circuit Expired - Lifetime US4404661A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP54-141783 1979-10-31
JP14178379A JPS5665396A (en) 1979-10-31 1979-10-31 Semiconductor memory circuit

Publications (1)

Publication Number Publication Date
US4404661A true US4404661A (en) 1983-09-13

Family

ID=15300056

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/202,822 Expired - Lifetime US4404661A (en) 1979-10-31 1980-10-31 Semiconductor memory circuit

Country Status (2)

Country Link
US (1) US4404661A (enrdf_load_stackoverflow)
JP (1) JPS5665396A (enrdf_load_stackoverflow)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503522A (en) * 1981-03-17 1985-03-05 Hitachi, Ltd. Dynamic type semiconductor monolithic memory
US4636981A (en) * 1982-07-19 1987-01-13 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device having a voltage push-up circuit
US4638463A (en) * 1985-01-24 1987-01-20 International Business Machines Corporation Fast writing circuit for a soft error protected storage cell
US5023465A (en) * 1990-03-26 1991-06-11 Micron Technology, Inc. High efficiency charge pump circuit
US5038325A (en) * 1990-03-26 1991-08-06 Micron Technology Inc. High efficiency charge pump circuit
US5185721A (en) * 1988-10-31 1993-02-09 Texas Instruments Incorporated Charge-retaining signal boosting circuit and method
EP1780727A1 (en) * 2005-10-26 2007-05-02 Infineon Technologies AG Memory device with improved writing capabilities
US20150131364A1 (en) * 2013-11-12 2015-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Negative bitline boost scheme for sram write-assist
US20160267952A1 (en) * 2012-03-15 2016-09-15 Intel Corporation Negative bitline write assist circuit and method for operating the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59210593A (ja) * 1984-04-20 1984-11-29 Hitachi Ltd 信号電圧昇圧回路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4061999A (en) * 1975-12-29 1977-12-06 Mostek Corporation Dynamic random access memory system
US4291393A (en) * 1980-02-11 1981-09-22 Mostek Corporation Active refresh circuit for dynamic MOS circuits
US4327426A (en) * 1980-02-11 1982-04-27 Texas Instruments, Incorporated Column decoder discharge for semiconductor memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4061999A (en) * 1975-12-29 1977-12-06 Mostek Corporation Dynamic random access memory system
US4291393A (en) * 1980-02-11 1981-09-22 Mostek Corporation Active refresh circuit for dynamic MOS circuits
US4327426A (en) * 1980-02-11 1982-04-27 Texas Instruments, Incorporated Column decoder discharge for semiconductor memory

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
J. M. Lee, "A 80ns 5V-Only Dynamic RAM," 1979 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 142, 143. *
S. S. Sheffield, "A 5V-Only 2Kx8 Dynamic RAM," 1979 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 144, 145. *

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503522A (en) * 1981-03-17 1985-03-05 Hitachi, Ltd. Dynamic type semiconductor monolithic memory
US4636981A (en) * 1982-07-19 1987-01-13 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device having a voltage push-up circuit
EP0100908A3 (en) * 1982-07-19 1987-08-19 Kabushiki Kaisha Toshiba Semiconductor memory device having a plurality of charge-storage type memory cells
US4638463A (en) * 1985-01-24 1987-01-20 International Business Machines Corporation Fast writing circuit for a soft error protected storage cell
US5185721A (en) * 1988-10-31 1993-02-09 Texas Instruments Incorporated Charge-retaining signal boosting circuit and method
US5023465A (en) * 1990-03-26 1991-06-11 Micron Technology, Inc. High efficiency charge pump circuit
US5038325A (en) * 1990-03-26 1991-08-06 Micron Technology Inc. High efficiency charge pump circuit
US20070109878A1 (en) * 2005-10-26 2007-05-17 Vincent Gouin Memory device with improved writing capabilities
EP1780727A1 (en) * 2005-10-26 2007-05-02 Infineon Technologies AG Memory device with improved writing capabilities
KR100880069B1 (ko) * 2005-10-26 2009-01-23 인피니언 테크놀로지스 아게 메모리 장치 및 메모리 소자에 기록하는 방법
US7486540B2 (en) 2005-10-26 2009-02-03 Infineon Technologies Ag Memory device with improved writing capabilities
US20160267952A1 (en) * 2012-03-15 2016-09-15 Intel Corporation Negative bitline write assist circuit and method for operating the same
US9818460B2 (en) * 2012-03-15 2017-11-14 Intel Corporation Negative bitline write assist circuit and method for operating the same
US10818326B2 (en) 2012-03-15 2020-10-27 Intel Corporation Negative bitline write assist circuit and method for operating the same
US10902893B2 (en) 2012-03-15 2021-01-26 Intel Corporation Negative bitline write assist circuit and method for operating the same
US20150131364A1 (en) * 2013-11-12 2015-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Negative bitline boost scheme for sram write-assist
US9070432B2 (en) * 2013-11-12 2015-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Negative bitline boost scheme for SRAM write-assist
US9437281B2 (en) 2013-11-12 2016-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Negative bitline boost scheme for SRAM write-assist

Also Published As

Publication number Publication date
JPS6226117B2 (enrdf_load_stackoverflow) 1987-06-06
JPS5665396A (en) 1981-06-03

Similar Documents

Publication Publication Date Title
US4081701A (en) High speed sense amplifier for MOS random access memory
US5619162A (en) Dram using word line potential circuit control
US4351034A (en) Folded bit line-shared sense amplifiers
US4417329A (en) Active pull-up circuit
US4622655A (en) Semiconductor memory
US5323345A (en) Semiconductor memory device having read/write circuitry
US4794571A (en) Dynamic read-write random access memory
US4404661A (en) Semiconductor memory circuit
KR0140175B1 (ko) 반도체 메모리 장치의 센스앰프 회로
US20060256630A1 (en) Apparatus and method to reduce undesirable effects caused by a fault in a memory device
US4578781A (en) MIS transistor circuit
US6452833B2 (en) Semiconductor memory device
US6115284A (en) Memory device with faster write operation
KR910004733B1 (ko) 데이타 버스 리셋트 회로를 지닌 반도체 기억장치
US5835403A (en) Multiplication of storage capacitance in memory cells by using the Miller effect
US5579276A (en) Internal voltage boosting circuit in a semiconductor memory device
US5703819A (en) Sense amplifier driving circuit
KR0154755B1 (ko) 가변플레이트전압 발생회로를 구비하는 반도체 메모리장치
USRE32682E (en) Folded bit line-shared sense amplifiers
JP2679033B2 (ja) 半導体記憶装置
JPH0217872B2 (enrdf_load_stackoverflow)
EP0318094B1 (en) Integrated memory circuit with on-chip supply voltage control
US5768200A (en) Charging a sense amplifier
JP3020944B2 (ja) 半導体集積回路
KR0170694B1 (ko) 반도체 메모리 장치의 센스 증폭기 풀다운 구동회로

Legal Events

Date Code Title Description
AS Assignment

Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, NO. 2-3, MARUNO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:NAGAYAMA, YASUJI;TANIGUCHI, MAKOTO;REEL/FRAME:004141/0479

Effective date: 19801024

STCF Information on status: patent grant

Free format text: PATENTED CASE