US4394586A - Dynamic divider circuit - Google Patents

Dynamic divider circuit Download PDF

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Publication number
US4394586A
US4394586A US05/408,148 US40814873A US4394586A US 4394586 A US4394586 A US 4394586A US 40814873 A US40814873 A US 40814873A US 4394586 A US4394586 A US 4394586A
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Prior art keywords
inverter
transistors
channel
output
transistor
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Expired - Lifetime
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US05/408,148
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English (en)
Inventor
Shinji Morozumi
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SUWA A Co OF JAPAN KK
Suwa Seikosha KK
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Suwa Seikosha KK
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Assigned to KABUSHIKI KAISHA SUWA, A COMPANY OF JAPAN reassignment KABUSHIKI KAISHA SUWA, A COMPANY OF JAPAN ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: MOROZUMI, SHINJI
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/42—Out-of-phase gating or clocking signals applied to counter stages

Definitions

  • This invention relates generally to an improved dynamic divider circuit for use in an electronic timepiece and especially to a simplified dynamic divider circuit comprised of insulated gate field effect transistors.
  • Dynamic divider circuits comprised of insulated gate field effect transistors consume significent amounts of power when operated at high frequencies. Because the size of a battery is limited in an electronic timepiece, and further because it is necessary to operate electronic timepieces at high frequencies, such divider circuits have been less than completely satisfactory.
  • a dynamic divider circuit comprised of inverters formed from insulated gate field effect transistors.
  • the dynamic divider circuit includes an intermediate inverter and a master and slave multiple inverters, both multiple inverters including a complementary connection of two series-connected P-channel and two series N-channel field effect transistors.
  • the P-channel and N-channel transistors are coupled in such a manner that the output terminal of the master inverter is coupled through the intermediate inverter to the input terminal of the slave inverter, and the output terminal of the slave inverter is directly coupled to the input gate of said master inverter.
  • a first clock pulse is supplied to the gate terminal of a further, series-connected N-channel transistor of said master inverter and to the gate terminal of a further series-connected P-channel transistor of said slave inverter.
  • a second clock pulse which is the complement of said first clock pulse, is supplied to the gate terminal of a further series-connected P-channel transistor of said first inverter and the gate terminal of a further, series-connected N-channel transistor of said second inverter, the binary division of such divider circuit utilizing the parasitic capacitance generated by the field effect transistors of said first and second inverter circuits as a memory element.
  • FIG. 1 is a circuit diagram of a prior art binary divider circuit
  • FIG. 2 is a timing chart of the input and output voltages of the circuit of FIG. 1;
  • FIG. 3 is a circuit diagram of a dynamic divider circuit according to the instant invention.
  • FIG. 4 is a timing chart of the input and output voltages of the circuit of FIG. 3;
  • FIG. 5 is an equivalent circuit diagram of a prior art transmission-type binary divider circuit in operation.
  • FIG. 6 is an equivalent circuit diagram of the dynamic divider circuit constructed in accordance with the instant invention.
  • FIG. 1 wherein a conventional master-slave flip-flop binary divider circuit is depicted.
  • the divider circuit is comprised of 20 insulating gate field effect transistors and 10 N-channel insulated gate field effect transistors.
  • the binary divider circuit effects a division of the input clock pulse in such a manner when clock pulses ⁇ and ⁇ are applied to the multi-inverter to determine a first and second condition. In a first condition a slave inverter S is written while the master inverters M and M hold their state, and in the second condition the master inverter M is written while slave inverters S and S are held constant.
  • the current consumption is determined by the amount of current flowing when both channels of the inverters are simultaneously in an ON condition when the inverter stages produce a change of state.
  • each insulated gate field effect transistor has approximately the same physical construction and hence the same operating characteristics, when such elements are assembled in an integrated circuit chip, current consumption is determined by the number of such elements in the chip and the rate of changing state, more accurately characterized as the frequency at which the circuit is operated.
  • the small-sized batteries are not capable of sustaining the power consumption over a long period of time due to their limited capacity.
  • First multiple inverter 1 hereinafter referred to as the master inverter includes a complementary connection of serially connected P-channel transistors P 1 and P 2 to serially coupled N-channel transistors N 1 and N 2 .
  • second multiple inverter 3 hereinafter referred to as the slave inverter, is comprised of a complementary connection of serially connected P-channel transistors P 4 and P 5 to serially connected N-channel transistors N 4 and N 5 .
  • Intermediate inverter 2 is comprised of a complementary connection of P-channel transistor P 3 to N-channel transistor N 3 .
  • the master inverter is coupled at output M, defined by the node formed by the connection of the drain terminals of transistors P 2 and N 2 to the input of the intermediate inverter 2, which input is defined by the node formed by the coupling of the gate terminals of transistors P 3 and N 3 .
  • the output M of the master inverter is defined by the node formed by the connection of the drain terminals of transistors P 3 and N 3 and is coupled to the input of the slave inverter defined by the node formed by the connection of the gate terminals of transistors P 5 and N 5 .
  • the output of the slave inverter defined by the node formed by the connection of the drain terminals of transistors P 5 and N 5 is directly coupled to a node of said master inverter defined by the connection of the gate terminals of transistors P 2 and N 2 .
  • the master and slave inverters are also directly coupled to each other by the coupling of the source terminals of P 1 to P 4 and N 1 to N 4 .
  • clock pulse ⁇ is coupled to the master inverter at the gate terminal of transistor N 1 and to the slave inverter at the gate terminal of transistor P 4 and clock pulse ⁇ , is coupled to the master inverter through the gate terminal of transistor P 1 and is coupled to the slave inverter through the gate terminal of transistor N 4 .
  • Capacitors C m and C s represent the equivalent capacitance caused by the operation of the divider circuit and the characteristics of the transistor elements. Such capacitance, known as parasitic capacitance, is present at the junctions formed in the insulated gate field effect devices and by the metallic wiring of such field effect transistors. It is a feature of this invention that such equivalent capacitances found at the output terminals of the master inverter and the slave inverter are utilized as memory elements for holding the states of the inverter circuits.
  • the contents memorized by such capacitive elements are changed according to the actual time constant created by the leakage currents, the effective capacitance at the drain terminals, and the rate at which charging and discharging is effected.
  • the time constant is equal to or greater than the value required to sustain the state of the inverter until the next change in state dictated by the clock pulse is applied to the divider circuit, the decaying effect of the time constant has no effect on the operation of the divider circuit.
  • the time constant effected thereby for such field effect transistors is several seconds allowing the use of such divider circuits for dividing signals of up to and including 1 Hz.
  • FIG. 5 wherein an equivalent circuit of the transmission-type dynamic divider circuit of the prior art is depicted.
  • a voltage is held, or memorized, by the parasitic capacitance C 1 on the drain side of a master inverter M and a transmission transistor Tr 1 when transistor Tr 1 is OFF.
  • a voltage is memorized by the parasitic capacitance C 2 which is effected at the source side of transistor Tr 1 and the drain side of transistor Tr 2 when transistor Tr 1 is turned ON.
  • transistor Tr 2 is turned ON, to thereby transmit the contents held thereby to slave inverter S, the voltage applied thereto is divided in the ratio of to C 1 :C 2 , and the operating point of the inverter can be knocked out of position.

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  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Electric Clocks (AREA)
  • Electromechanical Clocks (AREA)
  • Manipulation Of Pulses (AREA)
US05/408,148 1972-10-19 1973-10-19 Dynamic divider circuit Expired - Lifetime US4394586A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP47104830A JPS4963371A (enrdf_load_stackoverflow) 1972-10-19 1972-10-19
JP47/104830 1972-10-19

Publications (1)

Publication Number Publication Date
US4394586A true US4394586A (en) 1983-07-19

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US05/408,148 Expired - Lifetime US4394586A (en) 1972-10-19 1973-10-19 Dynamic divider circuit

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US (1) US4394586A (enrdf_load_stackoverflow)
JP (1) JPS4963371A (enrdf_load_stackoverflow)
CH (1) CH607882B (enrdf_load_stackoverflow)
GB (1) GB1451784A (enrdf_load_stackoverflow)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4507574A (en) * 1981-12-14 1985-03-26 Fujitsu Limited Constant operation speed logic circuit
US4645947A (en) * 1985-12-17 1987-02-24 Intel Corporation Clock driver circuit
US4716308A (en) * 1982-07-30 1987-12-29 Tokyo Shibaura Denki Kabushiki Kaisha MOS pull-up or pull-down logic circuit having equalized discharge time delays and layout avoiding crossovers
US4970407A (en) * 1988-06-09 1990-11-13 National Semiconductor Corporation Asynchronously loadable D-type flip-flop
US4988896A (en) * 1989-07-31 1991-01-29 International Business Machines Corporation High speed CMOS latch without pass-gates
US5453707A (en) * 1993-01-13 1995-09-26 Nec Corporation Polyphase clock generation circuit
US5463340A (en) * 1992-06-23 1995-10-31 Mitsubishi Denki Kabushiki Kaisha Phase clocked latch having both parallel and shunt connected switches for transmission gates
US20060087350A1 (en) * 2003-03-18 2006-04-27 David Ruffieux Frequency divider with variable division rate

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4181862A (en) * 1976-09-27 1980-01-01 Rca Corporation High speed resettable dynamic counter
US4539495A (en) * 1984-05-24 1985-09-03 General Electric Company Voltage comparator
US4695740A (en) * 1984-09-26 1987-09-22 Xilinx, Inc. Bidirectional buffer amplifier

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3431433A (en) * 1964-05-29 1969-03-04 Robert George Ball Digital storage devices using field effect transistor bistable circuits
US3483400A (en) * 1966-06-15 1969-12-09 Sharp Kk Flip-flop circuit
US3560998A (en) * 1968-10-16 1971-02-02 Hamilton Watch Co Electronically controlled timepiece using low power mos transistor circuitry
US3710271A (en) * 1971-10-12 1973-01-09 United Aircraft Corp Fet driver for capacitive loads
US3716723A (en) * 1971-06-30 1973-02-13 Rca Corp Data translating circuit
US3737673A (en) * 1970-04-27 1973-06-05 Tokyo Shibaura Electric Co Logic circuit using complementary type insulated gate field effect transistors
US3745371A (en) * 1970-08-11 1973-07-10 Tokyo Shibaura Electric Co Shift register using insulated gate field effect transistors
US3749937A (en) * 1970-11-27 1973-07-31 Smiths Industries Ltd Electrical dividing circuits
US3757510A (en) * 1972-07-03 1973-09-11 Hughes Aircraft Co High frequency electronic watch with low power dissipation
US3823551A (en) * 1971-05-03 1974-07-16 Riehl Electronics Corp Solid state electronic timepiece
US3829713A (en) * 1973-02-12 1974-08-13 Intersil Inc Cmos digital division network
US3833822A (en) * 1972-12-21 1974-09-03 Bell Telephone Labor Inc Ripple free counter

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5511022B2 (enrdf_load_stackoverflow) * 1972-02-25 1980-03-21

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3431433A (en) * 1964-05-29 1969-03-04 Robert George Ball Digital storage devices using field effect transistor bistable circuits
US3483400A (en) * 1966-06-15 1969-12-09 Sharp Kk Flip-flop circuit
US3560998A (en) * 1968-10-16 1971-02-02 Hamilton Watch Co Electronically controlled timepiece using low power mos transistor circuitry
US3737673A (en) * 1970-04-27 1973-06-05 Tokyo Shibaura Electric Co Logic circuit using complementary type insulated gate field effect transistors
US3745371A (en) * 1970-08-11 1973-07-10 Tokyo Shibaura Electric Co Shift register using insulated gate field effect transistors
US3749937A (en) * 1970-11-27 1973-07-31 Smiths Industries Ltd Electrical dividing circuits
US3823551A (en) * 1971-05-03 1974-07-16 Riehl Electronics Corp Solid state electronic timepiece
US3716723A (en) * 1971-06-30 1973-02-13 Rca Corp Data translating circuit
US3710271A (en) * 1971-10-12 1973-01-09 United Aircraft Corp Fet driver for capacitive loads
US3757510A (en) * 1972-07-03 1973-09-11 Hughes Aircraft Co High frequency electronic watch with low power dissipation
US3833822A (en) * 1972-12-21 1974-09-03 Bell Telephone Labor Inc Ripple free counter
US3829713A (en) * 1973-02-12 1974-08-13 Intersil Inc Cmos digital division network

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Suzuki et al., "Clocked MOS Calculator Circuitry"; IEEE Internat'l Solid-State Circuits Conference; Session VI: LSI Components, 2/14/1973. *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4507574A (en) * 1981-12-14 1985-03-26 Fujitsu Limited Constant operation speed logic circuit
US4716308A (en) * 1982-07-30 1987-12-29 Tokyo Shibaura Denki Kabushiki Kaisha MOS pull-up or pull-down logic circuit having equalized discharge time delays and layout avoiding crossovers
US4645947A (en) * 1985-12-17 1987-02-24 Intel Corporation Clock driver circuit
US4970407A (en) * 1988-06-09 1990-11-13 National Semiconductor Corporation Asynchronously loadable D-type flip-flop
US4988896A (en) * 1989-07-31 1991-01-29 International Business Machines Corporation High speed CMOS latch without pass-gates
US5463340A (en) * 1992-06-23 1995-10-31 Mitsubishi Denki Kabushiki Kaisha Phase clocked latch having both parallel and shunt connected switches for transmission gates
US5453707A (en) * 1993-01-13 1995-09-26 Nec Corporation Polyphase clock generation circuit
US20060087350A1 (en) * 2003-03-18 2006-04-27 David Ruffieux Frequency divider with variable division rate

Also Published As

Publication number Publication date
JPS4963371A (enrdf_load_stackoverflow) 1974-06-19
CH607882GA3 (enrdf_load_stackoverflow) 1978-12-15
GB1451784A (en) 1976-10-06
CH607882B (fr)

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Owner name: KABUSHIKI KAISHA SUWA SEIKOSHA 3-4, 4-CHOME GINZA

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Effective date: 19820219

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