US4302628A - Analog signal encrypting and decrypting system - Google Patents

Analog signal encrypting and decrypting system Download PDF

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US4302628A
US4302628A US06/139,675 US13967580A US4302628A US 4302628 A US4302628 A US 4302628A US 13967580 A US13967580 A US 13967580A US 4302628 A US4302628 A US 4302628A
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signal
encrypting
analog
decrypting
pulses
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Charles Akrich
Jean C. Lemaire
Michel J. Maillard
Michel Ruiz
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Telediffusion de France ets Public de Diffusion
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Telediffusion de France ets Public de Diffusion
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04K—SECRET COMMUNICATION; JAMMING OF COMMUNICATION
    • H04K1/00—Secret communication
    • H04K1/06—Secret communication by transmitting the information or elements thereof at unnatural speeds or in jumbled order or backwards

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  • This invention relates to an encrypting and decrypting system for encrypting an incoming analog signal into an encrypted analog signal and for decrypting the encrypted analog signal into an decrypted analog signal which is analogous to the incoming signal.
  • the invention concerns the encrypting and decrypting of an audiofrequency signal of a radiophonic program or, more generally, to the encoding and decoding, or scrambling and unscrambling, or enciphering and deciphering of an analog signal, thereby obtaining a non-intelligible signal to be transmitted from a station transmitter to listener receivers.
  • the listeners are selected from encrypting the audiofrequency signal broadcast by the radio-communications or television transmitter in accordance with a "key" or encrypting code and by thereafter decrypting the audiofrequency signal picked up by the listener's receiver in accordance with the "key” or decrypting code corresponding to the inverse operation of the encrypting code operation.
  • These encrypting and decrypting operations are made applicable to analog signals such as speech and musical signals.
  • Known encrypting and decrypting systems in the prior art implement an analog sampling of the incoming analog signal at periodic time intervals at predetermined instants. Thereafter there takes place a scrambling of the analog samples.
  • Known methods of arithmetic encoding can be applied, the simplest ones consisting of an encoding in accordance with a pseudo-random sequence or with permutation sequences of two or several analog samples. An example is found in U.S. Pat. No. 4,100,374.
  • the U.S. Pat. No. 4,100,374 discloses an encrypting and decrypting system based on an analog sample permutation method.
  • the delay means which is included in the encrypter (or the decrypter) of this patent comprises two analog shift registers each having N stages. The inputs of the first stages of the two shift registers receive N samples of the incoming signal to be encrypted (or the encrypted signal). Each of the two shift registers time delays of N incoming signal samples (or N encrypted signal samples) during every other period NT W of the encrypting signal (or the decrypting signal).
  • the 2 N stage outputs of the two shift registers are connected to the output of the encrypter (or the decrypter) through an analog switch which is analogous to a parallel-to-series converter.
  • the analog switch is controlled by the encrypting signal (or the decrypting signal) so as to select the N outputs of one of shift registers then the N outputs of the other shift register during two consecutive periods NT W .
  • the N outputs of a shift register are selected according to a predetermined encrypting sequence so as to transpose and read the previously written samples according to a various arrangement. This is equivalent to a permutation of samples which is synchronized at a reading frequency equal to the writing frequency 1/T W .
  • the encrypting signal controls also the addressing of the N outputs of a shift register according to a predetermined permutation and at a constant reading frequency.
  • the decrypting signal is composed of a series of stage addressing words in according with the complementary permutation to the encrypting permutation. Consequently, the encrypting signal producing means and the decrypting signal producing means are both necessary.
  • the principal object of this invention is to provide an encrypting and decrypting system overcoming the disadvantages of the prior art systems hereinabove described.
  • Another object of this invention is to provide an encrypting and decrypting system in which the initial order of the incoming signal samples is maintained in the encrypted signal.
  • a further object of this invention is to provide an encrypting and decrypting system in which the incoming signal samples undergo at least a time compression during each period of the key code signal and in which the encrypting and decrypting signals are identical.
  • the time distribution of the samples in the encrypted signal fluctuates in a similar way without modifying the initial order of the samples.
  • an encrypting and decrypting system comprises:
  • first analog means receiving said incoming signal for time delaying 2 N analog samples of said incoming signal:
  • first writing means for producing first clock pulses at a predetermined period F W which control the writing and sampling operations of N successive samples of said incoming signal in a first time delay means during a first period NT W ;
  • first reading means for producing an encrypting signal having N pulses per period equal to NT W , said N encrypting signal pulses controlling the in series reading operation of said N successive samples of said incoming signal in said first time delay means during a second period NT W following said first period thereby obtaining said analog encrypted signal and said N encrypting signal pulses being time distributed according to a predetermined regular distribution in each of said periods NT W thereby obtaining N encrypted signal samples having undergone at least a time compression and eventually a time expansion with regard to the regular time distribution of said N incoming signal delayed samples;
  • second analog means receiving said encrypted signal for time delaying 2 N analog samples of said encrypted signal
  • the N decrypting signal pulses controlling the writing operation of the N successive samples of said encrypted signal in said second time delaying means during said first period NT W and said N decrypting signal pulses being distributed in time according to said predetermined distribution
  • second reading means for producing second clock pulses at said predetermined period T W which are synchronized with said first clock pulses and control the reading operation of the N successive encrypted signal samples in said second time delaying means during said period NT W thereby obtaining said analog decrypted signal.
  • the delay or time compression and expansion function of the initial or encrypted signal is performed by means of two delay lines comprising analog shift registers such as charge transfer circuits (C.T.D.). Each delay line comprises N analog stages.
  • the inputs of the first stages of delay lines in the encrypter (or the decrypter) are connected to receive the initial (or encrypted) analog signal.
  • the outputs of the last stages of the two delays lines are connected alternately to the output of the encrypter (or the decrypter) during half the encrypting (or decrypting) signal period via analog switching means.
  • Each encrypting (or decrypting) signal period corresponds to the time taken to fill all the stages of a delay line during which the initial (or the decrypted) signal samples are written in the encrypter (or are read in the encrypter).
  • one of the two delay lines is write controlled in the encrypter at a predetermined clock period (or in the decrypter at N writing instants of the decrypting signal according to the predetermined time distribution), whereas the other delay line is read controlled in the encrypter at the N reading instants of the encrypting signal according to the predetermined time distribution (or in the decrypter at the predetermined clock period).
  • the preceding read or write controls are inverted relative to the two delay lines during the following period of the encrypting (or decrypting) signal.
  • the input of the first stage of a first delay line receives the initial (or encrypted) analog signal.
  • the N stage outputs of the first delay line are connected in parallel to the N stage inputs of a second delay line, respectively.
  • the output of the second delay line is connected to the encrypter (or decrypter) output.
  • the first delay line is write controlled in the encrypter at the writing clock period (or in the decrypter at the N writing instants of the decrypting signal according to the predetermined time distribution)
  • the second delay line is read controlled in the encrypter at N reading instants of the encrypting signal according to the predetermined time distribution (or in the decrypter at the reading and sampling clock period).
  • the first and second delay lines are simultaneously read and write controlled at the end of each encrypting (or decrypting) signal period for transferring in parallel the N analog samples from the first to the second delay line.
  • the means for producing in synchronism the encrypting and decrypting code signals which are identical may be based on the pulse modulation of a predetermined signal. This modulation may be of the position or frequency type and the frequency of the modulation signal can also be programmable.
  • the encrypting and decrypting signal producing means may be a programmable frequency multiplier or divider. The selection of these various means and the programmable frequency makes it possible to generate a plurality of key codes, each of which being assigned to a specialized program.
  • the pulse modulation produces a number of pulses greater than the number of the analog samples during one period of the encrypting or decrypting signal
  • a counter counts the N first pulses of the code signal at the start of each period and locks the transmission of the following pulses until the start of the following period. Consequently, N samples of the encrypted signal are always time compressed during a period NT W of the encrypting signal. Nevertheless, the time between two successive encrypted signal samples included in a same period NT W may be more than the sampling period T W .
  • the encrypted signal samples in a period NT W may be followed by a silent interval equal to at least one or several periods T W .
  • the encrypted signal is appropriate to be conveyed by a communication medium between the encrypter and the decrypter which may be by cable, Hertzian channel, optical fibres, direct broadcast, such as via satellite, or by any other type of broadcasting means and that the decrypted signal always presents correct listening quality characteristics.
  • FIG. 1 is a block diagram of an encrypting and decrypting system including a delay line arrangement according to the first embodiment
  • FIG. 2 shows waveforms useful in illustrating the reading and writing operations of the delay lines
  • FIG. 3 is a block diagram of the addressing circuit according to the first embodiment
  • FIG. 4 is a block diagram of the encrypting signal generator or the decrypting signal generator
  • FIG. 5 is a block diagram of the synchronization circuit of the encrypter.
  • FIG. 6 is a block diagram of the analog delay circuit and the addressing circuit included in the encrypter or the decrypter according to the second embodiment.
  • FIG. 1 shows an encrypting and decrypting system embodying the invention. It comprises an encrypter 1 for emission and a decrypter 2 for reception. The output of the encrypter 1 is linked to the input of the decrypter 2 by a communication medium 3.
  • the input of the encrypter 1 receives the initial analog signal to be encrypted.
  • This is a speech and/or musical signal which is transmitted by a microphone or the audio tape of a magnetic tape recorder included in a radio or television station studio recording equipment for example.
  • a low pass filter 10 filters the initial analog signal in a low frequency band which stretches, for example, up to 8 KHz.
  • the filtered signal may be transmitted to a compression and/or pre-emphasis circuit 11 whose output is connected to the input 120 of an analog delay circuit 12.
  • the circuit 11 contributes towards improving the performance of the encrypter by masking any possible defects due to sampling and switching inherent in encrypting.
  • the signal/noise ratio is also increased as a result of the circuit 11.
  • the analog delay circuit 12 is made up of two analog delay lines 121 1 , 121 2 which are connected in parallel, and an analog switching circuit 122.
  • the common inputs 120 of the analog delay lines 121 1 , 121 2 are connected to the output of the compression and/or pre-emphasis circuit 11.
  • the outputs of the last stages of the lines 121 1 , 121 2 are connected to the two analog inputs of analog AND gates 123 1 and 123 2 , respectively which are included in the switching circuit 122.
  • This duration NT W is equal to the period of the encrypting and decrypting signals.
  • the outputs of the analog AND gates 123 1 and 123 2 are connected to the inputs of an analog OR gate 124 whose output 125 transmits the encrypted signal.
  • each analog delay line is a charge transfer integrated circuit or is composed of several charge transfer integrated circuits which are connected in series.
  • each analog delay line 121 1 121 2 includes P analog shift registers. Each register is made up of 512 series stages of B.B.D. type.
  • the complementary reading (or writing) control signals S 1 and S 2 transmitted from the addressing circuit 13 to the AND gates 123 2 and 123 1 have a period equal to 2 NT W .
  • the pulse signals transmitted on the output wires 126 1 and 126 2 from the addressing circuit control the step-by-step advance of a sample in the delay lines in reading phase and also have a period equal to 2 NT W .
  • One of these, such as that on the wire 126 1 is composed during a first half-period NT W by N pulses having the constant period T W which control the sampling and writing in the delay line 121 1 .
  • the reading pulses have a time distribution which is determined by the encrypting key and different from the regular time distribution of the above writing pulses.
  • the other pulse signal on the wire 126 2 is composed during the above first half-period NT W by N pulses according to said determined time distribution which control the reading of N samples in delay line 121 2 , and is composed during the second above half-period NT W by N pulses which are equidistributed at constant period T W and which control the writing-in of N samples in the delay line 121 2 .
  • the second delay line 121 2 is in reading operation for which the samples of the incoming initial signal, previously delayed, advance at successive instants t 1 to t N which are distributed as per the encrypting code signal during the same half-period NT W .
  • the previous reading and writing operations are inverted: the first delay line 121 1 is in reading operation and the second delay line 121 2 is in writing operation.
  • the successive reading instants t 1 to t N are formed as per an encrypting code or key which is selected by an encrypting signal generator 15 and which may be dependent on the clock signal at frequency F W on the wire 140.
  • the generator 15 transmits the reading pulses at the instants t 1 to t N during each time NT W to addressing circuit 13, via a bus 150.
  • a synchronization circuit 16 receives from two output wires 160 of the addressing circuit 13 the complementary reading and writing control signals S 1 and S 2 for producing synchronizing pulses at the frequency NT W which allow appropriate restoration of the initial signal based on the encrypted signal in the decrypter 2.
  • the synchronizing pulses are transmitted along a wire 161 towards the encrypting generator 15 and are appropriately modulated by a high-frequency signal transmitted, via the output wire 141 of the time base 14, to give a synchronizing signal at the output 162 of the circuit 16.
  • the encrypted signal and the synchronizing signal are mixed in a mixing unit 17 after respectively passing through a low pass filter 171 which is analogous to the filter 10, and a pass band filter 172 whose pass band is centered on the synchronization modulation frequency.
  • the composite signal delivered from the output of the mixing unit 17 may be transmitted and appropriately shaped in a transmitter 18 which depends upon the transmission mode of the communication medium 3 between the encrypter 1 and the decrypter 2.
  • the composite signal may pass through an appropriate demodulating receiver 28 and is then filtered.
  • a low pass filter 271 which is analogous to the filter 10
  • a band pass filter 272 which is analogous to the filter 172, restore the encrypted signal and the synchronizing signal, respectively.
  • the decrypter 2 performs the inverse function of the encrypter 1 and comprises, in a similar way to the encrypter circuits 12 to 16, circuits 22 to 26.
  • An analog delay circuit 22 receives the encrypted signal transmitted from the low pass filter 271 via its input 220 and restores via its output 225 the decrypted signal which is analogous to that applied to the input 120 of the analog delay circuit 12 of the encrypter 1.
  • a write and read addressing circuit 23 controls analog delay lines 221 1 and 221 2 of the circuit 22 in writing and reading operating alternately, via wires 226 1 and 226 2 .
  • the addressing circuit 23 also controls the opening of analog AND gates 223 1 and 223 2 of an analog switching circuit 222 which is included in the circuit 22, alternately during reading, via wires 227 1 and 227 2 .
  • the circuit 222 is identical to the circuit 122 and also comprises an analog OR gate 224 whose output 225 delivers the decrypted signal.
  • a time base 24 transmits a clock signal at constant frequency F W along a wire 240 to the addressing circuit 23 and a decrypting signal generator 25.
  • the generator 25 previously records the decrypting code or key which is, in accordance with the invention, identical to the selected encrypting code, and transmits the writing pulses at variable non-equidistributed instants t 1 to t N to the addressing circuit 23 along a wire 250.
  • the synchronizing pulses are detected in a synchronization circuit 26 making use of the synchronizing signal which is delivered from the filter 272, and are transmitted along a wire 261 to the generator 25 and the time base 24.
  • the synchronizing signal also makes it possible to control the advance of the listener's recording equipment, such as the recording tape of a magnetophone for example (not shown).
  • the analog decrypted signal is transmitted from the output 225 of the analog switching circuit 222 to a low pass filter 20 which is analogous to the filter 10, and may be transmitted to an expansion and/or de-emphasis circuit 21 which is complementary to the circuit 11.
  • the output of circuit 21 is common with that of the decrypter 2 and restores a decrypted analog signal which is analogous to the initial analog signal received at the input of the encrypter 1.
  • the generator 15 produces N reading pulses at instants t 1 to t N such that, in general, t i+1 -t i ⁇ T W , with 1 ⁇ i>N.
  • the time distribution of N reading pulses over a reading interval NT W is achieved by means of a so-called pulse modulation circuit 151.
  • the circuit 151 can include one or several "pulse modulators” or “variable-step reading clocks” 1510 which are programmable or not and each of which generates a sequence of reading pulses during NT W .
  • a modulator 1510 is a programmable frequency multiplier or divider which multiplies or divides a reference frequency.
  • the frequency F W transmitted by the time base 14 along the wire 140 may be multiplied by a predetermined integer Q.
  • a modulator 1510 is a "pulse modulator" of a signal which is periodic or otherwise, and which has preferably a simple envelope. This signal may be a periodic sawtooth signal as illustrated on line b of FIG. 2 or a multi-level periodic signal as illustrated on line c of FIG. 2.
  • Such signal is produced by a signal generator included in the modulator 1510.
  • the modulation circuit included in the modulator 1510 operates according to one of the known pulse modulations. If the modulation is a position modulation, i.e. if the time positions of the pulses are proportional to the modulating signal amplitude, the reading pulses are distributed as illustrated by lines b 1 and c 1 of FIG. 2. When the modulation is a frequency modulation, pulse sequences at predetermined frequencies correspond to the predetermined amplitude values of the modulating signal, as illustrated on lines b 2 and c 2 of FIG. 2. It will be noted that other "pulse modulators" 1510 can easily be made by those skilled in the art and can result in the combination of the above embodiments.
  • saw-tooth or multilevel type modulators can have the frequency of the modulation signal which is programmable.
  • the encrypter and, above all, the decrypter will comprise one or several "pulse modulators" which make it possible for each to generate an encrypted signal which is practically incomprehensible.
  • the read samples in the encrypter 1 undergo always a time compression since all the written samples in the analog delay lines 121 1 , 121 2 are read and transmitted.
  • the time interval (t N -t 1 ) is always less than the period NT W of the encrypting signal.
  • a time expansion may be present between two samples i, j of a period NT W ; that is equivalent to t j -t i >(j-i)T W .
  • Such a time expansion is illustrated in FIG. 2 at line c 1 between the instants t 2 and t 1 or t 4 and t 3 and at line c 2 between the instants t 2 and t 1 , although (t N -t 1 ) ⁇ NT W is always satisfied.
  • the pulse modulators and/or the frequencies of the modulating signal of the latter are addressed by a read-only memory of encrypting key codes 152 which is included in the generator 15 shown in FIG. 4.
  • Each cell 1520 of the memory 152 contains the address of a modulator 1510 and, if necessary, of one of the modulation frequencies.
  • the code memory 152 is addressed, in a known manner, in reading by an alphanumeric keyboard, via a key code address register 154 which contains the address of a cell 1520 of the memory 152 in correspondence with each number identifying an encrypting key which is transmitted from the key board 153.
  • the addressed pulse modulator 1510 is energized and produces the reading pulses at the predetermined instants t 1 to t N at the output 1511 of the pulse modulation circuit 151, via an OR gate 1512.
  • the encrypting signal generator 15 comprises a counter 155 having maximum capacity N whose counting input is connected to the output 1511 of the pulse modulation circuit 151, and an AND gate 156 whose inputs are connected to the output 1550 of the counter 155 and to the terminal 1511.
  • the counter 155 is reset to zero (RS) each time it receives a synchronizing pulse which is transmitted along the wire 161 from the synchronization circuit 16 and which defines a transition between the reading and writing operatings of duration NT W relative to each delay line.
  • the counter 155 delivers a signal at its output 1550 which closes the AND gate 156 until the next zero setting, such that only N reading pulses pass through the AND gate 156 during a time NT W .
  • the N transmitted reading pulses are illustrated by full lines on lines b 1 , b 2 , c 1 and c 2 of FIG. 2, whereas the following pulses which are inhibited, are illustrated by dotted lines.
  • the synchronizing pulse on the wire 161 is also transmitted to the selected modulator 1510 for it to be triggered at the start of each reading and writing operation of duration NT W so as to produce a modulation signal having a period NT W , as illustrated in lines b and c of FIG. 2.
  • the addressing circuit 13 is shown in FIG. 3. It produces the signals S 1 which simultaneously controls the writing operation setting of the delay line 121 1 and the reading operation setting of the other delay line 121 2 .
  • the addressing circuit 13 also produces the signal S 2 which controls the reading operation setting of the delay line 121 1 and the writing operation setting of the other delay line 121 2 .
  • the signal S 1 is applied at the output of a divide-by-N frequency divider 130 whose input receives the writing pulses at the constant frequency F W which are provided from the time base 14 on the wire 140.
  • the addressing circuit 13 also comprises two identical logic circuits which enable the alternate transmission of writing pulses and the reading pulses to the delay lines 121 1 , 121 2 .
  • Each logic circuit is made up of a first AND gate 132 1 , 132 2 which controls the writing and sampling in the delay line 121 1 , 121 2 , a second AND gate 133 1 , 133 2 which controls the reading in the delay line 121 1 , 121 2 and an OR gate 134 1 , 134 2 whose inputs are connected to the outputs of first and second AND gates 132 1 , 133 1 or 132 1 , 133 2 and whose output controls the advance of initial signal samples in the delay line 121 1 , 121 2 , via the wire 126 1 , 126 2 .
  • Two common inputs of the AND gates 132 1 and 133 2 receive the signal S 1 which also controls the opening of the analog AND gate 123 2 of switching circuit 122, via the wire 127 2 .
  • Two common inputs of the AND gates 133 1 and 132 2 receive the signal S 2 which also controls the opening of the analog AND gate 123 1 of the switching circuit 122, via the wire 127 1 .
  • the other inputs of the writing and sampling gates 132 1 and 132 2 receive, via the time base outputting wire 140, the writing pulses at the constant frequency F W and alternately control the sampling and writing of the initial signal in the delay lines 121 1 and 121 2 during successive periods NT W .
  • reading gates 133 1 and 133 2 receive, via the output wire 150 from the generator 15, the reading pulses and alternately control the reading and transmission of the encrypted signal from the delay lines 121 1 and 121 2 during successive periods NT W , via the analog AND gates 123 1 and 123 2 which are opened alternately and in correspondance with the opening of the AND gates 133 1 and 133 2 .
  • the synchronization circuit 16 is schematically illustrated in FIG. 5. It comprises a dual monostable flip-flop 163 which transmits a synchronizing pulse on the wire 161 at each rise front of the complementary signals S 1 and S 2 , i.e. at the beginning of each time interval NT W .
  • the inputs of the flip-flop 163 are connected to the outputs of the divider 130 and the inverter 131, via the two-wire bus 160.
  • the synchronization circuit 16 also comprises a frequency modulator 164 whose input is connected to the output of the flip-flop 163 and whose output applies the synchronizing signal along the wire 162 to the input of the band pass filter 172.
  • the modulator 164 modulates in phase the synchronizing pulse at a subcarrier frequency of 15 kHz which is transmitted from the output wire 141 of the time base 14. As already stated, this modulated synchronizing pulse is mixed with the encrypted signal in the mixing unit 17 of the encrypter 1 and is detected in the synchronization circuit 26 of the decrypter 2.
  • the addressing circuits 13, 23 and the generators 15, 25 in the encrypter 1 and decrypter 2 have identical block-diagrams, respectively. Reference numbers are indicated in brackets and correspond to the blocks and wires of the decrypter 2 shown in FIG. 1.
  • the synchronization circuit 26 of the decrypter 2 is essentially made up of a frequency demodulator whose output 261 applies the synchronizing pulses to the zero-resetting input RS of counter 155 and possibly to the triggering input of certain pulse modulators 1510 of the decrypting signal generator 25.
  • the synchronizing pulses are also received into the time base 24 for phasing the phase locking loop it contains at the frequency F W .
  • the listener When the listener wishes to record the specialized program corresponding to the selected encrypted code, he types the same identification key on the key board 153 of the decrypter 2 which causes through the key code address register 154 and the code memory 152 of the decrypter, the addressing and energizing of the corresponding modulator 1510 and, if the latter is frequency programmable, the selection of a frequency for the modulating signal.
  • the selected modulator 1510 in the decrypter is identical to that selected in the encrypter. Indeed, the decrypter must recognize the samples which are transmitted by the encrypter at successive reading instants t 1 to t N after each beginning of a writing interval NT W .
  • the writings of the encrypted signal in the analog delay lines 221 1 and 221 2 during successive time intervals NT W must be identical upon reading the samples in the delay lines 121 1 and 121 2 of the encrypter.
  • the reading in the decrypter 2 is identical to the writing in the encrypter 1 and is rhythmed at the constant frequency F W . As shown in FIG.
  • the writing AND gates 132 1 and 132 2 receive the time non-equidistributed writing pulses in accordance with the encrypting code which are delivered from the output 250 of the decrypting signal operator 25, whereas the reading AND gates 133 1 and 133 2 receive the reading pulses at the constant frequency F W which are delivered from the output 240 of the time base 24.
  • the synchronization circuit 26 synchronizes, via the wire 261, the emissions of the writing pulses which are transmitted from the selected pulse modulator 1510 and the reading pulses which are transmitted from the time base 24, the chopping of the encrypted signal and the restoration of the initial signal in the decrypter 2 are controlled in synchronism with the sampling and the reading of the initial signal in the encrypter 1.
  • two analog delay lines 121' 1 , 121' 2 , of the delay circuit 12 in the encrypter 1 and two analog delay lines 222' 1 , 222' 2 of the delay circuit 12' in the decrypter 1 are intended for the writing and reading operations, respectively.
  • reference numbers are in brackets and represent the components which are included in the delay circuit 22' and the writing and reading addressing circuit 23' of the decrypter 2 and are identical to the circuits 12' and 13' of the encrypter 1. Reference will be made hereinafter to the encrypter, unless otherwise stated.
  • the input 120' of the first stage of the first delay line 121' 1 receives continuously the initial analog signal.
  • the delay line 121' 1 samples the initial signal into N series analog samples at constant writing frequency F W during each period NT W .
  • the writing pulses at frequency F W are transmitted along wire 126' 1 from the addressing circuit 13'.
  • the end of each period NT W is detected by the dual monostable flip-flop 163 which opens N analog AND gates 122' 1 to 122' N (respectively 222' 1 to 222' N for the decrypter) at the time of the transmission of a synchronizing pulse along the wire 161 (respectively 261 for the decrypter).
  • the other inputs of the gates 122' 1 to 122' N are connected to the outputs of N stage pairs of the first delay line 121' 1 and simultaneously transmit in parallel N stored samples to the inputs of N stage pairs of the second delay line 121' 2 .
  • the delay line 121' 2 operates in reading-out at instants t 1 to t N according to the predetermined time distribution of the selected code delivered from the addressing circuit 13', via the wire 126' 2 .
  • the output 125' of the last stage of the delay line 121' 2 produces the encrypted signal as for the first embodiment.
  • the addressing circuit 13' of the encrypter is simpler. It comprises no more than the frequency divider 130 which delivers the signal S 1 , the inverter 131 which delivers the signal S 2 , and two AND gates such as 132 1 and 133 1 . All these components are inter-connected in a similar way to that depicted in FIG. 3.
  • the writing gate 132 1 of the circuit 13', 23' transmits along the wire 126' 1 the writing pulses at the constant frequency F W which are supplied from the time base 14, via the wire 140, in the encrypter, respectively along the wire 226' 1 at the instants t 1 to t N determined by the writing pulses which are supplied from the decrypting signal generator 25, via the wire 250, in the decrypter.
  • the reading gate 133 1 of the circuit 13', 23' transmits the reading pulses along the wire 126' 2 at the instants t 1 to t N determined by the reading pulses which are supplied from the encrypting signal generator 15, via the wire 150, in the decrypter, respectively along the wire 226' 2 at the constant frequency F W which are supplied from the time base 24, via the wire 240, in the decrypter.
  • the recurrent code sequences of duration NT W are chosen, on the one hand, to obtain a totally unintelligible encrypted signal and, on the other, to restore the initial analog signal from the encrypted signal with a high signal/noise ratio, so that the listening quality of the decrypted signal is close to that of the intitial signal.
  • the choice between the different arrangements of the two delay lines and also between the types of pulse modulator depends on utilization restrictions such as manufacturing cost of the decrypter which, unlike the encrypter, is produced in large quantities.
  • At least one of the generators 15 and 25, preferably the decrypting signal generator 25, may comprise only one pulse modulator or more simply one frequency multiplier or divider which is synchronized with a clock frequency.
  • the latter circuit generates just one time distribution of instants t 1 to t N during a period NT W and may an integrated circuit which is plugged into the decrypter rack. It is turned on by a straight-forward initialization push-button replacing the keyboard.
  • this selection of the listeners can be made using decrypters including analog delay lines which comprise a predetermined number of stages lower than that of the encrypter delay lines which provides for a predetermined program to be received by decrypters having delay lines whose stage number is equal to that really utilized in the delay lines of the encrypter. Indeed, it is easy to select first stages of a delay line in the encrypter.
  • the transmission of the compound signal resulting from mixing the encrypted signal and the synchronizing signal in the encrypter can be performed, as already stated, by cable, Hertzian channel, optical fibres or an analogous communication medium.
  • the initial analog signal can come within the radio-communication, television, or telephone field.
  • the synchronizing signal may be mixed with the encrypted signal in this channel, or may modulate an audio-frequency subcarrier wave, which is mixed with the encrypted signal, wherein the subcarrier is modulated in phase for example by the synchronizing signal.
  • the composite encrypted and synchronizing signal can be conveyed in a conventional television channel, or be time-division multiplexed with the video signal for example by appropriately inserting it into the line synchronizing and blanking signals and/or in the frame synchronizing and blanking signals.
  • any combination of encrypting means in accordance with the invention and known decrypting means thereby obtaining a encrypted signal from time compression and expansion of a constant-period sampled analog signal or a sampled analog signal whose samples have been periodically mixed beforehand by permutation or in keeping with any suitable sequence also lies within the scope of the invention herein.
  • the inverse rearrangement carried out by the corresponding decrypter also comes within the scope of this invention.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
US06/139,675 1979-04-20 1980-04-14 Analog signal encrypting and decrypting system Expired - Lifetime US4302628A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR7910092A FR2454664A1 (fr) 1979-04-20 1979-04-20 Systeme de cryptage et de decryptage d'un signal analogique par compressions et expansions temporelles
FR7910092 1979-04-20

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US4302628A true US4302628A (en) 1981-11-24

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US06/139,675 Expired - Lifetime US4302628A (en) 1979-04-20 1980-04-14 Analog signal encrypting and decrypting system

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US (1) US4302628A (ref)
EP (1) EP0018869B1 (ref)
CA (1) CA1142637A (ref)
DE (1) DE3063260D1 (ref)
FR (1) FR2454664A1 (ref)

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US9853809B2 (en) 2015-03-31 2017-12-26 Board Of Regents Of The University Of Texas System Method and apparatus for hybrid encryption
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GB2151886A (en) * 1983-12-21 1985-07-24 British Broadcasting Corp Conditional-access broadcast transmission
GB2180728A (en) * 1985-09-17 1987-04-01 Gec Avionics Data encryption using shift registers
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US4434323A (en) 1981-06-29 1984-02-28 Motorola, Inc. Scrambler key code synchronizer
US8683539B1 (en) 1981-11-03 2014-03-25 Personalized Media Communications, Llc Signal processing apparatus and methods
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EP0117276A3 (en) * 1982-09-20 1986-05-21 Sanyo Electric Co., Ltd. Privacy communication method and privacy communication apparatus employing the same
US4742546A (en) * 1982-09-20 1988-05-03 Sanyo Electric Co Privacy communication method and privacy communication apparatus employing the same
US4683586A (en) * 1983-01-11 1987-07-28 Sony Corporation Scrambling system for an audio frequency signal
US4893339A (en) * 1986-09-03 1990-01-09 Motorola, Inc. Secure communication system
US9853809B2 (en) 2015-03-31 2017-12-26 Board Of Regents Of The University Of Texas System Method and apparatus for hybrid encryption
WO2024206857A1 (en) * 2023-03-31 2024-10-03 Signal Advance, Inc. Signal protection and retrieval by non-linear analog modulation
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US20250047485A1 (en) * 2023-03-31 2025-02-06 Signal Advance, Inc. Signal protection and retrieval by non-linear analog modulation

Also Published As

Publication number Publication date
EP0018869B1 (fr) 1983-05-18
EP0018869A1 (fr) 1980-11-12
CA1142637A (en) 1983-03-08
FR2454664B1 (ref) 1983-12-30
FR2454664A1 (fr) 1980-11-14
DE3063260D1 (en) 1983-07-07

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