GB2180728A - Data encryption using shift registers - Google Patents

Abstract

The invention provides a data encryption/decryption method (and the equipment therefor), in which plain form data is transferred sequentially through two sets of analogue shift registers at a number of different transfer rates such that for each register data fed in at one rate is then fed out at another. The data transferred between the two sets of registers is encrypted, but when fed out of the last register is decrypted, and in plain form. Each set of shift registers may contain two registers each as shown or, in another arrangement only one register is used for encryption and two registers for decryption, these two being filled alternatively from the encryption register. <IMAGE>

Description

1 GB 2 180 728 A 1 SPECIFI1CATION Data encryption b 10 This invention

concerns data encryption, a nd relates in pa rticu lar to the encryption of a nalog ue data, such as 5 speech, for tra nsmissio n over a narrow ba nd chan nel, and to the received sig na I's su bsequent de-cryption to reconstitute the data in its original form.

Sig nals transm itted over a ny so rt of " broadcasC system, best exempi if ied by radio, can i n general be picked u p by a nyone with the correct sort of receiver properly tu ned in. For many reasons, however, it may be desirable for the sig nals to be intel 1 igea ble on ly to the intended, and thus authorised, recipient, and to ensure 10 this it is common to "scramble", or encrypt, the data before transmission, so that only the recipient who can approprately "unscramble", or decrypt, the signal will be able to see the data in its original plain form.

Such a data tranception system is said to be a "secure" system, in that the data involved is secure against eavesdroppers. As m ight be expected, however, there a re different levels of security - some encryption methods are so simple (and cheap) they can be recognised, and the appropriate de-cryption technique worked out and applied within a few minutes, while others are so complex (and expensive) they maytake hou rs, days or even years to crack. Natu ral ly, the type of encryption employed is chosen to f it the secu rity level required.

In one known method of data encryption there aretwo sequential registers andtwo different transfer rates, andforeach register data that has been clocked in (filling upthe register) atone rate is clocked out attheother. 20 Thusjoreach registerthe data clocked out represents a frequency-shifted version of the datathatwas clocked in. It is this frequency shifting that encrypts -and subsequently decrypts -the data. Foreach register the shifting may be up ordown and that in fact itwill alternatefrom onetothe other. The reason forthis alternation is simple: data clocked in at a first rate is clocked outata second, butas it is so clocked out naturallya further batch of data is being clocked in, atthis second rate, to be clocked out in itsturn atthefirst 25 rate, and so on. Accordingly, a batch of data clocked in atthe lower rate and out atthe higher rate isup-shifted, whilethe next batch, necessarily clocked in atthe higherand out atthe lower rate, is down-shifted (andthe next batch is up-shifted,the nextdown, and so on).

The invention relatesto the encryption, and subsequent decryption, of data, specifically narrowband ana logue data typified byspeech (the human voice contains almost all its output in the band from 300 Hzto 3000Hz); purely for convenience, hereinafterthe invention is described mainly interms of its applicationto the encryption/decryption of speech.

Typical users desirous of having theirspeech communications rendered unintelligible to unintended and unauthorised recipients are the Police, who prefer criminals notto be able to gain useful information by listening in to police radio broadcasts, the Military,who are againstthe Enemy making use of overhead battlefield (and other) conversations, and Businessmen,who do notwish theircommercial rivalsto be ableto make sense out of anytelephone conversations to which they may become a party. For a Police car radio network, wherethe information transmitted is usuallyfor immediate action, only a low level of security is required, butfor a Business discussion of long term plans a much higher level is desirable.

Many different data encryption systems have been proposed; all have advantages and disadvantages. The 40 present invention suggests a novel system that is at heart extremely simple (and thus cheap) but can be elaborated to almost any degree of complexity. It can, therefore, be of value whetherthe situation requires a low or a high level of security.

In one aspect, therefore, the invention provides a data encryption/decryption method, in which: first and second registers are associated with encryption and a third and fourth with decryption, plain-form data is transferred sequential ly th rough the fouranalogue shift registers such that data element is clocked atclif ferent clocking rates and for each register data which is fed in at one clocking rate isthen fed out atanother; and data isfed into a third register atthe same clocking rate as itwas fed out of the second register, and isfed out of the third register atthe same clocking rate as itwas fed into the second register; and data isfed intothe fourth register atthe same clocking rate as itwas out of thefirst registerand is fed out of thefourth registerat 50 the same clocking rate as itwas fed into thefirst register, whereby, byvirtue of the resulting frequency shifting, the data transferred between the second and third registers is encrypted, butwhen fed out of the fourth register is decrypted, and in plain form.

In another aspectthe invention provides a data encryption/decryption method in which a first register is associated with encryption and a second and a third register are associated with decryption; plain form data 55 isfed into thefirst register at a series of clock rates and then fed out of thefirst register at a different series of clock rates and fed into the second register atthe same series of clock rates itwasfed out of the first registerat, when the second register isfull the data being fed out of the first register is fed into thethird register atthe same series of clock rates itwas clocked out of the first registerat and the data in the second register isfed out atthe same series of clock rates itwas fed into the first register at, when thethird register isfull the data being 60 fed out of the first register is fed into the second register atthe same series of clock rates ltwas fed out ofthe first register at and the data in the third register is fed out atthe same series of clock rates itwasfed intothe first register at, and this cycle of use of the second and third registers is repeated; the series of clock rates supplied tothe registers being such that; data transferred between the first register and the second andthird registers is encrypted, and the data output of the second and third registers is plain form and the the duration 65 2 GB 2 180 728 A 2 of time taken to fill or empty each of the registers with data is a constant.

In a further aspect the invention provides analogue data encryption/decryption equipment which includes: four shift registers arranged in a sequence; tranception means whereby the output of the second register can be supplied to the input of the third register, input means for feeding plain-form data to the first register; output means for feeding plain-form data from the fourth register; clock pulse means for each register, for giving a sequence of different clock sign a] s to the registers to contro I the transfer of their contents therethrough; and synchronisation means enabling the clock pulse means for each register to be synchronised one with the other, such that, when plain form data is transferred sequential lythroug h the four registers at four different clocking rates (a) for each register, data which is fed in atone clocking rate is then fed out at another, and (b) data is fed into the third register at the same clocking rate as it was fed put of the second register, and is fed out of the third register at the same clocking rate as it was fed into the second register, (c) data is fed into thefourth register at the same clock rate as it was fed out of the first register, and is fed out of the fourth register at the same cl ockin grate as it was fed l nto the first register.

In another aspect the invention provides data encryption/decryption equipment which includes: a first shift register associated with encryption and a second and a third shift register associated with decryption; tranc- is eption means whereby the output of the first register can be supplied to the inputs of the second orthird registers; input means for feeding plain form data to the first register; output means for feeding plain form data from the fourth register; clock pulse means for each register for giving a sequence of different clock signa Is to the registers to control the transfer of their contents therethrou g h; synchronisation means enabl ing the clock pulse means for each register to be synchronised one with another; and switching means enabling sections of the output of the first register to be supplied alternately to the inputs of the second and third registers, each section being one register full of data, arranged such that, when plain form data is transferred throu g h the register at a p l ura l ity of different clocking rates, for each register data which is fed in at one clocking rate is fed out at another, data is fed into the second register at the same rate it was fed out of the first, data is fed out of the second register at the same rate it was fed into the first, data is fed into the third register at the same rate it was fed into the first and data is fed out of the third register at the same rate it was fed out of the first.

The invention relates to the encryption, and subsequent decryption, of data. As mentioned hereinbefore, this data could be of any type, butthe invention is primarily concerned with analogue speech signals -that is, voice signals that occupy the relatively narrow (-3KHz wide) band from about 3001-1z to about 3000Hz. Specif- 30 ically, the invention is intended for use in a voice communications system wherein speech data is encrypted at one location, transferred to another location, and there decrypted. The communications system may be of any sort; two examples are telephone (wired) networks and radio (wireless) networks. In the formerthere are atthe two locations the telephones that are connected to each other possibly by an Exchange of some sort, while in the latterthere are atthe two locations thetransmitter and the receiver, the one launching into the aetheC information-carrying electromagnetic radiation to be received by the other.

The data to be transferred by the inventive method - the input data - is described asplain-form data, to distinguish itfrom the encrypteddata actual ly transferred between the two locations. It may, in fact, be "plain-form", and not encoded in any way exceptthat necessary for its actual transferral through the system (as, say, voice sound is converted into electrical pulses, and then electromagnetic pulses, and back again to 40 sound, fortransception in any radio system), and indeed it is thoughtto be the main use of the inventive method that uncoded voice sound can be simply and cheaply scrambled into intel ligeable form, and then unscrambled. It is not impossible, however, that the input data could already be encoded/encrypted, in which case "plain-form" has merely the aforementioned distinguishing meaning.

In one method of the invention the data is transferred sequential ly th rough four analogue shift registers - it 45 is inputto one,transferred ("clocked") through that one and out, and then it is inp.utto a second, transferred through this other and out. The encrypted data is then transmitted to a second location where it is inputto a third shift register, clocked through it, then input to a fourth register, transferred through it and out. The data is inputto the first register in plain form, is outputfrom the second register - and inputto the third register - in encrypted form (as will be explained below, the encrypted form is merely a frequency-shifted version of the 50 plain form), and is output by the fou rth register in plain form. In any system using the inventive method to secure data being transferred between locations, the first and second registers are at the transmitting loca tion, the third and fourth registers are atthe receiving location, and the data transferred between thetwo locations is encrypted.

This aspect of the invention requires at leastfour analogue shift registers (though in more complexforms, it 55 may use more - six say, pre-encrypting the data and then post decrypting itwith an additional fifth and sixth registers.) An analogue shift register is an electronic device having a sequence of elements, or cells, in each of which may be stored an electrical charge the value of which may be any within some continuous range. This sequence of cells is aregister, and because the contents can represent - be analogous to - any value (within some range) it is an analogue register. The contents of each cell may be shifted clocked -to the sequentially 60 next cell underthe control of transfer clock pulses suitably delivered to the device (so the register is a shift register), and by doing this an electrical signal/value presented to thefirst cell may be transferred into that cell, then shifted to the next cell and f ina 1 ly transferred to, and out of, the last cell. The process isvery like pouring waterfrom one bucketto the next in a chain of buckets (indeed, one form of such a device is actually known as a "bucket brigade device"); water -the signal As poured into the first bucket, and thenceto 65 1 4 4 3 0 10 or GB 2 180 728 A 3 the next, and the next.... and so on till it reaches, and is poured out of, the last bucket. Itwill be obviousthat any signal fed into the cell sequence is delayed - over a signal bypassing the sequence - bythe time ittakesto transfer itthrough and out of the cells. Clearly, this transfertime is a function of the clockfrequency. The lower thefrequency - the lowerthe rate of clock pulses driving the transferfrom one cell to the next -the longer itall 5 takes.

If an analogue signal is presented to - and inputto - an analogue shift register, and if, as it is input, so it is transferred on and through the register at a rate at or greaterthan the minimum required bythe Nyquist rule (sampling rates must be at leasttwice the frequency of the input signal's highest frequency component),then the output signal will consist of a series of pulses, or bits, thatfaithfully define - and in effect are -the original input signal togetherwith a clockfrequency component added thereto. Byfiltering off this clockcomponent 10 there may be reconstituted the original input signal, albeit in delayed form.

Most analogue shift registers are those electronic devices known as Charge Coupled Devices (CCDs). They may contain any number of cells - usually 2n, where n is from 5to 10 (Le, from 32 to 1024 cells) -through 512 cell CCDs are common. They may also be clocked at any rate (though the timetaken to transfer chargefrom one cell to the next isfinite, and thus limits the clocking rate), buttypical rates are 1 to 1 OOKHz.

When using analogue shift registers it is normal to clocksignals through them ata constant rate. However, in some applications - conversions between different television frame systems, for example - it isthe practice to clockthe signal in at one rate (until the register isfull), and then outat a different rate. This hasthe effectof comprising orstretching the signal. A compressed signal -the same number of pulses, or bits, but in a shorter time - has a higher frequency than the original inputform; it is a frequency-upshifted version of the original 20 signal. Conversely, a stretched signal -the same number of bits, but in a longertime - has a lowerfrequency than the original input; it is a frequency-downshifted version of the original. In either case the frequency is shifted by a factor of the ratio of the inputto the outputclock rates. Thus, if a signalatfrequency Fin is clocked in at rate Rin and clocked out at rate R.utthen thefrequency Fout of the outputsignal is given by Fout = Fn. Rout Rin As an example, if a MHz sinewave input signal (Fin=3KHz) is clocked in at 1 OKHz (Rin= 1 OKHz) and outat20KHz (Rot=20KHz) then the output signal frequency F.ut is 3-2-1= 6KHz. Conversely, if the 3KHz signal was clocked in 30 at20KHz and out at 1 OKHzthen the output signal frequency is 3-1-0 = 1. 5KHz.

In the basic method of the invention there are four sequential registers, and four different transfer rates, and for each register data that has been clocked in (filling up the register) at one rate is clocked out atanother.

From theforegoing explanation, itwill therefore be appreciated thatforeach registerthe data clocked out represents a frequency-shifted version of the data thatwas clocked in. It is thisfrequency shifting thatencrypts - and subsequently decrypts -the data; it is discussed in more detail hereinafter, but here it should be noted thatforeach registerthe shifting may be up or down, and that in fact itwill alternatefrom onetothe other. The reason for this alternation is simple: data clocked in at a first rate is clocked out at the second, but as it is so clocked out naturally a further batch of data is being clocked in, at this second rate, to be clocked out in its turn at the first rate, and soon. Accordingly, a batch of data clocked in at the lower rate and out at the higher 40 rate is up-shifted, while the next batch, necessarily clocked in at the higher and out at the lower rate, is down-shifted (and the next batch is upshifted, the next down, and soon).

For each register the alternation of the two rates itse If occurs at a rate that is a function of the length ofthe registers (the number of cel Is) and the two clocking rates, for it occurs as each register is filled up with the data clocked in. Though not al I analogue shift registers behave in quite the same way, it is for convenience sufficient to assume that a device clocked at, say, 1OKHz is having its cel I contents transferred at a rate of 10,000 per second, so that a 1024-cell device would be filled (or emptied) in about a tenth (=1024/10,000) of a second. A similar device clocked at 20KHzwould thus be filled (or emptied) in about a twentieth (=1024120,000) of a second. Using such a device, and 10 and 20KHz clock rates, alternation wou I cl occur at 0.1, 0.05,0.1,0.05 (and soon) second interva Is. The effect on a voice signal is very confusing! The four clock rates maybe different by a I most any factor, as low as 1. 1 times still provides an acceptable scrambling effect.

It is afeature ofthe method ofthe invention thatthe datathatisfed intothethird registerissofed in atthe same rate as itwasfed outofthesecond register,the data that isfed outofthethird register is so fed out atthe same rate itwasfed in tothe second register,the data that isfed into thefourth registeris sofed in atthesame 55 rate as itwasfed outofthefirst registerandthe datathat isfed out ofthefourth registeris sofed outatthe same rate as itwasfed intothefirst register. This, coupled with the alternation ofthe ratesfor each register, results in the data passing between thetwo pairs of registers being in encryptedform (either up ordown shifted) while the data that exitsthefourth register is in decrypted, plain form (for its encrypted version has been either down- or up-shifted, as appropriate). - The data passing between thetwo sets of registers is frequency shifted, and thus encrypted. Moreover,the shift alternates between being an up shift and being a down shift and the amount of up or down shifting is not constant. It is perhaps this constant variation indirection and amount offrequency shifting that rendersthe method ofthe invention particularly effective, especially with voice data, where the main energy lies atthe lower end ofthe frequency range (300to 1 000Hz, say) butthe intelligence - the "formants" -lies mostly atthe 65 4 GB 2 180 728 A 4 upper end of the range (2000 to 3000 Hz, say). By shifting the formants back and forth between, say, twice and a half the usual frequencies, and by doing this fairly frequently, so that the ear/brain has no time to adapt, so the voice signal is rendered quite unintel I igeable.

As stated herein before data is fed into each register atone rate and out of that register at a noth er rate, data is fed sequential ly through the four registers, data is fed out of the fourth register at the same rate at which it is fed into the first and data is fed out of the third register at the same rate at which it was fed into the second. The rate at which data is fed inlout is determined by clock pulses fed to the relevant register to cause the trans ferral of its contents, cell-by-cel I, into, through and out of the device, and thus is dependent on a clock pulse rate. In order to ensure that these events are in time one with another it is necessary, when putting the invention into operation, to employ some method of synchronising the application to each register of the four different sets of clock pulses. In principle, this merely requires that, sent either alongside or buried within the coded data, there is a mastertiming signal that enables the fourth register's timing system to synchronise with the first register's system and the third register's timing system to synchronise with the second register's system. For example, commonly each pair of two registers wil I have its own, nomina I ly independent, clock - the heart of the timing system -that is crystal-control led to keep very accurate time. This clock signal can then 15 be used to derive the needed different timing signals for each register of the pair. However, even clocks such as these tend to "drift" off frequency as time goes on, so there will be some way of re-triggering the clock cycle from an external source. If, then, each pair of registers'timing system is associated with trigger pulse transmitting/receiving means, such that the encrypting registers'timing system can send to the decrypting registers'ti m ing system a suitable trigger pulse at some appropriate time, then that pulse can be caused to 20 retrigger the decrypting registers'clock, and place the two clocks in perfect synchronisation. in one more particular example of synchronisation, discussed further hereinafter with reference to the accompanying Drawings, it is arranged firstly that an unencrypted tone be transmitted from the encrypting to the decrypting register, either continuously (and subsequently filtered out at the receiver) or at the start of transmission (the tone may conveniently be derived by shaping an output from the encrypt clock generating system and modi fying to a -possibly -triangular form, or that suitable for the characteristics of the system). For systems with large group delays the tone frequency should be fairly low, typically 200Hz. At the receiving end the encrypted output from the receiving apparatus perse is fed to atone decoderlphase locked loop. This generates two oupts. The first output is a dcpulsewhich is produced on lockup, and is fed to the decryption clock generator as a coarse reset. The clock reference generator is crystal controlled, and its output is fed via agate to the decryption clock generator. Atone generator derived from an output of the clock generator is set to the same as that at the transmitter. This is compared with the second output of the phase locked tone decoded by means of a phase sensitive rectifier. If the two signa Is are not in phase, the rectifier output wil I consist of a series of pulses whose width wi I I be a function of relative phase. The output is shaped and connected to the gate at the input of the clock generator. As a resu It a phase or pulses will be "blanked" at the clock generator 35 input. The tone at the receiver wi I I now slip until it is in phase with the incoming signal, when the phase sensitive detection output disappears. Providing the signals remain in phase, no further blanking occurs.

To allow for crystal oscillator drift, a dcsignal can be derived from the PSR to adjust the fundamental crystal frequency for ultra fine adjustment.

For more complex systems, the transmitted tone frequency can be varied to indicate "Time of day" atthe 40 transmitter.

This method provides a means of synchronisation which does not indicate encryption information.

In its most basicform the invention employs four analogue shift registers in sequence. This can resultin acceptable low level security, butfor higher levels the resulting encryption is inadequate.

One simple wayto raisethe security level is slowlyto modifythe four clock rates according to some preag- 45 reed code. Alternatively, the clock pulsetrains could themselves be modified - by leaving outthe occasional pulse, oreven inserting an additional pulse - again in a prearranged manner. Such changes would havethe effect of disrupting the operation of any unauthorised "automatic" decryption device not partytothe codes, so making more difficuitthe work of the eavesdropper.

A number of other possibilities exist. For example, if on a four-register system a fixed period forthe overall 50 system delay is adopted, for example 80 milliseconds, then each registerwould have a nominal delay of 20 milliseconds. However, in place of a fixed clock rateforeach period a pulse train could be provided pseudo randomlyvarying at a slow rate. Thetwo constraints are, firstly, thatthe maximum spacing between pulses should be lessthan-1-, where F is the upperfrequency response required, and secondly, thatthe numberof pulses within the period when all slots are filled must exceed the number of bits (cells) in the registertime. 55 Anotherway of improving the security of the encrypted data would be to changethe clocking rate,that is, change otherthan the alternation between two rates in the known system. However, such a change in clock ing rate will alter the time taken by data to pass through the system. As a result, data will be either overwritten - resulting in loss of data, or blank areas will appear in the signal.

This problem can be overcome by arranging the clock frequencies supplied to the encrypting registerso 60 thatthe time taken to clock in some set amount of data is a constant. We shall call this time period theframe time. The simplest such amountto choose is one encrypting registerfull of data. Thus the signal will ef fectively be processed as a string of sections of signal, each of these sections of signal being of theframe length T. Each section isfed into the encrypting registerat a series of different clock rates and then fed outof the register ata different series of clock rates. Each of the series of clock rates being chosen so that inframe 65 4 It 4_ GB 2 180 728 A 5 timeTthetotal numberof clock pulses supplied to the registeris equaltothe numberof cells intheregister.

Each ofthesesections of signal is encrypted bya numberof different frequency shifts because itis read into the registerata series of clock rates andthen read outofthe registerata differentseries of clockrates(the numberof different clock rates, the order of theclockrates andthe clockrates mayall bealtered). Becausethe 5 time taken for data representing each section of signal to pass through the register is a constant, problems of overwriting and blank areas in the signal are avoided.

For instance, if a 4096 cell line were used to encryptthe signal, a frame time of the signal 58.368 mseccould be chosen and oneframe length could befed into the register atfour different clock rates asfollows:- ClockRate No. of Bits Time Taken 10 1. 50KHz 1024 10.24 msec.

2. 41.66 KHz 1024 12.288 msec.

3. 35.71 KHz 1024 14.336 msec.

4. 23.81 KHz 1024 21.504 msec. 15 Total: 4096 58.368 msec.

In the next 58.368 msc. the data in the register isfed out asfollows:ClockRate No. of Bits Time Taken 1. 41.66 KHz 1024 12.228 msec.

2. 26.32 KHz 1024 19.456 msec.

3. 31.25 KHz 1024 16.384 msec. 25 4. 50 KHz 1024 10.24 msec.

Total: 4096 58.368 msec.

The signal section is thus encrypted because each 1024 bit section of it is read in and out of the registerat 30 different rates, but the time taken to read the signal section in is the same as the time taken to read the signal out. As the section is read out of the registerthe next signal section is read in and it is later read out at a third sequence of four clock rates.

The signal is decrypted by reading it into a decrypting register atthe same sequence of clock rates itwas read out of the encrypting register and then reading it out of a decrypting register at the same sequence of clock rates it was read into the encrypting register. Because this requires onesignal section to be read out of decryption at one rate and the next section to be rread into decryption simultaneously at another rate, itwill, in fact, be necessary to use two registers to decryptthe signal, the two decrypting registers decrypting alter nate signal sections.

Such a system is simplest, and provides the highest degree of encryption, when the encrypting and dec- 40 rypting registers are of equal size. ltwouid however, be possibleto use encrypting and decrypting registers of different sizes. If a system with differentsized encrypting and decrypting registers were used,the numberof clock pulses supplied in thefixed frame time must not be largerthan the capacity of the smallest register.

In orderto increase the security level of such a system the length of the encrypting and decrypting registers could be altered. This could not be done while a signal was being transmitted, because itwould cause loss of 45 data orthe introduction of blank sections into the output signal. However, this could be done in the course of a speech message by altering the register's lengths during pauses.

The signal to be encrypted could, of course, be pre-encoded or encrypted for additional security.

Alternatively, the analogue data - a speech signal, say - can be separated into two bands, lower and upper, and fed to two separate sets of registers operating independently. Atthe receiver high and low passfilters would separate the two bands before injecting them into two corresponding separate sets of registers. This method also hasthe advantage that in each pairof framesthe instantaneous time and frequency relationship of pitch and formant is completely distorted, and the clock change ratios can be reduced.

Yet another embodiment enables the speech time sequence to betransformed. If two sets of encrypting registers are connected in series and a signal applied for a time which would fill all the registers, thetwo sets 55 can then betransposed, and transmitted in reverse order. On reception in two sets of decrypting registers,the contents are again transposed before being clocked out. This method can be combined with any other; the number of registers employed determinesthe amount of transposition. Obviously, more registers increase s the overall delay. However, transposition would also reduce the relative clock change necessary, and the individual frames could be shorter.

Various embodiments of the invention are now described, though only byway of illustration, with refer ence to the accompanying Drawings, in which:

Figure 1 is a sequence representing an analogue shift registerthrough which a simple signal istransferred; Figure2is a sequence showing a register likethat of Figure 1 having a simple signal transferred through itat different rates; 6 GB 2 180 728 A 6 Figure 3 is a schematic circuit diagram fora simple form of apparatus applying one method of the invention; Figure 4 shows how data passes through the encryption/decryption system of the invention; Figure 5shows a schematic circuit fora synchronising system for use with the invention, and Figure 6 is a schematic circuit diagram for apparatus applying another method of the invention.

The sequence of Figure l represents the transferral of a simple sine wave signal F through a 16-cel l analog ueshift register (101).Attime To all the cells 1-16 are empty; the signal F is presented to the register's input end (the left as viewed) on the input line (102). If the register receives a clock pulse (at time T1, not shown in the Figure) then a charge representing the va l ue of the signal atthat time is placed in the first cell. A second pulse (at time T2, also not shown) causes the contents of cell 1 to be transferred to cell 2 and cell 1 itself is then filled with afresh charge representing the new value of the signal presented thereto at that time. The view at time T4 shows the situation after three such pulses (in a complete series of i pulses). By time T4, the original cell contents have been successively transferred, via cells 2 and 3, to cell 4, and cells 3, 2 and 1 hold, in that order, the charges representing the value of the signal presented to cell 1 at times T3, T2 and T1 respectively.

By time T12the original cell 1 contents have reached cell 12, and bytime T16 they have reached the final cell 15 (16) at the output end of the register (the right as viewed). Atthe next clock pulse the contents of cell 16 are transferred out of the register on the output line (103), and at time T22four such transferrals have occurred. At time Tithe number of thesetransferrals is M 6; the signal on the output line is a series of pulses that is in essence the original sine wave F with the clock frequency (CF: in this case 16 times the input sine wave frequency) superimposed, and a simple filter will remove it and leave the output signal indistinguishable from the input signal.

The same register is shown in Figure 2, with the same simple sinewave input atfrequency Fin. However, the sequence shows how the outputfrequency F,,ut varies as the Clock Rate (CR) alternates from CR, to CR2 and back.

Up to time T16 clock rate CR, has transferred in the signal, filling the register. In orderto illustratethe principle, the Figure imagines that CR, was exactly right so as to fill the register with one wavelength in the period TO to T1r,. Thus, CR, = 16 Fin. If the clock rate were to remain at CR, the signal would be transferred on and out, and the output signal would have the same frequency as the input signal - Le, F.ut= Fin. However, if forthe period from T16 up to T32 the clock rate is halved (CR2= 1 /2 CR1) then the register contents are output at half the rate Le, at half the frequency. Forthis period, then, F.',t= 1/2Fin.

Of course, also during the period T16to T32 afresh "batch" of signal has been input, butthistime atCR2 ratherthan CR1. A fu 11 register therefore holds two wavelengths (CR2=8Fin), and when - in the subsequent period from T32to T48 -this is output at clock rate CR, the effect is to make the output signal frequency Fout twice that of the input sig na 1 (Le, F. ut= 2F1,).

The general situation is Fout= CR..t Fin CRin i meaning thatthe output frequency is related to the input frequency by a factor that is the ratio of the outputto inputclocking rates.

Figure 3 shows a schematic diagram fora simple form of circuit according to the invention.

In Figure3two pairsof registers (delay lines 1,2 anc13,4) areconnected byatransmission path.Al KHz signal is inputto line 1,encrypted andfedto line2. Line2then encrypts the encrypted signal fora second time 45 andthis "doubly encrypted" signal istransmittedto line 3. The encryption clueto line2 isdecrypted byline3 andthe resulting singly encrypted signal fed to line4which removes the encryption dueto line 1 to reproduce the unencrypted 1 KHzsignal. Fourclocks (A, B,Cand D) control the data transfer through the registers, clocks Aand B areapplied alternatelyto registers 1 anc14 byswitch S1 andclocksCand D areapplied alternatelyto registers2and 3 byswitch S2.

Inthegeneral case,with a signal offrequency Fin inputto line 1 and clocked through through atratesCR, and CR2 alternatly applied, and through line2atratesCR3and CR4 alternately applied, the situation isas shown in Figure 4, where a signal offrequencyFin isclocked into the first delay line at clock rate CR1. When line 1 isfullthesignal isclocked outof line 1 atclock rate CR2and and into line2 atclockrateCR3.

When line2 isfullthesignal is clocked outof line 2andtransmitted atclockrateCR4.

Ata distant location this encrypted signal is received andclocked into line 3 atclock rateCR4.When line3is fullthesignal isclocked outof line3 atclock rate CR3 and into line4atclockrateCR2.

Finally,when line 4 is full, the signal isclocked outof line4atclock rate CR, asa decrypted signal at frequency Fin.

In this casethe encrypted transmitted signal, which isvulnerableto interception, is frequency shifted to a 60 frequency Fin.CR2. CR4.

CR, CR3 7 GB 2 180 728 A.7 Since the lines 1 to 4 are of equal size and clock frequencies CR, to CR4 area I I different, this transmitted frequency wil I vary among the following four frequencies.

a) Fin. CR2. CR4 CR, CR3 b) Fin.CR1.CR4 CR2 CR, c) Fin.CR2.CR3 CR, CR4 d) Fin.CR1.CR3 CR2 CR4 When applied to speech encryption such a simple system might be expected to suffer severe degradation in speech quality due to the bandwidth increase due to the alternate frequency shifting of the encrypted signal. In practice, over atypical link such as a standard telephone for example, the speech quality is quite impressive, providing good speaker recognition.

The encrypted speech is quite unintelligeable, appearing almost similarto band inversion, butwith a garble" effect.

The blockcliagram of Figure 5 relatesto a way of achieving synchronisation of the encrypting and decrypt- ing registers.

Atone istransmitted either continously (and subsequently filtered outatthe receiver) oratthestartof transmission. Thetone is derived byshaping an outputfrom the encrypt clock generating system and modify- 25 ing to a (possibly) trian gu 1 ar form, or that suitable forthe characteristics of the sytem. Thesignal is not encrypted. Forsysternswith large group delays the frequency should befairly low, typically 200Hz.

Atthe receiverthe encrypted outputfrom the receiverisfedto atone decoder/phase-locked loop.This generatestwo outputs. Thefirst output is a dc pulsewhich is produced on lock-up. This isfed tothedecryp- tion clock generator as a coarse reset.

Theclock reference generator is crystal controlled, its outputfed via a gatetothe decryption clockgenerator. Atone generator derived from an outputof the clockgenerator is settothe same frequency as that atthe transmitter. This iscompared with the second outputof the phase-locked tone decoder by means of a phase sensitive rectifier. If thetwo signals are not in phase,the rectifier output will consist of a series of pulses whosewidth will be a function of relative phase. The outputisshaped and connectedtothe gate atthe inputof 35 the clock generator. As a resulta pulse or pulseswill be "blanked" atthe clock generatorinput. Thetone atthe receiverwill nowslip until it is phasewith the incoming signal, when the phase sensitive detection output disappears. Providing the signals remain in phase no further blanking occurs.

To allowforcrystal oscillator drift, a dcsignal can be derived from the PSIRto adjustthe fundamental crystal frequencyfor ultra fine adjustment.

In Figure 6 an analogue speech encoder/decoder includes an encrypting system 8 and a decrypting system 9.

An analogue speech signal is applied at 10 and is clocked into a 4096 cell shift register 11. The shift register 11 is clocked at a series of different clock rates, these clock rates are derived from a 1 MHz reference frequency generated by a frequency source 12 by a variable divider 13. The variable divider 13 is controlled by a code 45 selector 14which selects a code in response to the signal provided by a pseudo-random code generator 15.

Atthe start of a signal to be encrypted the pseudo-random code generator 15 produces a numberwhich is supplied to code selector 14. Code selector 14 comprises a large read only memory containing all possible sequences of clock rates that can be used in the encoding shift register 11, and a memory addressing system.

When the code selector 14 receives a numberfrom pseudo-random code generator 15 it uses an algorythmto 50 convertthis numberto a memory address and usesthe sequence of clock rates stored atthis memory address. The algorythm used to derivethis address is programmed into the code selector 14 before communications are started. Thus even someone possessing an identical receiverto the authorised recipient of a message cannot decryptthe message unless he knows the algorythm being used.

The possible series of clock rates are all sequences of four clock rates, each clock rate being used for 1024 55 clock pulses and having a total period of 58.368 milliseconds.

Code selector 14then sets thevariable divider 13to feed thefirst of these clock rates to the register 1 1.The number of clock pulses sentto the register 11 is counter by a counter 16 and every 1024 pulses the counter 16 sends a signal to the code selector 14to change the variable divider 13 to the next clockfrequency. Every4096 clock pulses the counter 16 steps the pseudo-random code generator 15 to its next setting. When the code 60 generator 15 is stepped the code selector 14 uses the algorythm to clock up a new sequence of clock rates.

This change in clock rate sequences occurs every 4096 clock pulses - in other words once per registerfull of data, so the data is clocked out of the delay line at different rates to those at which it was clocked in. Thusthe data is encrypted byfrequency shifting, because four different clock rates are used in each 4096 pulse cycle, the signal will have four different frequency shifts per cycle.

8 GB 2 180 728 A 8 This encryptedsignal is then supplied to a transmitted 17 which transmits it.

The transmitted signal is received by a receiver 18 which supplies it to the input of the decryption system 19.

The decryption system 19 includes two shift registers 19A and 1913. Shift registers 19A and 19B are clocked at clock rates derived from a 1 MHz reference frequency generated by a frequency source 20 by variable dividers 21 A and 21 B respectively. The variable dividers 21 A and 21 Bare controlled by a code selector 22 which is in turn controlled by a pseudo-random code generator 23.

Two switches 24 and 30 are arranged so that at any time one of register 19A and 19B is connected to an input of decrypter9 and the other is connected to an output of decrypter9.

When an encrypted signal is fed into the decryption system 9 the switch 24 applies it to the input end of shift register 19A. To decrypt this signal it is read into the shift register 19A at the same sequence of clock rates as it 10 was read out of the shift register 11.

This is achieved by the pseudo-random sequence generators 15 and 23 producing the same pseudo random sequence and being synchronised, the necessary synchronisation can be easily arranged and so need not be described in detail, so that the numbers supplied to the code selector 14 and to the code selector 22 along line 25A are the same. The code selectors 14 and 22 have the same clock pulse sequences stored at 15 equivalent addresses and use the same algorythm to derive addresses f rom the numbers provided. The algorythms can be changed depending on the time, who the recipient of the message is, or in any other predetermined manner, such a procedure is simple and ned not be discussed here.

The code selector 22 controls variable divider 21 Ato read the encrypted signal into register 19A atthe same time itwas read out of register 11. A counter 26 counts the number of clock pulses sentto the register 21Aand 20 signals the code selector 22 along line 27A, every 1024 poulses. When the code selector 22 receives a signal on line 27A it changes the output of variable divider 21 Ato the next clockfrequency.

After 4096 clock pulses, counter 26 signals switches 24 and 30 along line 31. In response to this signal, switches 24 and 30 change position so that shift register 19A is connected to the output of the decrypting system 9, and shift register 19B is connected to the input. Counter 26 also signals the pseudo-random code 25 generator 23 along line 29, in response to this signal the pseudo-random code generator 23 steps to its next setting and providesthis numberto the code selector 22 along a line 2513, it also provides the numbertwo steps before this number in the pseudo-random code sequence to the code selector 22 along the line 25A.

The code selector 22 uses these two numbers to find two memory addresses and obtains two series of clock rates. The series of clock rates found using the present numberfrom the pseudo-random code generator23, 30 which will bethe same as the series being used to clock encrypting register 11, are used by code selector 22to clockthe signal received bythe receiver 18 into the shift register 1913. The series of clock rates found using the two steps back numberfrom the pseudo-random generator code generator 23, which will be the same asthe series which was used to read the data now in shift register 19A out of shift generator 11, are used bycode selector 22 to clock outthe data in register 19Ato an output 32 of the decrypting unit 9.

The counter 26 separately countsthe number of clock pulses going to registers 19A and 19B and signalsthe code selector along lines 27A and 27B respectively every 1024 pulses on the appropriate line. Every4096 pulsesthe counter signals the code selector 22 on line 28. Note that since all code series used produce 4096 pulses in 58.368 msec. the counts of pulses to both registers will reach 4096 simultaneously. When the code selector 22 receives a signal on line 27A it sets variable divider 21 Ato produce the next clockfrequency in the 40 series used to clockthe register 19A, and similarly when it receives a signal on line 2713, it sets variable divider 21 B to produce the next clockfrequency in the series used to clockthe register 1 9B.

Thus encrypted data is read into register 19B atthe same series of frequencies it was read out of encrypting register 11, and the data thatwas previously read into register 19A atthe same series of frequencies as itwas read out of encrypting register 11 is read out of register 19A at the same series of f requencies as it was read 45 into register 1 9A and is decoded.

Atthe end of 4096 clock pulses register 19A is empty and register 19B isfuil, the switches 24 and 30 are changed to connect register 19Ato read in data and register 19B to read out data and the pseudo random sequence generator 23 is stepped. Encrypted data from encrypting register 11 is then fed into register 19A while the data in register 19B is read out in decrypted form. This cycle of use of the two registers 19A and 19B 50 then continues with the lines alternately reading in and reading out data and providing a continuous decryp ted signal at output 32.

The system described could be made more secure by removing the constraint that each clockfrequency in each series of clock frequencies fasts for the same number of pulses, this would allow a very much larger number of possible series to be used. However, it would then be necessary forthe code selectors 14 and 22 to 55 programme counters 16 and 26 respectivelywith the number of pulses that each frequency in each sequence of frequencies would last so thatthe code selectors 14 and 22 could be signalled to alterthe clockfrequencies atthe righttimes.

The system could be made still more secure by arranging the encrypting and decrypting shift registers to be of variable length. All the shift registerswould have to changetheir length simultaneously of course. Such a 60 change could not be madewhile data was being passed through the system without seriously degrading the outputsignal, but it could be carried out during silent parts of the signal, silences being common in speech. A system with this facility would need a sensor in the encrypterto detect silences or blanks in the incoming signal and some meansto inform the decrypter what the new register length was. Itwould also be necessary to a Iterthe clock frequency series produced by selectors 14 and 22 to fit each new register length.

4 ip W 9 Also the signal to be transmitted could be pre-encrypted and post decrypted by another similar encryption/ decryption system, or indeed by any other type of encryption/decryption system.

D 10 AK GB 2 180 728 A 9

Claims (16)

1. A data encryption/decryption method, in which: first and second registers are associated with encryp tion and a third and fourth with decryption; plain-form data is transferred sequentiallythrough thefour analogue shift registers such that each data element is clocked at different clocking rates and for each register data which is fed in atone clocking rate is then fed out at another and data is fed into the third register atthe same clocking rate as itwas fed out of the second register, and is fed out of the third register at the same clocking rate as it was fed into the second register; and data is fed into the fourth register atthe same clocking rate as it was out of the first register and is fed out of the fourth register at the same clocking rate as it wasfed into the first register whereby, by virtue of the resulting frequency shifting, the data transferred between the two pairs of registers is encrypted, butwhen fed out of the fourth register is decrypted, and in plain form.

2. A method as claimed in claim 1, in which the clock rates forthe third and fourth registers are notthe 15 same as, or are not in synchronisation with, those of the first and second registers.

3. A method as claimed in any of the preceding claims, in which, to synchronise the application to each register of the appropriate two different sets of clock pulses, each of the two pairs of registers have theirown, nominally independent, clock pulse source, each pulse source is associated with trigger pulse transmitting/ receiving means, such that the encrypting register pair's timing system can send to the decrypting register 20 pair's timing system a suitable trigger pulse at some appropriate time, and that pulse can be caused to retriggerthe decrypting register's clock, and place the two clocks in perfect synchronisation.

4. A method as claimed in any of the preceding claims, in which, to raise the security level, eitherthefour clock rates are slowly modified according to some preag reed code, or the clock pulse trains are themselves modified in a prearranged manner.

5. A data encryption/decryption method in which a first register is associated with encryption and a second and a third register are associated with decryption; plain form data is fed into the first register ata series of clock rates and then fed out of the first register at a different series of clock rates and fed into the second register atthe same series of clock rates it was fed out of the first register at, when the second register is full the data being fed out of the first register is fed into the third register at the same series of clock rates it 30 was clocked out of the first register at and the data in the second register is fed out atthe same series of clock rates itwas fed into the first register at, when the third register is full the data being fed out of the first register is fed into the second register at the same series of clock rates itwas fed out of the first register at and the data in the third register is fed out atthe same series of clock rates it was fed into thef irst register at, and this cycle of use of the second and third registers is repeated; the series of clock rates supplied to the registers being 35 such that; data transferred between the first register and the second and third registers is encrypted, and the data output of the second and third registers is plain form and the duration of time taken to fill or empty each of the registers with data is a constant.

6. A data encryption/decryption method as claimed in claim 5 in which the first, second and third shift registers are all of equal capacity and the duration of time taken to fill or empty each of the registers with data 40 isthesame.

7. A method as claimed in any preceding claim in which the data is speech.

8. A method as claimed in any of the preceding claims, wherein each shift register is a charge coupled device (CCD).

9. A method as claimed in any preceding claim, in which data is preencrypted by one or more extra registers before being supplied to the encrypting register or registers and is post-decrypted by one or more extra registers after coming out of the decrypting registers.

10. Data encryption/decryption equipment, which includes: four shift registers arranged in a sequence; tranception means whereby the output of the second register can be supplied to the input of the third register, input means forfeeding plain form data to the first register; output means forfeeding plain form data from the fourth register; clock pulse means for each register, forgiving a sequence of different clock signals to the registers to control the transfer of their contents therethrough; and synchronisation means enabling the clock pulse means for each registerto be synchronised one with the other, such that, when plain form data is transferred sequentially through the four registers atfour different clocking rates, (a) for each register, data which is fed in atone clocking rate is then fed out at another, (b) data is fed into the third register at the same 55 clocking rate as it was fed out of the second register, and is fed out of the third register atthe same clocking rate as it was fed into the second register, and (c) data is fed into the fourth register atthe same clocking rate as itwas fed out of the first register, and is fed out of the fourth register atthe same clocking rate as itwas fed into the first register.

11. Data encryption/decryption equipment which includes: a first shift register associated with encryp- 60 tion and a second and a third shift registers associated with decryption; tranception means wherebythe output of the first register can be supplied to the inputs of the second orthird registers; input meansfor feeding plain form data to the first register; output means forfeeding plain form data from the fourth register; clock pulse means for each registerfor giving a sequence of different clock signals to the registers to control the transfer of their contents therethrough: synchronisation means enabling the clock pulse means for each 65 GB 2 180 728 A register to be synchronised one with another; and switching means enabling sections of the output of thefirst register to be supplied alternately to the inputs of the second and third registers, each section being one register full of data, arranged such that wflen plain form data is transferred through the register at a plurality of different clocking rates, for each register data which is fed in atone clocking rate is fed out at another, data is fed into the second register at the same rate as it was fed out of the first, data is fed out of the second register at the same rate it was fed into the first, data is fed into the third register at the same rate it was fed into thefirst and data is fed out of the third register at the same rate it was fed out of the first.

12. Data encryption/decryption equipment as claimed in claim 11 in which thefirst, second and third shift registers are all of equal capacity and the duration of timetaken to fill or empty each of the registerwith data is thesame.

13. Data encryption/decryption equipment as claimed in claim 11 or 12 in which said clock pulse means for each register comprise a variable divider devising clock pulses from a reference frequency source.

14. Data encryption/decryption equipment as claimed in claim 13 in which each variable divider is controlled by control means that select one of a plurality of different sequencies of different clockfrequencies, which sequence is selected being decided by the output of a pseudo-random code generator.

15. Data encryption/decryption equipment as claimed in claim 14 in which which sequence of different clock frequencies is selected in response to each possible output of the pseudo-random code generator can bevaried.

16. Data encryption/decryption equipment as claimed in any of claims 11 to 15 in which each clock signal 'i W Il in the sequence of different clock signals contains the same number of bits. 20 Printed for Her Majesty's Stationery Office by Croydon Printing Company (11 K) Ltd,2187, D8991685. Published by The Patent Off[ce,25Southampton Buildings, London WC2A I AY, from which copies maybe obtained.

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