US4079195A - Method and apparatus for the synchronization of a deciphering device functioning as a receiver with an enciphering device functioning as transmitter - Google Patents

Method and apparatus for the synchronization of a deciphering device functioning as a receiver with an enciphering device functioning as transmitter Download PDF

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Publication number
US4079195A
US4079195A US05/652,758 US65275876A US4079195A US 4079195 A US4079195 A US 4079195A US 65275876 A US65275876 A US 65275876A US 4079195 A US4079195 A US 4079195A
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auxiliary
information
pulses
pulse groups
pulse
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US05/652,758
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English (en)
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Peter Frutiger
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Anstalt Europaeische Handelsgesellschaft
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Anstalt Europaeische Handelsgesellschaft
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/12—Transmitting and receiving encryption devices synchronised or initially set up in a particular manner

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  • the present invention relates to a new and improved method of synchronizing a deciphering device operating as a receiver with an enciphering device operating as a transmitter, and furthermore, the present invention relates to apparatus for the performance of the aforesaid method.
  • Enciphering and deciphering devices which cooperate in a digital network as transmitter and receiver, respectively, are conventionally equipped with Key pulse Generators which, as a general rule are stepped forward for each character pulse to be enciphered and deciphered respectively. Consequently, synchronism of the receiver end Key Generator, required for proper deciphering, with the Key Generator at the transmitter end is ensured. Of course, there is presupposed that at the start of the transmission of the message the Key Generators at the transmitter end and receiver end have the same starting position.
  • the Key Generators are programmed with a secret base information, the Basic Key, which is valid for a certain period of time for all devices hooked up to the network. Starting from this base information there is determined for each transmitted message a certain starting information, commonly called the Message Key. The starting information need not of necessity be secret, provided that knowledge thereof without the base information is useless to an unauthorized individual. In practice such Message Key information is placed ahead of the actual message. By means of this MK receiver end device is brought into the same starting position as the transmitter end device.
  • the synchronization of the Key Generators at the transmitter end and receiver end at the start of the transmission of a message or text is especially problematic in the case of meshed or interconnected networks where messages of high information content or density are transmitted in various directions always between different stations. If, for instance, station A has transmitted a message during a predetermined time duration T to station B, then, as explained above, the Key Generators of these stations A and B are advanced through a number of steps corresponding to the length of the transmitted message. Now if station A or station B is supposed to transmit a message to station C which was not operational during the aforementioned time duration T, then, first of all the Key Generator of such station C must be synchronized with the Key Generator of station A or station B, as the case may be. This synchronization or placing in step of the Key Generators with one another must occur very rapidly.
  • Another and more specific object of the present invention aims at the provision of a new and improved method of, and apparatus for, synchronizing a deciphering device working as a receiver with an enciphering device working as a transmitter and allowing placing in step or synchronization of the transmitter end and receiver end Key Generators at the start of message transmission and, when necessary, also during message transmission.
  • each introduced auxiliary pulse series is produced according to a given formation principle from the preceding introduced auxiliary pulse series.
  • the pulse series transmitted by the transmitter are stored in a buffer memory, the stored pulses compared with comparison pulse series in order to determine the coincidence of the stored auxiliary pulse series with the comparison pulse series.
  • the comparison pulse series possess the same number of pulses and are formed according to the same formation principle as the auxiliary pulse series. Moreover, after determination of coincidence of the comparison pulse series with the stored auxiliary pulse series the latter are separated from the stored information pulse series.
  • the invention not only concerns the aforementioned method aspects but also relates to apparatus for the performance thereof and is manifested by the features that at the transmitter end there is present a switching device at the first input of which there appear the information pulses and the second input of which is connected with an auxiliary pulse generator.
  • the output of the switching device can be connected during a fixed first number of clock steps with the first input and during a fixed second number of clock steps with the second input.
  • a buffer memory and a comparison pulse generator which is coupled with a comparison stage which compares the pulses stored in the buffer memory with the comparison pulse series produced by the comparison pulse generator and which after determination of the coincidence of the stored auxiliary pulse series with the comparison pulse series acts upon a circuit for separating the pulses the information pulses from one another.
  • FIG. 1 is a block diagram of circuitry at the transmitter end
  • FIG. 2 is a block diagram of circuitry at the receiver end
  • FIG. 3 schematically illustrates the pulse train formed by means of the circuit of FIG. 1;
  • FIG. 4 schematically illustrates a component of the circuitry of FIG. 1;
  • FIG. 5 illustrates a reinjected shift register constituting a component of the circuitry of FIGS. 1 and 2;
  • FIG. 6 schematically illustrates the buffer memory of the circuit according to FIG. 2.
  • FIG. 7 illustrates the pulse train in columns and lines produced by the shift register of FIG. 5.
  • the clock generators of the transmitting station and receiving station operate synchronously with the aid of a non-illustrated conventional clock synchronization device so that the reference clock speed in the transmitting device and receiving device can be considered to be the same.
  • the information coded in the aforementioned manner is enciphered at the transmitter end in the mixing stage (not shown) in conventional manner.
  • the enciphered information depicted in FIG. 1 by the train of information pulses 1, is inserted with the frequency f o into a shift register 2.
  • the information stored in the shift register 2 is delivered to one input A of a changeover switch 3 with a clock frequency f 1 which is higher than the frequency f o .
  • a counter 4 is coupled with this switch 3.
  • the input B of the switch 3 has delivered thereto at the frequency f 1 auxiliary pulses generated by an auxiliary pulse generator 5 which, in the embodiment under discussion, is constituted by a reinjected shift register.
  • the feedback occurs by means of an Exclusive-Or-circuit 6.
  • the auxiliary pulses are of the same type as the information pulses 1, so that these auxiliary pulses can be transmitted in the same manner as the information pulses. However, in contrast to the information pulses the auxiliary pulses are formed according to a certain principle or law.
  • auxiliary pulse generator 5 The mode of operation of the auxiliary pulse generator 5 will be explained more fully based upon referring to FIG. 5.
  • the counter 4 causes changeover switch 3 to connect its input A with its output C during five clock steps and then to connect its input B with its output C during the next three clock steps.
  • the output C of the switch 3 is connected with a shift register 7 in which receives the information and auxiliary pulses at the frequency f 1 .
  • the information stored in the shift register 7 is recalled in the form of an endless pulse train 8 and transmitted in any desirable manner to the receiving station. If desired possible to remove the pulse series 8 directly at the output C of the reversing switch or switching device 3.
  • FIG. 3 there is schematically illustrated the generation of the information pulse train 8 by the circuitry of FIG. 1. Between successive groups of five information pulses 1 there is inserted a group of three auxiliary pulses 9 which, as described, occurs by means of the switch 3 of FIG. 1.
  • FIG. 4 there is illustrated a stepping mechanism which functionally corresponds to the switch 3 including the counter 4 of FIG. 1.
  • the coil 10b of an electromagnet 10 is connected at one end at the terminal "0" of a not particularly illustrated voltage source.
  • the other end of the coil 10b is connected via a resistor 11 with the contact 12a of a switch 12, the other contact 12b of which is connected to the positive terminal "+" of the voltage source.
  • a capacitor 13 is connected in parallel with the coil 10b of the electromagnet 10.
  • the armature 10a of the electromagnet 10 is constructed as stepping or feed pawl for a ratchet wheel 14 or equivalent structure.
  • the armature 10a is rotatably mounted on a pivot 15 and cooperates by means of its one end 10c with the contact 12b of the switch 12.
  • the armature 10a is rocked by a tension spring 16 into the position illustrated in FIG. 4 where it is out of engagement with the teeth 14a of the ratchet wheel 14 and holds closed the contact 12.
  • a blocking pawl 17 is drawn by means of a spring 17a or equivalent structure into the gaps between neighboring teeth 14a in order to prevent any return rotation of the ratchet wheel 14.
  • a shift 18 connected with the ratchet wheel 14 carries at its other end a contact arm 19 cooperating with contacts 20 arranged in a circular configuration.
  • the contact arm 19 is connected via a sliding contact 21 with the terminal C which corresponds to the output C of the reversing switch or switching device 3 of FIG. 1.
  • Five neighboring contacts 20 are connected together and coupled with a terminal A corresponding to the input A of the switch 3 of FIG. 1.
  • the remaining three contacts 20 are all connected with a terminal B which corresponds to the input B of the switch 3 of FIG. 1.
  • the armature 10a assumes the position illustrated in FIG. 4 and the switch 12 is closed.
  • the coil 10b of the magnet 10 is energized. Since the capacitor 13 first must be charged the attraction of the armature 10a occurs with a time-delay. Due to the attraction of the armature 10a the ratchet wheel 14 is rotated in clockwise direction through one tooth division and the blocking pawl 17 prevents a return rotation. Together with the rotation of the ratchet wheel 14 the contact arm 19 is also rotated to the next successive contact 20.
  • terminal A is connected to the shift register 2 and the terminal B to the shift register 5 of FIG. 1, then it will be seen that the terminal C is connected each time through five clock steps with the shift register 2 and during the following three clock steps with the shift register 5.
  • the shift register 5 is a three stage register.
  • the feedback logic circuit comprises an Exclusive-Or-gate 6, the inputs 6a and 6b of which are connected with the first and third stages of the shift register 5 and the output 6c of which is connected with the first stage of such shift register.
  • the information inserted in each instance during each clock pulse in the first shift register stage I is formed from the information previously stored in the first and third stages I, III, and specifically according to the following truth table:
  • Position 1 there is illustrated a random condition or state of the shift register 5.
  • Position 1a illustrates the intermediate state after a shift step towards the right without refilling the first stage.
  • Position 2 illustrates the state after a first complete clock step.
  • position 3 to 7 there are illustrated the successive states of the shift register 5.
  • positions 8 there is again reached the state according to position 1. After seven steps there has been reached, apart from the state "B,” “B,” “B” which would not lead to any new state according to the operational principle, each of the possible states at least once.
  • FIG. 2 there is illustrated circuitry at the receiver end which in a manner to be discussed more fully hereinafter is capable of separating the information pulses from the auxiliary pulses.
  • This circuitry comprises a storage matrix 22 which, in the embodiment being considered, will be seen to possess four lines and eight columns.
  • Reference character 23 designates a comparison stage or comparator which is coupled with a comparison bit generator 24 serving for producing comparison bit groups and which in the case under discussion is a reinjected shift register.
  • the feedback occurs with the aid of an Exclusive-Or-gate 25.
  • the shift register 24 together with the feedback logic circuit 25 corresponds both in construction and mode of operation to the reinjected shift register 5 of FIGS. 1 and 5.
  • switch 26 Connected with the output of the storage matrix 22 is a switch 26 which is opened and closed by the comparison stage 23 in a manner still to be described. Further, switch 26 is connected to a shift register 27.
  • FIG. 6 there is illustrated the storage of the arriving or incoming information pulses in the storage matrix 22.
  • the auxiliary pulses have been designated by "A” and "B” and the information pulses by "L” and "0.” Mention is again made of the fact that such distinguishment is not present in reality since the auxiliary pulses and information pulses are of the same type.
  • FIG. 6a illustrates the storage in the first line.
  • FIG. 6a there have been stored both of the first bits "O" and "L" of the information pulse group.
  • FIG. 6b there have been stored nine bits i.e., five information bits, three auxiliary bits and a further information bit.
  • Both of the bits shown in FIG. 6a are now located in line 2, column 1 and line 1, column 8.
  • FIGS. 6c and 6d illustrate the state of the storage matrix 22 after there has occurred the further storage of bits.
  • FIG. 6d illustrates the storage matrix 22 in an almost filled condition or state. Both of the bits which have been stored and illustrated in FIG. 6a are now located in line 4, columns 6 and 7.
  • FIG. 6e illustrates the condition or state which results from FIG. 6d five clock pulses later.
  • the first stored bits (FIG. 6a) have now disappeared.
  • FIGS. 6f, 6g and 6h illustrate the relevant states after a further three, further seven and further two clock pulses, respectively.
  • auxiliary bits "A,” "B” always appear in columns. These columns can be located adjacent one another (FIGS. 6e and 6h), or however can be the first two and the last columns (FIGS. 6d and 6f), or the first and both of the last columns (FIG. 6g).
  • FIG. 7 there are illustrated the states of the shift register 24 (FIGS. 2 and 5) arranged in lines in columns, wherein the content of each line is shifted by one step relative to the content of the line situated thereabove.
  • the bit group of line 1, column I is located in line 2 of column II, in line 3 in column III and in line 4 in column IV.
  • the first line of the illustration of FIG. 7 corresponds to the illustration of the state of the shift register 5 and 24 respectively, selected in FIG. 5.
  • the above-described comparison of the information stored in the columns of the storage matrix 22 with the comparison bits which are produced by the shift register 24 is carried out by the comparison stage 23 (FIG. 2).
  • the comparison stage 23 As soon as the comparison stage 23 has determined by comparison the position of the auxiliary bit group in the received pulse train and the bit group stored in the storage matrix 22, then each time for five clock steps it closes the switch 26 and again opens the same for the next following three clock steps.
  • the switch 26 is closed, the output of the storage matrix 22 is connected with the input of the shift register 27.
  • the information bits stored in the storage matrix 22 are thus stored in the shift register 27, whereas the auxiliary bits are separated out during the three clock steps during which the switch 26 is opened.
  • the information bits are then removed and further processed i.e., deciphered as continuous information pulse train 28 from the shift register 27. Apart from transmission errors, this information pulse train 28 corresponds to the information pulse train 1 at the transmitter end (FIG. 1).
  • auxiliary pulses are changed by transmission faults or defects, then there is rendered somewhat difficult the location of the auxiliary pulse groups at the receiver end since no longer all of the pulses of the auxiliary pulse groups represent the state required according to the information principle. It is however still possible to determine the correct position of the auxiliary pulse groups. With the transmitter and receiver placed into the same position i.e. synchronized, transmission defects hardly have a distrubing effect since for the confirmation of the proper operation there are required only a few correct auxiliary pulses.
  • the receiver If the receiver has moved out of step during the information transmission, for instance owing to a disturbance lasting over a longer period of time, for instance a breakdown and so forth, then, the receiver again will synchronize-in at the transmitter end in the previously described manner as soon as there are received in the shift register a sufficient number of correct auxiliary pulse groups.
  • auxiliary pulses separated out at the receiver end by means of the circuitry of FIG. 2 can be utilized for the synchronization of the Key Generators of the receiving station and the transmitting station. Each auxiliary pulse group is then characteristic for the momentary condition or state of the Key Generator.
  • the synchronization of the Key Generators in this manner constitutes subject matter of the commonly assigned copending U.S. application Ser. No. 653,757filed Jan. 27, 1976 entitled “Method And Apparatus For Synchronizing A Receiver End Key Character Generator With A Transmitter End Key Character Generator", the disclosure of which is incorporated herein by reference.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Radio Relay Systems (AREA)
  • Dc Digital Transmission (AREA)
US05/652,758 1975-02-05 1976-01-27 Method and apparatus for the synchronization of a deciphering device functioning as a receiver with an enciphering device functioning as transmitter Expired - Lifetime US4079195A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH1366/75 1975-02-05
CH136675A CH581930A5 (da) 1975-02-05 1975-02-05

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US (1) US4079195A (da)
JP (1) JPS51103715A (da)
AR (1) AR229335A1 (da)
AT (1) AT346395B (da)
BE (1) BE838158A (da)
CA (1) CA1054066A (da)
CH (1) CH581930A5 (da)
DE (1) DE2603843C2 (da)
DK (1) DK42876A (da)
FI (1) FI753737A (da)
FR (1) FR2300472A1 (da)
GB (1) GB1512925A (da)
IT (1) IT1055059B (da)
NL (1) NL7601009A (da)
NO (1) NO760340L (da)
SE (1) SE7601091L (da)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4176246A (en) * 1977-03-16 1979-11-27 Anstalt Europaische Handelsgesellschaft Apparatus for the transmission end-enciphering and reception end-deciphering of information
US4305152A (en) * 1978-03-31 1981-12-08 Tokyo Shibaura Denki Kabushiki Kaisha Security communication system
US4435826A (en) 1980-09-05 1984-03-06 Hitachi, Ltd. Frame synchronizer
US4506372A (en) * 1981-11-11 1985-03-19 Lgz Landis & Gyr Zug Ag. Method and apparatus for recognizing in a receiver the start of a telegram signal consisting of a bit impulse sequence
US4661980A (en) * 1982-06-25 1987-04-28 The United States Of America As Represented By The Secretary Of The Navy Intercept resistant data transmission system
US6590981B2 (en) * 2000-02-22 2003-07-08 Zyfer, Inc. System and method for secure cryptographic communications

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DE3207040A1 (de) * 1982-02-26 1983-09-08 Siemens AG, 1000 Berlin und 8000 München Vefahren und anordnung zum uebertragen von zeichen
DE3518462A1 (de) * 1985-05-23 1986-11-27 Standard Elektrik Lorenz Ag, 7000 Stuttgart System zur verschluesselten nachrichtenuebertragung
DE3832946A1 (de) * 1988-09-28 1990-04-05 Siemens Ag Verfahren zur verschluesselung digitaler zeitmultiplexsignale
US5237593A (en) * 1989-05-04 1993-08-17 Stc, Plc Sequence synchronisation

Citations (6)

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Publication number Priority date Publication date Assignee Title
US3597539A (en) * 1968-12-04 1971-08-03 Itt Frame synchronization system
US3639838A (en) * 1968-01-30 1972-02-01 Hughes Aircraft Co Synchronized variable delay time division communication system
US3740478A (en) * 1971-10-19 1973-06-19 Philips Corp Pseudo-random multiplex synchronizer
US3823266A (en) * 1971-07-21 1974-07-09 Philips Corp Synchronization system
US3936601A (en) * 1974-05-28 1976-02-03 Burroughs Corporation Method and apparatus for altering the synchronous compare character in a digital data communication system
US3969582A (en) * 1973-12-21 1976-07-13 De Staat Der Nederlanden, Te Dezen Vertegenwoordigd Door De Directeur-Generaal Der Posterijen, Telegrafie En Telefonie System for automatic synchronization of blocks transmitting a series of bits

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Publication number Priority date Publication date Assignee Title
DE1076733B (de) * 1958-05-29 1960-03-03 Telefunken Gmbh Anordnung zur Sicherstellung des Synchronlaufs der Schluessel-zeichengeneratoren aufder Sende- und Empfangsseite bei der Geheimuebertragung von kodierten Nachrichtensignalen
FR1582790A (da) * 1968-01-16 1969-10-10
CH539989A (de) * 1971-04-19 1973-07-31 Gretag Ag Verfahren und Vorrichtung zur chiffrierten Nachrichtenübermittlung

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3639838A (en) * 1968-01-30 1972-02-01 Hughes Aircraft Co Synchronized variable delay time division communication system
US3597539A (en) * 1968-12-04 1971-08-03 Itt Frame synchronization system
US3823266A (en) * 1971-07-21 1974-07-09 Philips Corp Synchronization system
US3740478A (en) * 1971-10-19 1973-06-19 Philips Corp Pseudo-random multiplex synchronizer
US3969582A (en) * 1973-12-21 1976-07-13 De Staat Der Nederlanden, Te Dezen Vertegenwoordigd Door De Directeur-Generaal Der Posterijen, Telegrafie En Telefonie System for automatic synchronization of blocks transmitting a series of bits
US3936601A (en) * 1974-05-28 1976-02-03 Burroughs Corporation Method and apparatus for altering the synchronous compare character in a digital data communication system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4176246A (en) * 1977-03-16 1979-11-27 Anstalt Europaische Handelsgesellschaft Apparatus for the transmission end-enciphering and reception end-deciphering of information
US4305152A (en) * 1978-03-31 1981-12-08 Tokyo Shibaura Denki Kabushiki Kaisha Security communication system
US4435826A (en) 1980-09-05 1984-03-06 Hitachi, Ltd. Frame synchronizer
US4506372A (en) * 1981-11-11 1985-03-19 Lgz Landis & Gyr Zug Ag. Method and apparatus for recognizing in a receiver the start of a telegram signal consisting of a bit impulse sequence
US4661980A (en) * 1982-06-25 1987-04-28 The United States Of America As Represented By The Secretary Of The Navy Intercept resistant data transmission system
US6590981B2 (en) * 2000-02-22 2003-07-08 Zyfer, Inc. System and method for secure cryptographic communications

Also Published As

Publication number Publication date
CH581930A5 (da) 1976-11-15
FR2300472A1 (fr) 1976-09-03
NO760340L (da) 1976-08-06
FR2300472B1 (da) 1981-12-31
AT346395B (de) 1978-11-10
DE2603843C2 (de) 1985-06-20
DK42876A (da) 1976-08-06
IT1055059B (it) 1981-12-21
JPS51103715A (da) 1976-09-13
AR229335A1 (es) 1983-07-29
CA1054066A (en) 1979-05-08
ATA71876A (de) 1978-03-15
SE7601091L (sv) 1976-08-06
BE838158A (fr) 1976-05-28
FI753737A (da) 1976-08-06
NL7601009A (nl) 1976-08-09
DE2603843A1 (de) 1976-08-19
GB1512925A (en) 1978-06-01

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