US3987251A - Time division switching network for switching multirate multiplexed data - Google Patents

Time division switching network for switching multirate multiplexed data Download PDF

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Publication number
US3987251A
US3987251A US05/645,237 US64523775A US3987251A US 3987251 A US3987251 A US 3987251A US 64523775 A US64523775 A US 64523775A US 3987251 A US3987251 A US 3987251A
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order
channels
channel
multiplexing
octets
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US05/645,237
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Alain Texier
Edgar L. Lapeyronnie
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1623—Plesiochronous digital hierarchy [PDH]
    • H04J3/1629—Format building algorithm
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
    • H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M11/00—Telephonic communication systems specially adapted for combination with other electrical systems
    • H04M11/06—Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
    • H04M11/064—Data transmission during pauses in telephone conversation

Definitions

  • incoming time-division second-order multiplex channels 1 0 to 1 255 at an user rate of 64 kbit/s and in which the octets are serially conveyed are multiplexed into 8 parallel multiplex junctions 2 0 to 2 7 each at the rate of 2.048 Mbit/s - i.e., where the time slots allotted to the incoming multiplex channels are 125/256 ⁇ 0.5 ⁇ s.
  • the 8 multiplex junctions 2 0 to 2 7 transmit the bits of the octets in parallel, one bit on each of the junctions.
  • the second-order incoming channels 1 0 to 1 255 are composite channels of known type, each having three individual channels, one transmitting 64 kbit/s data, the second transmitting a 64 kHz clock or timing bit signal, and the third transmitting a 8 kHz clock or timing octet signal.
  • the latter channels which, in the earlier patent application mentioned, arise from monorate multiplexing of first-order channels, either of 5 12.8 kbit per s. channels exclusively or of 20 3.2 kbit per s. channels exclusively or of 80 0.8 kbit per s. channels exclusively arise in the present case from a multirate multiplexing of first-order channels comprising e.g.:
  • composition of the other second-order channels does not need to be given here.
  • the multiplexings of the first-order channels into second-order channels are performed in multiplexers 13, 14, 15 respectively as regards second-order channels 1 0 , 1 1 , 1 2 .
  • the multiplexing of the 256 64 kbit/s channels is performed in a multiplexer 11.
  • Each multiplexer 13, 14, 15 comprises in known manner a respective time base 130, 140, 150 producing timing pulses at the frequency of the incoming data and timing pulses at the frequency of the outgoing data, and a respective buffer store 131, 141, 151.
  • the octets are written into the respective store 131, 141, 151 under the control of the timing signals at the frequency of the incoming data; during write-in, the first bit -- i.e., the framing bit -- is eliminated and replaced by a bit F of the multiframing sequence produced by the multiframing sequence generator 23, 24, 25 respectively.
  • Such generators are known in the art. The earlier patent application hereinbefore alluded to described such a generator, of use for producing an 80-bit pseudorandom multiframing sequence and which can be used without alteration as the generator 23 or 24 or 25 of FIG. 1a.
  • the multiplexer 11 which multiplexes already multiplexed signals comprises in conventional manner a time base 110, a series-to-parallel converter 112 and a buffer store 111.
  • Time base 110 defines incoming-bit time 66 lasting approximately 16 ⁇ s and outgoing time slots of 0.5 ⁇ s.
  • the incoming bits are in series and an octet lasts for a 16 ⁇ 8 ⁇ 125 ⁇ s time slot.
  • the outgoing octets are in parallel and last for a 0.5 ⁇ s time slot.
  • Multiplexer 11 is associated with an octet address computer 40 (FIG. 1b) connected to whichever of the multiplex 2.048 Mbit/s junctions transmits the first bits of the octets (assumed to be the multiplex junction 2 0 ), computer 40 being connected to time base 110.
  • An octet computer of this kind is described in the patent application previously mentioned.
  • the octets and their first bits form 256 interlaced sequences.
  • each octet has a two-part address. The first part thereof is between 0 and 255 and is the rank of the octet in the frame of 256 0.5 ⁇ s time slots forming the parallel 2.048 Mbit/s multiplex.
  • the first part of the address therefore contains 8 bits.
  • the second part of the address is the channel address in the 80-octet multiframe.
  • the number of bits in the second part of the address varies according as the second-order 64 kbit/s channel has been formed by the multiplexing of 5 or 20 or 80 first-order channels.
  • each channel appears with 16 recurrent octets in the multiframe, so the second part of the address is between 0 and 4 and has 3 bits.
  • each channel appears with 4 recurrent octets in the multiframe; consequently, the second part of the address is between 0 and 19 and has 5 bits.
  • each channel appears with just a single octet in the multiframe and so the second part of the address is between 0 and 79 and contains 7 bits.
  • the address of the octet in the second-order channel (between 0 and 79) automatically gives the addresses of the first-order channel, since for a given second-order digital channel 1 j (0 ⁇ j ⁇ 255) of address j (first part of the octet address) it is known which first-order channels of high or intermediate or low rate are multiplexed in such second-order channel.
  • i denote the number of the octet between 0 and 79.
  • the channel number is the remainder q x of the division i/5.
  • the channel number is the remainder q y of the division i/20.
  • the channel number is the remainder q z of the division i/80 whereby the channel number is identical to the octet number i.
  • the first-order channel address cannot be deduced automatically from the address of the octet in the multiframe of the second-order channel and, as stated in the opening part hereof, a table contained in a read-only store 60 must be available.
  • Store 60 is addressed for reading-out by the address (first and second parts) of the octet and supplies the address of the first-order channel.
  • the first-order channel multiplexing schedule given in Table II of the opening part hereof corresponds to the second-order digital channel 1 107 , in which case the first part of the octet number is
  • octet 58 of channel 107 belongs to the fifth of the 8 low-rate channels or, if the channels are numbered from 1 to 20, to the 17th channel.
  • the first-order channel address ChA supplied by read-only store 60 effects a read-out addressing of the marking store 50 of the data switching network.
  • the latter store contains marking words (MW) which can be selectively directed to the control unit 52 or to the buffer store 53.
  • the marking words comprise a status bit (StB) which is a one or a zero according to the actual state of the communication. In proportion as the communication establishment proceeds, the marking word goes from the marking store to the control unit, where it is modified and sent back to the marking store. It can be said that the processing of connection and disconnection progresses by modification of the marking word.
  • the status bit (StB) of the marking word indicates whether the data channel from which an octet is received is in the data-transmitting state or in the signalling state. Further, the marking word contains the address of the correspondent if the channel is being transmitting data, or call-processing bits if the channel is being transmitting signalling in view of connection.
  • a signalling octet (SOc) supplied by control unit 52 is written into the buffer store at the address (ChA) of the incoming channel.
  • inverter 50 which converts the status bit (StB) which equal to zero into a one
  • the gates 56 are open by the inverted status bit and connect the control unit to the information inputs of store 53, and gates 57 are also open and connect store 60 to the write-in addressing inputs of store 53.
  • the octets IOc may be data octets or signalling octets.
  • the octets IOc are stored in buffer memory 53 through gates 54 at the address of the called party.
  • the called party address is contained in the marking word and is applied to the write-in address inputs of buffer store 53 through gates 55.
  • the octets IOc are signalling octets, they are sent to control unit 52.
  • This control unit generates signalling octets SOc which are stored in the buffer memory 53 through gates 56 at the address of the calling party. This is to inform the calling parts of the processing of the call (calling tone, ringing back tone, etc.).
  • the calling party address is contained in the read-only memory store 60 and is applied to the write-in address inputs of buffer store 53 through gates 57.
  • read-out from the buffer store 53 was controlled directly by time base 110. In the present case, however, read-out from store 53 is controlled by time base 110 which gives the addresses of the outgoing octets through the read-only store 60 which gives the addresses of the corresponding first-order channels.
  • the first bits of the octets written into the buffer store 53 are removed at write-in and are replaced at read-out by the bits F of a pseudorandom multiframing sequence produced by generator 58.
  • the octets to carry the bits of the multiframing sequence are the octets of a single 2.048 Mbit/s multiplex channel, e.g.
  • the channel 102 0 since all the 256 64 kbit/s multiplex channels are phase-locked at the output there is no need to apply to the octets the bits of the multiframing sequences in shared time.
  • the first bit of the pseudorandom sequence can be applied to the 256 outgoing second-order multiplex channels of the first frame, the second bit of the sequence can then be applied to the 256 outgoing second-order multiplex channels of the second frame, and so on up to the 80th bit of the sequence.
  • the 256 pseudorandom multiframing sequences of the octets of the frames of the 256 second-order multiplex channels are out of phase in the case of the incoming second-order multiplex channels and in phase in the case of the outgoing second-order multiplex channels.
  • the octets with their multiframing sequence bits and appearing in parallel at the 2.048 Mbit/s third-order multiplex junctions 102 0 to 102 7 are applied to a multiplex demultiplexer 11' which converts the 8 2.048 Mbit/s parallel multiplexed channels 102 0 to 102 7 into 256 serial 64 kbit/s multiplexed channels 101 0 to 101 255 .
  • the demultiplexer 11' shares the time base 110 with the multiplexer 11 and has a parallel-to-series converter 112' and a buffer store 111'.
  • the multiplex channel 101 0 was demultiplexed into two 12.8 kbit/s channels 103 0 and 103 1 , 10 3.2 kbit/s channels 104 0 to 104 9 and 8 0.8 kbit/s channels 105 0 to 105 7 in the demultiplexer 113, that the multiplex channel 101 1 was demultiplexed into 3 12.8 kbit/s channels 103 2 , 103 3 and 103 4 , 5 3.2 kbit/s channels 104 10 to 104 14 and 12 0.8 kbit/s channels 105 8 to 105 19 in the demultiplexer 114 and that the multiplex channel 101 2 was demultiplexed into 4 12.8 kbit/s channels 103 5 to 103 8 , no 3.2 kbit/s chennel and 16 0.8 kbit/s channels 105 20 to 105 35 in the demultiplexer 115.
  • Each of the demultiplexers 113, 114, 115 has a respective time base 1130, 1140, 1150 and a respective buffer store 1131, 1141, 1151.
  • Associated with each demultiplexer 113, 114, 115 is a multiframe recovering circuit 123, 124, 125 respectively of the kind described in the earlier patent application mentioned herein.
  • the output of the transcoder of the multiframe recovering circuit is used as a register for addressing the demultiplexer buffer store.
  • 80 can be written in quaternary notation as:
  • t, x, y, z are quaternary digits having the value 0 or 1 or 2 or 3. If x, y and z can have values greater than 3, reducing x by one unit is the same as increasing y by 4 units or as increasing z by 16 units, and decreasing y by one unit is the same thing as increasing z by 4 units.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
US05/645,237 1974-12-27 1975-12-29 Time division switching network for switching multirate multiplexed data Expired - Lifetime US3987251A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR74.43116 1974-12-27
FR7443116A FR2296320A1 (fr) 1974-12-27 1974-12-27 Reseau de commutation numerique du type a multicadence par multiplex

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US3987251A true US3987251A (en) 1976-10-19

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US (1) US3987251A (it)
JP (1) JPS5190203A (it)
CA (1) CA1060976A (it)
CH (1) CH608676A5 (it)
DE (1) DE2558599C3 (it)
FR (1) FR2296320A1 (it)
GB (1) GB1501165A (it)
IT (1) IT1051946B (it)
NL (1) NL7515091A (it)
SE (1) SE431146B (it)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4160128A (en) * 1976-03-31 1979-07-03 Texier Alain G Digital data transmission system providing multipoint connections
US4168401A (en) * 1977-04-05 1979-09-18 Societe Anonyme De Telecommunications Digital switching unit for a multirate time-division multiplex digital switching network
WO1980000775A1 (en) * 1978-09-25 1980-04-17 Western Electric Co Time-division switching system for multirate data
US4244046A (en) * 1978-02-07 1981-01-06 Societe Anonyme De Telecommunications Digital data transmission system providing multipoint communications
US4246530A (en) * 1978-12-04 1981-01-20 International Telephone And Telegraph Corporation Memory network for TDM switching system
US4330689A (en) * 1980-01-28 1982-05-18 The United States Of America As Represented By The Secretary Of The Navy Multirate digital voice communication processor
US4370648A (en) * 1981-03-31 1983-01-25 Siemens Corporation Synchronizing circuit for use with a telecommunication system
US4377860A (en) * 1981-01-05 1983-03-22 American Microsystems, Inc. Bandwidth reduction method and structure for combining voice and data in a PCM channel
US4512014A (en) * 1979-08-24 1985-04-16 Siemens Aktiengesellschaft Time slot multiplex system for the division multiplexing of digital communication signals
US4654860A (en) * 1983-06-16 1987-03-31 The Boeing Company Spacecraft telemetry regenerator
US4751699A (en) * 1985-09-12 1988-06-14 Andre Tarridec Multiplexing and demultiplexing equipments for a synchronous digital link with variable modulation speed and rate
US4788679A (en) * 1986-09-02 1988-11-29 Nippon Telegraph And Telephone Corporation Packet switch with variable data transfer rate links
US4939723A (en) * 1989-06-07 1990-07-03 Ford Aerospace Corporation Bit-channel multiplexer/demultiplexer
US5490258A (en) * 1991-07-29 1996-02-06 Fenner; Peter R. Associative memory for very large key spaces
US5842224A (en) * 1989-06-16 1998-11-24 Fenner; Peter R. Method and apparatus for source filtering data packets between networks of differing media
US20050063382A1 (en) * 1989-06-16 2005-03-24 Fenner Investments, Ltd. Packet switching node

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3224769A1 (de) * 1981-11-19 1983-05-26 Robert Bosch Gmbh, 7000 Stuttgart Kraftstoffeinspritzeinrichtung fuer brennkraftmaschinen, insbesondere pumpeduese fuer dieselbrennkraftmaschinen
US4490819A (en) * 1982-04-22 1984-12-25 International Telephone And Telegraph Corporation Rate converter
DE3228518A1 (de) * 1982-07-29 1984-02-09 Heinrich-Hertz-Institut für Nachrichtentechnik Berlin GmbH, 1000 Berlin Schaltungsanordnung zur aufbereitung von pcm-systemen zum zwecke der vermittlung
FR2548490A1 (fr) * 1983-06-30 1985-01-04 Thomson Csf Circuit programmable de transformation serie-parallele d'un signal numerique, et son application a un recepteur de signaux video numeriques
JPH0824386B2 (ja) * 1986-09-30 1996-03-06 日本電気株式会社 選択呼出信号受信機

Citations (6)

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Publication number Priority date Publication date Assignee Title
US3535450A (en) * 1966-12-08 1970-10-20 Siemens Ag Multiplex transmission method
US3794768A (en) * 1972-05-25 1974-02-26 Bell Telephone Labor Inc Cross-office connecting scheme for interconnecting multiplexers and central office terminals
US3890469A (en) * 1973-12-04 1975-06-17 Gte Automatic Electric Lab Inc Time division switching system
US3894189A (en) * 1972-02-08 1975-07-08 Ericsson Telefon Ab L M Method of operating file gates in an exchange for PCM words
US3922494A (en) * 1973-03-26 1975-11-25 British Minister Of Defence Data signal switching apparatus
US3952162A (en) * 1974-05-28 1976-04-20 Texier Alain G Time division digital switching network

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3535450A (en) * 1966-12-08 1970-10-20 Siemens Ag Multiplex transmission method
US3894189A (en) * 1972-02-08 1975-07-08 Ericsson Telefon Ab L M Method of operating file gates in an exchange for PCM words
US3794768A (en) * 1972-05-25 1974-02-26 Bell Telephone Labor Inc Cross-office connecting scheme for interconnecting multiplexers and central office terminals
US3922494A (en) * 1973-03-26 1975-11-25 British Minister Of Defence Data signal switching apparatus
US3890469A (en) * 1973-12-04 1975-06-17 Gte Automatic Electric Lab Inc Time division switching system
US3952162A (en) * 1974-05-28 1976-04-20 Texier Alain G Time division digital switching network

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4160128A (en) * 1976-03-31 1979-07-03 Texier Alain G Digital data transmission system providing multipoint connections
US4168401A (en) * 1977-04-05 1979-09-18 Societe Anonyme De Telecommunications Digital switching unit for a multirate time-division multiplex digital switching network
US4244046A (en) * 1978-02-07 1981-01-06 Societe Anonyme De Telecommunications Digital data transmission system providing multipoint communications
WO1980000775A1 (en) * 1978-09-25 1980-04-17 Western Electric Co Time-division switching system for multirate data
US4206322A (en) * 1978-09-25 1980-06-03 Bell Telephone Laboratories, Incorporated Time-division switching system for multirate data
US4246530A (en) * 1978-12-04 1981-01-20 International Telephone And Telegraph Corporation Memory network for TDM switching system
US4512014A (en) * 1979-08-24 1985-04-16 Siemens Aktiengesellschaft Time slot multiplex system for the division multiplexing of digital communication signals
US4330689A (en) * 1980-01-28 1982-05-18 The United States Of America As Represented By The Secretary Of The Navy Multirate digital voice communication processor
US4377860A (en) * 1981-01-05 1983-03-22 American Microsystems, Inc. Bandwidth reduction method and structure for combining voice and data in a PCM channel
US4370648A (en) * 1981-03-31 1983-01-25 Siemens Corporation Synchronizing circuit for use with a telecommunication system
US4654860A (en) * 1983-06-16 1987-03-31 The Boeing Company Spacecraft telemetry regenerator
US4751699A (en) * 1985-09-12 1988-06-14 Andre Tarridec Multiplexing and demultiplexing equipments for a synchronous digital link with variable modulation speed and rate
US4788679A (en) * 1986-09-02 1988-11-29 Nippon Telegraph And Telephone Corporation Packet switch with variable data transfer rate links
US4939723A (en) * 1989-06-07 1990-07-03 Ford Aerospace Corporation Bit-channel multiplexer/demultiplexer
US5842224A (en) * 1989-06-16 1998-11-24 Fenner; Peter R. Method and apparatus for source filtering data packets between networks of differing media
US20050063382A1 (en) * 1989-06-16 2005-03-24 Fenner Investments, Ltd. Packet switching node
US7145906B2 (en) 1989-06-16 2006-12-05 Fenner Investments, Ltd. Packet switching node
US5490258A (en) * 1991-07-29 1996-02-06 Fenner; Peter R. Associative memory for very large key spaces

Also Published As

Publication number Publication date
DE2558599C3 (de) 1979-11-15
DE2558599B2 (it) 1979-03-22
SE431146B (sv) 1984-01-16
NL7515091A (nl) 1976-06-29
FR2296320B1 (it) 1979-03-16
GB1501165A (en) 1978-02-15
CH608676A5 (it) 1979-01-15
JPS5190203A (it) 1976-08-07
DE2558599A1 (de) 1976-07-01
IT1051946B (it) 1981-05-20
FR2296320A1 (fr) 1976-07-23
SE7514591L (sv) 1976-06-28
CA1060976A (en) 1979-08-21

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